Home
last modified time | relevance | path

Searched refs:SCU_HIBERNATE (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-latest/XMCLib/drivers/src/
Dxmc4_scu.c952 SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ((uint32_t)~SCU_HIBERNATE_HDCR_RCS_Msk)) | in XMC_SCU_HIB_SetRtcClockSource()
963 SCU_HIBERNATE->HDCR = (SCU_HIBERNATE->HDCR & ((uint32_t)~SCU_HIBERNATE_HDCR_STDBYSEL_Msk)) | in XMC_SCU_HIB_SetStandbyClockSource()
1255 SCU_HIBERNATE->OSCSICTRL &= (uint32_t)~(SCU_HIBERNATE_OSCSICTRL_PWD_Msk); in XMC_SCU_HIB_EnableInternalSlowClock()
1265 SCU_HIBERNATE->OSCSICTRL |= (uint32_t)SCU_HIBERNATE_OSCSICTRL_PWD_Msk; in XMC_SCU_HIB_DisableInternalSlowClock()
1274 SCU_HIBERNATE->HDCLR = event; in XMC_SCU_HIB_ClearEventStatus()
1283 SCU_HIBERNATE->HDSET = event; in XMC_SCU_HIB_TriggerEvent()
1303 SCU_HIBERNATE->HDCR |= event; in XMC_SCU_HIB_EnableEvent()
1323 SCU_HIBERNATE->HDCR &= ~event; in XMC_SCU_HIB_DisableEvent()
1332 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_HIB_Msk; in XMC_SCU_HIB_EnterHibernateState()
1348 SCU_HIBERNATE->HINTSET = SCU_HIBERNATE_HINTSET_HIBNINT_Msk; in XMC_SCU_HIB_EnterHibernateStateEx()
[all …]
/hal_infineon-latest/XMCLib/devices/XMC4500/Source/
Dsystem_XMC4500.c393 if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) in SystemCoreClockSetup()
400 SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; in SystemCoreClockSetup()
407 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; in SystemCoreClockSetup()
416 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; in SystemCoreClockSetup()
420 } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); in SystemCoreClockSetup()
430 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4700/Source/
Dsystem_XMC4700.c456 if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) in SystemCoreClockSetup()
463 SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; in SystemCoreClockSetup()
470 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; in SystemCoreClockSetup()
479 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; in SystemCoreClockSetup()
483 } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); in SystemCoreClockSetup()
493 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c509 if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL) in SystemCoreClockSetup()
516 SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk; in SystemCoreClockSetup()
523 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk; in SystemCoreClockSetup()
532 SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk; in SystemCoreClockSetup()
536 } while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL); in SystemCoreClockSetup()
546 SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk; in SystemCoreClockSetup()
/hal_infineon-latest/XMCLib/drivers/inc/
Dxmc4_scu.h1869 return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_STDBYSEL_Msk); in XMC_SCU_HIB_GetStdbyClockSource()
1910 return (XMC_SCU_HIB_RTCCLKSRC_t)(SCU_HIBERNATE->HDCR & SCU_HIBERNATE_HDCR_RCS_Msk); in XMC_SCU_HIB_GetRtcClockSource()
3087 return (SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_HIBNOUT_Msk); in XMC_SCU_HIB_GetHibernateControlStatus()
3099 return SCU_HIBERNATE->HDSTAT; in XMC_SCU_HIB_GetEventStatus()
/hal_infineon-latest/XMCLib/devices/XMC4500/Include/
DXMC4500.h16325 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE) macro
/hal_infineon-latest/XMCLib/devices/XMC4700/Include/
DXMC4700.h17580 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE) macro
/hal_infineon-latest/XMCLib/devices/XMC4800/Include/
DXMC4800.h18624 #define SCU_HIBERNATE ((SCU_HIBERNATE_TypeDef *) SCU_HIBERNATE_BASE) macro