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Searched refs:SCB_INTR_TX_MASKED_BLOCKED_Pos (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_scb.h657 #define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_scb_v2.h683 #define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_scb_v4.h758 #define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h3214 #define SCB_INTR_TX_MASKED_BLOCKED_Pos SCB_V2_INTR_TX_MASKED_BLOCKED_Pos macro