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Searched refs:SCB_CTRL_ENABLED_Msk (Results 1 – 13 of 13) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_scb_ezi2c.h555 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk; in Cy_SCB_EZI2C_Enable()
Dcy_scb_common.h2099 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; in Cy_SCB_FwBlockReset()
2105 SCB_CTRL(base) |= (uint32_t) SCB_CTRL_ENABLED_Msk; in Cy_SCB_FwBlockReset()
Dcy_scb_i2c.h1169 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk; in Cy_SCB_I2C_Enable()
Dcy_scb_spi.h952 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk; in Cy_SCB_SPI_Enable()
Dcy_scb_uart.h1001 SCB_CTRL(base) |= SCB_CTRL_ENABLED_Msk; in Cy_SCB_UART_Enable()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_scb.h133 #define SCB_CTRL_ENABLED_Msk 0x80000000UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_scb_v2.h137 #define SCB_CTRL_ENABLED_Msk 0x80000000UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/ip/
Dcyip_scb_v4.h141 #define SCB_CTRL_ENABLED_Msk 0x80000000UL macro
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_scb_ezi2c.c205 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; in Cy_SCB_EZI2C_Disable()
Dcy_scb_spi.c279 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; in Cy_SCB_SPI_Disable()
Dcy_scb_uart.c472 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; in Cy_SCB_UART_Disable()
Dcy_scb_i2c.c228 SCB_CTRL(base) &= (uint32_t) ~SCB_CTRL_ENABLED_Msk; in Cy_SCB_I2C_Disable()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h2668 #define SCB_CTRL_ENABLED_Msk SCB_V2_CTRL_ENABLED_Msk macro