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Searched refs:RAM2_PWR_CTL (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c156 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_PWR_CTL),
277 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
397 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
517 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
638 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
759 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
886 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_PWR_CTL),
1006 /* cpussRam2PwrCtl */ (uint16_t)offsetof(CPUSS_Type, RAM2_PWR_CTL),
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h74 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */ member
Dcyip_cpuss_v2.h92 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h102 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1124 __IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h526 #define CPUSS_RAM2_PWR_CTL ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_PWR_CTL))