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Searched refs:RAM2_CTL0 (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c153 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM2_CTL0),
274 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
394 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
514 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
635 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
756 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
883 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0),
1003 /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_Type, RAM2_CTL0),
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h72 __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ member
Dcyip_cpuss_v2.h90 __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ member
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_cm0plus.c229 CPUSS->RAM2_CTL0 &= ~(0x80000); /* set bit 19 to 0 */ in EnableEcc()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h100 __IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1122 __IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h524 #define CPUSS_RAM2_CTL0 ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_CTL0))