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Searched refs:RAM1_STATUS (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss_v2.h87 __IM uint32_t RAM1_STATUS; /*!< 0x00001384 RAM 1 status */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h97 __IM uint32_t RAM1_STATUS; /*!< 0x00001384 RAM 1 status */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h521 #define CPUSS_RAM1_CTL0 ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_STATUS))