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Searched refs:RAM1_PWR_CTL (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c155 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_PWR_CTL),
276 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
396 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
516 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
637 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
758 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
885 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_PWR_CTL),
1005 /* cpussRam1PwrCtl */ (uint16_t)offsetof(CPUSS_Type, RAM1_PWR_CTL),
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h70 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */ member
Dcyip_cpuss_v2.h88 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h98 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1120 __IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h523 #define CPUSS_RAM1_PWR_CTL ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_PWR_CTL))