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Searched refs:RAM1_CTL0 (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/source/
Dcy_device.c152 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V1_Type, RAM1_CTL0),
273 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
393 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
513 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
634 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
755 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
882 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0),
1002 /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_Type, RAM1_CTL0),
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h68 __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */ member
Dcyip_cpuss_v2.h86 __IOM uint32_t RAM1_CTL0; /*!< 0x00001380 RAM 1 control */ member
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1c/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_cm0plus.c226 CPUSS->RAM1_CTL0 &= ~(0x80000); /* set bit 19 to 0 */ in EnableEcc()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h96 __IOM uint32_t RAM1_CTL0; /*!< 0x00001380 RAM 1 control */ member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1118 __IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */ member