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Searched refs:QCLK_EN (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h825 #define UDB_BCTL_QCLK_EN_0 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U])
826 #define UDB_BCTL_QCLK_EN_1 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U])
827 #define UDB_BCTL_QCLK_EN_2 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U])
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_udb.h227 …__IOM uint32_t QCLK_EN[16]; /*!< 0x00000010 Quadrant Digital Clock Enable Regist… member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h465 #define UDB_BCTL_QCLK_EN_0 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[0U])
466 #define UDB_BCTL_QCLK_EN_1 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[1U])
467 #define UDB_BCTL_QCLK_EN_2 (((UDB_V1_Type *) cy_device->udbBase)->BCTL.QCLK_EN[2U])