1 /***************************************************************************//** 2 * \file cyip_ppc.h 3 * 4 * \brief 5 * PPC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PPC_H_ 28 #define _CYIP_PPC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PPC 34 *******************************************************************************/ 35 36 #define PPC_R_ADDR_SECTION_SIZE 0x00000004UL 37 #define PPC_R_ATT_SECTION_SIZE 0x00000004UL 38 #define PPC_SECTION_SIZE 0x00010000UL 39 40 /** 41 * \brief Region Address (PPC_R_ADDR) 42 */ 43 typedef struct { 44 __IM uint32_t R_ADDR; /*!< 0x00000000 Region Address */ 45 } PPC_R_ADDR_Type; /*!< Size = 4 (0x4) */ 46 47 /** 48 * \brief Region Attribute (PPC_R_ATT) 49 */ 50 typedef struct { 51 __IM uint32_t R_ATT; /*!< 0x00000000 Region Attribute */ 52 } PPC_R_ATT_Type; /*!< Size = 4 (0x4) */ 53 54 /** 55 * \brief Peripheral Protection Controller (PPC) 56 */ 57 typedef struct { 58 __IOM uint32_t CTL; /*!< 0x00000000 PPC Control Registers */ 59 __IM uint32_t STATUS1; /*!< 0x00000004 Status1 Register */ 60 __IM uint32_t STATUS2; /*!< 0x00000008 Status2 Register */ 61 __IOM uint32_t LOCK_MASK; /*!< 0x0000000C Locked Mask */ 62 __IM uint32_t RESERVED[4]; 63 __IOM uint32_t INTR_PPC; /*!< 0x00000020 Interrupt */ 64 __IOM uint32_t INTR_PPC_SET; /*!< 0x00000024 Interrupt set */ 65 __IOM uint32_t INTR_PPC_MASK; /*!< 0x00000028 Interrupt mask */ 66 __IM uint32_t INTR_PPC_MASKED; /*!< 0x0000002C Interrupt masked */ 67 __IM uint32_t RESERVED1[1012]; 68 __IOM uint32_t PC_MASK[1024]; /*!< 0x00001000 Protection Context Mask */ 69 __IOM uint32_t NS_ATT[32]; /*!< 0x00002000 Non-secure attribute */ 70 __IM uint32_t RESERVED2[224]; 71 __IOM uint32_t S_P_ATT[32]; /*!< 0x00002400 Secure Privilege Attribute */ 72 __IM uint32_t RESERVED3[1760]; 73 __IOM uint32_t NS_P_ATT[32]; /*!< 0x00004000 Non-secure Privilege Attribute */ 74 __IM uint32_t RESERVED4[992]; 75 PPC_R_ADDR_Type R_ADDR[1024]; /*!< 0x00005000 Region Address */ 76 PPC_R_ATT_Type R_ATT[1024]; /*!< 0x00006000 Region Attribute */ 77 } PPC_Type; /*!< Size = 28672 (0x7000) */ 78 79 80 /* PPC_R_ADDR.R_ADDR */ 81 #define PPC_R_ADDR_R_ADDR_R_ADDR_Pos 2UL 82 #define PPC_R_ADDR_R_ADDR_R_ADDR_Msk 0xFFFFFFFCUL 83 84 85 /* PPC_R_ATT.R_ATT */ 86 #define PPC_R_ATT_R_ATT_R_SIZE_Pos 24UL 87 #define PPC_R_ATT_R_ATT_R_SIZE_Msk 0x1F000000UL 88 89 90 /* PPC.CTL */ 91 #define PPC_CTL_RESP_CFG_Pos 0UL 92 #define PPC_CTL_RESP_CFG_Msk 0x1UL 93 /* PPC.STATUS1 */ 94 #define PPC_STATUS1_INDEX_Pos 0UL 95 #define PPC_STATUS1_INDEX_Msk 0x3FFUL 96 #define PPC_STATUS1_PC_Pos 12UL 97 #define PPC_STATUS1_PC_Msk 0xF000UL 98 #define PPC_STATUS1_TYPE_Pos 16UL 99 #define PPC_STATUS1_TYPE_Msk 0x70000UL 100 #define PPC_STATUS1_MS_Pos 24UL 101 #define PPC_STATUS1_MS_Msk 0xFF000000UL 102 /* PPC.STATUS2 */ 103 #define PPC_STATUS2_ADDR_Pos 0UL 104 #define PPC_STATUS2_ADDR_Msk 0xFFFFFFFFUL 105 /* PPC.LOCK_MASK */ 106 #define PPC_LOCK_MASK_LOCK_MASK_Pos 0UL 107 #define PPC_LOCK_MASK_LOCK_MASK_Msk 0xFFFFFFFFUL 108 /* PPC.INTR_PPC */ 109 #define PPC_INTR_PPC_SECURE_VIO_Pos 0UL 110 #define PPC_INTR_PPC_SECURE_VIO_Msk 0x1UL 111 /* PPC.INTR_PPC_SET */ 112 #define PPC_INTR_PPC_SET_SECURE_VIO_Pos 0UL 113 #define PPC_INTR_PPC_SET_SECURE_VIO_Msk 0x1UL 114 /* PPC.INTR_PPC_MASK */ 115 #define PPC_INTR_PPC_MASK_SECURE_VIO_Pos 0UL 116 #define PPC_INTR_PPC_MASK_SECURE_VIO_Msk 0x1UL 117 /* PPC.INTR_PPC_MASKED */ 118 #define PPC_INTR_PPC_MASKED_SECURE_VIO_Pos 0UL 119 #define PPC_INTR_PPC_MASKED_SECURE_VIO_Msk 0x1UL 120 /* PPC.PC_MASK */ 121 #define PPC_PC_MASK_PC_MASK_Pos 0UL 122 #define PPC_PC_MASK_PC_MASK_Msk 0xFFFFFFFFUL 123 /* PPC.NS_ATT */ 124 #define PPC_NS_ATT_NS_Pos 0UL 125 #define PPC_NS_ATT_NS_Msk 0xFFFFFFFFUL 126 /* PPC.S_P_ATT */ 127 #define PPC_S_P_ATT_S_P_Pos 0UL 128 #define PPC_S_P_ATT_S_P_Msk 0xFFFFFFFFUL 129 /* PPC.NS_P_ATT */ 130 #define PPC_NS_P_ATT_NS_P_Pos 0UL 131 #define PPC_NS_P_ATT_NS_P_Msk 0xFFFFFFFFUL 132 133 134 #endif /* _CYIP_PPC_H_ */ 135 136 137 /* [] END OF FILE */ 138
