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Searched refs:PLL_PDIV (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/XMCLib/devices/XMC4800/Source/
Dsystem_XMC4800.c179 #define PLL_PDIV (1U) macro
184 #define PLL_PDIV (1U) macro
189 #define PLL_PDIV (1U) macro
198 #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
199 #define VCO_INPUT (OSCHP_FREQUENCY / (PLL_PDIV + 1UL))
202 #define PLL_PDIV (1U) macro
206 #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
207 #define VCO_INPUT (OFI_FREQUENCY / (PLL_PDIV + 1UL))
597 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
640 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
[all …]
/hal_infineon-latest/XMCLib/devices/XMC4700/Source/
Dsystem_XMC4700.c162 #define PLL_PDIV (1U) macro
167 #define PLL_PDIV (1U) macro
172 #define PLL_PDIV (1U) macro
181 #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
184 #define PLL_PDIV (1U) macro
188 #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
540 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
581 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
587 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
593 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
[all …]
/hal_infineon-latest/XMCLib/devices/XMC4500/Source/
Dsystem_XMC4500.c158 #define PLL_PDIV (1U) macro
163 #define PLL_PDIV (1U) macro
168 #define PLL_PDIV (1U) macro
177 #define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
181 #define PLL_PDIV (1U) macro
185 #define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
478 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
525 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
536 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()
547 (PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos)); in SystemCoreClockSetup()