1 /***************************************************************************//** 2 * \file cyip_lvdsss.h 3 * 4 * \brief 5 * LVDSSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_LVDSSS_H_ 28 #define _CYIP_LVDSSS_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * LVDSSS 34 *******************************************************************************/ 35 36 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_SECTION_SIZE 0x00000020UL 37 #define LVDSSS_LVDS_THREAD_SECTION_SIZE 0x00000200UL 38 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_SECTION_SIZE 0x00000010UL 39 #define LVDSSS_LVDS_GPIF_LEFT_SECTION_SIZE 0x00001000UL 40 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_SECTION_SIZE 0x00000010UL 41 #define LVDSSS_LVDS_GPIF_RIGHT_SECTION_SIZE 0x00001000UL 42 #define LVDSSS_LVDS_GPIF_SECTION_SIZE 0x00003000UL 43 #define LVDSSS_LVDS_AFE_SECTION_SIZE 0x00000800UL 44 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_SECTION_SIZE 0x00000080UL 45 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_SECTION_SIZE 0x00000100UL 46 #define LVDSSS_LVDS_ADAPTER_DMA_SECTION_SIZE 0x00010000UL 47 #define LVDSSS_LVDS_SECTION_SIZE 0x00040000UL 48 #define LVDSSS_SECTION_SIZE 0x00040000UL 49 50 /** 51 * \brief LVDS Low power and Wakeup Interrupt registers (LVDSSS_LVDS_LVDS_LOW_PWR_INTR) 52 */ 53 typedef struct { 54 __IOM uint32_t LVDS_WAKEUP_INTR; /*!< 0x00000000 LVDS_WAKEUP Interrupt Request Register */ 55 __IOM uint32_t LVDS_WAKEUP_INTR_MASK; /*!< 0x00000004 LVDS_WAKEUP Interrupt Mask Register */ 56 __IM uint32_t LVDS_WAKEUP_INTR_MASKED; /*!< 0x00000008 LVDS_WAKEUP Interrupt Generator */ 57 __IOM uint32_t LVDS_WAKEUP_INTR_SET; /*!< 0x0000000C LVDS_WAKEUP Interrupt Set Register */ 58 __IOM uint32_t LOW_PWR_CTL[2]; /*!< 0x00000010 Low power mode control register */ 59 __IM uint32_t RESERVED[2]; 60 } LVDSSS_LVDS_LVDS_LOW_PWR_INTR_V1_Type; /*!< Size = 32 (0x20) */ 61 62 /** 63 * \brief Set of registers for a thread (LVDSSS_LVDS_THREAD) 64 */ 65 typedef struct { 66 __IOM uint32_t GPIF_DATA_CTRL; /*!< 0x00000000 Data Control Register */ 67 __IM uint32_t GPIF_INGRESS_DATA_WORD0; /*!< 0x00000004 Socket Ingress Data */ 68 __IM uint32_t GPIF_INGRESS_DATA_WORD1; /*!< 0x00000008 Socket Ingress Data */ 69 __IM uint32_t GPIF_INGRESS_DATA_WORD2; /*!< 0x0000000C Socket Ingress Data */ 70 __IM uint32_t GPIF_INGRESS_DATA_WORD3; /*!< 0x00000010 Socket Ingress Data */ 71 __IOM uint32_t GPIF_EGRESS_DATA_WORD0; /*!< 0x00000014 Socket Egress Data */ 72 __IOM uint32_t GPIF_EGRESS_DATA_WORD1; /*!< 0x00000018 Socket Egress Data */ 73 __IM uint32_t GPIF_INGRESS_ADDRESS; /*!< 0x0000001C Thread Ingress Address */ 74 __IOM uint32_t GPIF_EGRESS_ADDRESS; /*!< 0x00000020 Thread Egress Address */ 75 __IOM uint32_t GPIF_THREAD_CONFIG; /*!< 0x00000024 Thread Configuration Register */ 76 __IM uint32_t RESERVED; 77 __IM uint32_t VARW0; /*!< 0x0000002C Variable Register */ 78 __IM uint32_t VARW1; /*!< 0x00000030 Variable Register */ 79 __IM uint32_t PTSSS; /*!< 0x00000034 PTS snapshot register */ 80 __IM uint32_t SCRSS_DW0; /*!< 0x00000038 SCR snapshot register */ 81 __IM uint32_t SCRSS_DW1; /*!< 0x0000003C SCR snapshot register */ 82 __IM uint32_t HDR_FLGS; /*!< 0x00000040 Header Flags */ 83 __IM uint32_t RESERVED1[3]; 84 __IM uint32_t EVC_VAR0_DW0; /*!< 0x00000050 Event Count Variable0 */ 85 __IM uint32_t EVC_VAR0_DW1; /*!< 0x00000054 Event Count Variable0 */ 86 __IM uint32_t EVC_VAR1_DW0; /*!< 0x00000058 Event Count Variable1 */ 87 __IM uint32_t EVC_VAR1_DW1; /*!< 0x0000005C Event Count Variable1 */ 88 __IM uint32_t PLC_DW0; /*!< 0x00000060 Payload Count register */ 89 __IM uint32_t PLC_DW1; /*!< 0x00000064 Payload Count register */ 90 __IOM uint32_t PAYLOAD_CFG; /*!< 0x00000068 Payload Config register */ 91 __IM uint32_t RESERVED2; 92 __IOM uint32_t DCRC_CONFIG; /*!< 0x00000070 Data CRC Configuration register */ 93 __IOM uint32_t DCRC; /*!< 0x00000074 Data CRC */ 94 __IOM uint32_t DCRC_STS; /*!< 0x00000078 Data CRC status */ 95 __IM uint32_t RESERVED3; 96 __IOM uint32_t MCRC_CONFIG; /*!< 0x00000080 MetaData(or Header) CRC Configuration register */ 97 __IOM uint32_t MCRC; /*!< 0x00000084 MetaData CRC */ 98 __IOM uint32_t THREAD_DMA_INTF_CFG; /*!< 0x00000088 Thread controller DMA interface configuration */ 99 __IM uint32_t RESERVED4; 100 __IOM uint32_t MD0_CTRL; /*!< 0x00000090 Metadata-0 Control word */ 101 __IOM uint32_t MD1_CTRL; /*!< 0x00000094 Metadata-1 Control word */ 102 __IOM uint32_t MD2_CTRL; /*!< 0x00000098 Metadata-2 Control word */ 103 __IOM uint32_t MD3_CTRL; /*!< 0x0000009C Metadata-3 Control word */ 104 __IM uint32_t RESERVED5[88]; 105 } LVDSSS_LVDS_THREAD_V1_Type; /*!< Size = 512 (0x200) */ 106 107 /** 108 * \brief GPIF Waveform registers (LVDSSS_LVDS_GPIF_LEFT_WAVEFORM) 109 */ 110 typedef struct { 111 __IOM uint32_t WAVEFORM0; /*!< 0x00000000 GPIF state definition */ 112 __IOM uint32_t WAVEFORM1; /*!< 0x00000004 GPIF state definition */ 113 __IOM uint32_t WAVEFORM2; /*!< 0x00000008 GPIF state definition */ 114 __IOM uint32_t WAVEFORM3; /*!< 0x0000000C GPIF state definition */ 115 } LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_V1_Type; /*!< Size = 16 (0x10) */ 116 117 /** 118 * \brief GPIF State Machine Left Waveform memory (LVDSSS_LVDS_GPIF_LEFT) 119 */ 120 typedef struct { 121 LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_V1_Type WAVEFORM[256]; /*!< 0x00000000 GPIF Waveform registers */ 122 } LVDSSS_LVDS_GPIF_LEFT_V1_Type; /*!< Size = 4096 (0x1000) */ 123 124 /** 125 * \brief GPIF Waveform registers (LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM) 126 */ 127 typedef struct { 128 __IOM uint32_t WAVEFORM0; /*!< 0x00000000 GPIF state definition */ 129 __IOM uint32_t WAVEFORM1; /*!< 0x00000004 GPIF state definition */ 130 __IOM uint32_t WAVEFORM2; /*!< 0x00000008 GPIF state definition */ 131 __IOM uint32_t WAVEFORM3; /*!< 0x0000000C GPIF state definition */ 132 } LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_V1_Type; /*!< Size = 16 (0x10) */ 133 134 /** 135 * \brief GPIF State Machine Right Waveform memory. (LVDSSS_LVDS_GPIF_RIGHT) 136 */ 137 typedef struct { 138 LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_V1_Type WAVEFORM[256]; /*!< 0x00000000 GPIF Waveform registers */ 139 } LVDSSS_LVDS_GPIF_RIGHT_V1_Type; /*!< Size = 4096 (0x1000) */ 140 141 /** 142 * \brief GPIF-II Configuration Registers (LVDSSS_LVDS_GPIF) 143 */ 144 typedef struct { 145 __IOM uint32_t GPIF_CONFIG; /*!< 0x00000000 GPIF Configuration Register */ 146 __IOM uint32_t GPIF_BUS_CONFIG; /*!< 0x00000004 Bus Configuration Register */ 147 __IOM uint32_t GPIF_BUS_CONFIG2; /*!< 0x00000008 Bus Configuration Register #2 */ 148 __IOM uint32_t GPIF_AD_CONFIG; /*!< 0x0000000C Address/Data configuration register */ 149 __IOM uint32_t GPIF_CTL_FUNC0; /*!< 0x00000010 CTL pin functional usage register #0 */ 150 __IOM uint32_t GPIF_CTL_FUNC1; /*!< 0x00000014 CTL pin functional usage register #1 */ 151 __IOM uint32_t GPIF_CTL_FUNC2; /*!< 0x00000018 CTL pin functional usage register #2 */ 152 __IOM uint32_t GPIF_CTL_FUNC3; /*!< 0x0000001C CTL pin functional usage register #3 */ 153 __IOM uint32_t GPIF_CTL_FUNC4; /*!< 0x00000020 CTL pin functional usage register #4 */ 154 __IM uint32_t GPIF_STATUS; /*!< 0x00000024 GPIF Status Register */ 155 __IM uint32_t RESERVED[2]; 156 __IOM uint32_t GPIF_INTR; /*!< 0x00000030 GPIF Interrupt Request Register */ 157 __IOM uint32_t GPIF_INTR_MASK; /*!< 0x00000034 GPIF Interrupt Mask Register */ 158 __IM uint32_t GPIF_INTR_MASKED; /*!< 0x00000038 GPIF Interrupt Generator */ 159 __IOM uint32_t GPIF_INTR_SET; /*!< 0x0000003C GPIF Interrupt Set Register */ 160 __IM uint32_t GPIF_ERROR; /*!< 0x00000040 GPIF Error Register */ 161 __IM uint32_t RESERVED1[3]; 162 __IOM uint32_t GPIF_CTRL_BUS_DIRECTION[20]; /*!< 0x00000050 Control Bus in/out direction */ 163 __IM uint32_t RESERVED2[4]; 164 __IOM uint32_t GPIF_CTRL_BUS_DEFAULT; /*!< 0x000000B0 Control bus default values */ 165 __IOM uint32_t GPIF_CTRL_BUS_POLARITY; /*!< 0x000000B4 Control bus signal polarity */ 166 __IOM uint32_t GPIF_CTRL_BUS_TOGGLE; /*!< 0x000000B8 Control bus output toggle mode */ 167 __IM uint32_t RESERVED3[17]; 168 __IOM uint32_t GPIF_CTRL_BUS_SELECT[20]; /*!< 0x00000100 Control bus connection matrix register */ 169 __IM uint32_t RESERVED4[4]; 170 __IOM uint32_t GPIF_CTRL_COUNT_CONFIG; /*!< 0x00000160 Control counter configuration */ 171 __IOM uint32_t GPIF_CTRL_COUNT_RESET; /*!< 0x00000164 Control counter reset register */ 172 __IOM uint32_t GPIF_CTRL_COUNT_LIMIT; /*!< 0x00000168 Control counter limit register */ 173 __IM uint32_t RESERVED5; 174 __IOM uint32_t GPIF_ADDR_COUNT_CONFIG; /*!< 0x00000170 Address counter configuration */ 175 __IOM uint32_t GPIF_ADDR_COUNT_RESET; /*!< 0x00000174 Address counter reset register */ 176 __IOM uint32_t GPIF_ADDR_COUNT_LIMIT; /*!< 0x00000178 Address counter limit register */ 177 __IM uint32_t RESERVED6; 178 __IOM uint32_t GPIF_STATE_COUNT_CONFIG; /*!< 0x00000180 State counter configuration */ 179 __IOM uint32_t GPIF_STATE_COUNT_LIMIT; /*!< 0x00000184 State counter limit register */ 180 __IM uint32_t RESERVED7[2]; 181 __IOM uint32_t GPIF_DATA_COUNT_CONFIG; /*!< 0x00000190 Data counter configuration */ 182 __IOM uint32_t GPIF_DATA_COUNT_RESET_LSB; /*!< 0x00000194 Data counter reset register */ 183 __IM uint32_t RESERVED8; 184 __IOM uint32_t GPIF_DATA_COUNT_RESET_MSB; /*!< 0x0000019C Data counter reset register */ 185 __IOM uint32_t GPIF_DATA_COUNT_LIMIT_LSB; /*!< 0x000001A0 Data counter limit register */ 186 __IOM uint32_t GPIF_DATA_COUNT_LIMIT_MSB; /*!< 0x000001A4 Data counter limit register */ 187 __IOM uint32_t GPIF_CTRL_COMP_VALUE; /*!< 0x000001A8 Control comparator value */ 188 __IOM uint32_t GPIF_CTRL_COMP_MASK; /*!< 0x000001AC Control comparator mask */ 189 __IOM uint32_t GPIF_DATA_COMP_VALUE_WORD0; /*!< 0x000001B0 Data comparator value */ 190 __IOM uint32_t GPIF_DATA_COMP_VALUE_WORD1; /*!< 0x000001B4 Data comparator value */ 191 __IOM uint32_t GPIF_DATA_COMP_VALUE_WORD2; /*!< 0x000001B8 Data comparator value */ 192 __IOM uint32_t GPIF_DATA_COMP_VALUE_WORD3; /*!< 0x000001BC Data comparator value */ 193 __IM uint32_t RESERVED9[4]; 194 __IOM uint32_t GPIF_DATA_COMP_MASK_WORD0; /*!< 0x000001D0 Data comparator mask */ 195 __IOM uint32_t GPIF_DATA_COMP_MASK_WORD1; /*!< 0x000001D4 Data comparator mask */ 196 __IOM uint32_t GPIF_DATA_COMP_MASK_WORD2; /*!< 0x000001D8 Data comparator mask */ 197 __IOM uint32_t GPIF_DATA_COMP_MASK_WORD3; /*!< 0x000001DC Data comparator mask */ 198 __IOM uint32_t GPIF_ADDR_COMP_VALUE; /*!< 0x000001E0 Address comparator value */ 199 __IOM uint32_t GPIF_ADDR_COMP_MASK; /*!< 0x000001E4 Address comparator mask */ 200 __IM uint32_t RESERVED10[2]; 201 __IM uint32_t GPIF_LAMBDA_STAT0; /*!< 0x000001F0 Lambda Status Register */ 202 __IM uint32_t GPIF_LAMBDA_STAT1; /*!< 0x000001F4 Lambda Status Register */ 203 __IM uint32_t GPIF_ALPHA_STAT; /*!< 0x000001F8 Alpha Status Register */ 204 __IM uint32_t GPIF_BETA_STAT; /*!< 0x000001FC Beta Status Register */ 205 __IOM uint32_t GPIF_WAVEFORM_CTRL_STAT; /*!< 0x00000200 Waveform program control */ 206 __IOM uint32_t GPIF_WAVEFORM_SWITCH; /*!< 0x00000204 Waveform switch control */ 207 __IOM uint32_t GPIF_WAVEFORM_SWITCH_TIMEOUT; /*!< 0x00000208 Waveform timeout register */ 208 __IM uint32_t RESERVED11; 209 __IOM uint32_t GPIF_CRC_CALC_CONFIG; /*!< 0x00000210 CRC Calculate Configuration Register */ 210 __IM uint32_t RESERVED12; 211 __IOM uint32_t GPIF_BETA_DEASSERT; /*!< 0x00000218 Beta Deassert Register */ 212 __IM uint32_t RESERVED13; 213 __IOM uint32_t GPIF_FUNCTION[32]; /*!< 0x00000220 Transition Function Registers */ 214 __IM uint32_t RESERVED14[4]; 215 __IOM uint32_t LINK_IDLE_CFG; /*!< 0x000002B0 Link Idle Config register */ 216 __IM uint32_t RESERVED15[3]; 217 __IOM uint32_t LVCMOS_CLK_OUT_CFG; /*!< 0x000002C0 lvcmos clock out config register */ 218 __IM uint32_t RESERVED16[847]; 219 LVDSSS_LVDS_GPIF_LEFT_V1_Type LEFT; /*!< 0x00001000 GPIF State Machine Left Waveform memory */ 220 LVDSSS_LVDS_GPIF_RIGHT_V1_Type RIGHT; /*!< 0x00002000 GPIF State Machine Right Waveform memory. */ 221 } LVDSSS_LVDS_GPIF_V1_Type; /*!< Size = 12288 (0x3000) */ 222 223 /** 224 * \brief Phy Configuration Registers (LVDSSS_LVDS_AFE) 225 */ 226 typedef struct { 227 __IOM uint32_t DLL_DFTLPF; /*!< 0x00000000 DLL Low-Pass Filter Config Register */ 228 __IOM uint32_t DLL_CONFIG; /*!< 0x00000004 DLL Configuration Register */ 229 __IM uint32_t DLL_STATUS; /*!< 0x00000008 DLL Status Register */ 230 __IOM uint32_t DLL_M_CONFIG; /*!< 0x0000000C Master DLL Config Register */ 231 __IM uint32_t DLL_M_STATUS; /*!< 0x00000010 Master DLL Status Register */ 232 __IOM uint32_t DLL_S_CONFIG[12]; /*!< 0x00000014 Slave DLL Configuration */ 233 __IM uint32_t RESERVED[3]; 234 __IM uint32_t DLL_S_STATUS[12]; /*!< 0x00000050 Slave DLL Status */ 235 __IOM uint32_t GENERAL_LICIO_CIO; /*!< 0x00000080 LICIO_CIO Config reg (common for all pads) */ 236 __IOM uint32_t LICIO_CIO[27]; /*!< 0x00000084 LICIO_CIO Config reg (per pad) */ 237 __IM uint32_t RESERVED1[4]; 238 __IOM uint32_t GENERAL_LICIO_LI; /*!< 0x00000100 LICIO_LI Config reg (common for all pads) */ 239 __IOM uint32_t LICIO_LI[10]; /*!< 0x00000104 LICIO_LI Config reg (per pad) */ 240 __IM uint32_t RESERVED2; 241 __IOM uint32_t LICIO_VSSIO_IREF; /*!< 0x00000130 LICIO_VSSIO_IREF Config reg */ 242 __IM uint32_t LICIO_LI_OUT_STATUS; /*!< 0x00000134 LICO_LI pad Rx output status */ 243 __IOM uint32_t PLL_CONFIG; /*!< 0x00000138 PLL Configuration register */ 244 __IOM uint32_t PLL_CONFIG_2; /*!< 0x0000013C PLL Configuration register2 */ 245 __IM uint32_t PLL_STATUS; /*!< 0x00000140 PLL Status Register */ 246 __IOM uint32_t REG_1P25; /*!< 0x00000144 REG1P25 Config reg */ 247 __IOM uint32_t RX[10]; /*!< 0x00000148 LVDS RX Configuration Registers */ 248 __IOM uint32_t GENERAL_RX; /*!< 0x00000170 General RX Configuration Register */ 249 __IOM uint32_t GENERAL_RX_LVCMOS; /*!< 0x00000174 General LVCMOS RX Configuration Register */ 250 __IOM uint32_t RX_LVCMOS[26]; /*!< 0x00000178 LVCMOS RX Configuration Registers */ 251 __IM uint32_t RESERVED3[9]; 252 __IOM uint32_t PRBS_GEN; /*!< 0x00000204 State counter limit register */ 253 __IOM uint32_t PHY_GENERAL_CONFIG; /*!< 0x00000208 Phy Configuration register */ 254 __IM uint32_t PHY_GENERAL_STATUS_1; /*!< 0x0000020C Phy Status register (Loopback Status Lanes) */ 255 __IM uint32_t PHY_GENERAL_STATUS_2; /*!< 0x00000210 Phy Status register */ 256 __IOM uint32_t PHY_INTR; /*!< 0x00000214 Phy Interrupt Register */ 257 __IOM uint32_t PHY_INTR_MASK; /*!< 0x00000218 Phy Interrupt Mask Register */ 258 __IM uint32_t PHY_INTR_MASKED; /*!< 0x0000021C Phy Interrupt Masked Register */ 259 __IOM uint32_t PHY_INTR_SET; /*!< 0x00000220 Phy Interrupt Set Register */ 260 __IOM uint32_t PHY_TRAIN_CONFIG; /*!< 0x00000224 Phy Training Mode Config register */ 261 __IOM uint32_t PHY_ADC_CONFIG; /*!< 0x00000228 ADC config register */ 262 __IOM uint32_t PHY_DDFT_MUX_SEL; /*!< 0x0000022C Digital Mux Select Register */ 263 __IOM uint32_t LICIO_VCCD_V1P1; /*!< 0x00000230 LICIO_VCCD_V1P1 Config reg */ 264 __IOM uint32_t PHY_GPIO[26]; /*!< 0x00000234 GPIO Config register */ 265 __IM uint32_t RESERVED4[26]; 266 __IOM uint32_t PHY_GPIO_INTR_CFG; /*!< 0x00000304 GPIO Interrupt Config register */ 267 __IM uint32_t RESERVED5; 268 __IOM uint32_t PHY_GENERAL_CONFIG_2; /*!< 0x0000030C Phy Configuration Register2 */ 269 __IM uint32_t PRBS_STATUS; /*!< 0x00000310 Loopback error rate register */ 270 __IOM uint32_t LVDS_STATUS_MONITOR[10]; /*!< 0x00000314 LVDS Pin status monitor */ 271 __IM uint32_t RESERVED6; 272 __IM uint32_t PHY_ADC_STATUS; /*!< 0x00000340 ADC status register */ 273 __IOM uint32_t FRM_CLK_GLITCH_FILTER; /*!< 0x00000344 Frame clock glitch filter configuration register */ 274 __IM uint32_t RESERVED7[46]; 275 __IOM uint32_t LICIO_CIO_CTRL_DS; /*!< 0x00000400 LICIO_CIO control pad DS/SR register */ 276 __IOM uint32_t LICIO_CIO_DATA_DS[17]; /*!< 0x00000404 LICIO_CIO Data/Clk pad DS/SR register */ 277 __IM uint32_t RESERVED8[45]; 278 __IOM uint32_t DLY_CELL_LOAD; /*!< 0x000004FC Delay cell Load control register */ 279 __IOM uint32_t SAR_CLK_FREQ_CFG; /*!< 0x00000500 SAR clock frequency configuration */ 280 __IM uint32_t STUCK_AT_CNTRS; /*!< 0x00000504 Stuck-at fault counters */ 281 __IOM uint32_t STUCK_CNTR_RST_CTL; /*!< 0x00000508 Stuck-at fault counters Reset control register */ 282 __IM uint32_t RESERVED9; 283 __IOM uint32_t STUCK_CNTR_SIG_SEL_0; /*!< 0x00000510 Stuck at fault counter signal select */ 284 __IOM uint32_t STUCK_CNTR_SIG_SEL_1; /*!< 0x00000514 Stuck at fault counter signal select */ 285 __IM uint32_t RESERVED10[2]; 286 __IOM uint32_t CTL_PIN_SDLL_CFG[7]; /*!< 0x00000520 Control pin slave dll monitor config */ 287 __IM uint32_t RESERVED11; 288 __IM uint32_t LVDS_BER_STATUS; /*!< 0x00000540 LVDS rx_data_channel instance ber status */ 289 __IM uint32_t RESERVED12[175]; 290 } LVDSSS_LVDS_AFE_V1_Type; /*!< Size = 2048 (0x800) */ 291 292 /** 293 * \brief Socket Registers (LVDSSS_LVDS_ADAPTER_DMA_SCK) 294 */ 295 typedef struct { 296 __IOM uint32_t SCK_DSCR; /*!< 0x00000000 Descriptor Chain Pointer */ 297 __IOM uint32_t SCK_SIZE; /*!< 0x00000004 Transfer Size Register */ 298 __IOM uint32_t SCK_COUNT; /*!< 0x00000008 Transfer Count Register */ 299 __IOM uint32_t SCK_STATUS; /*!< 0x0000000C Socket Status Register */ 300 __IOM uint32_t SCK_INTR; /*!< 0x00000010 Socket Interrupt Request Register */ 301 __IOM uint32_t SCK_INTR_MASK; /*!< 0x00000014 Socket Interrupt Mask Register */ 302 __IM uint32_t RESERVED[2]; 303 __IOM uint32_t DSCR_BUFFER; /*!< 0x00000020 Descriptor buffer base address register */ 304 __IOM uint32_t DSCR_SYNC; /*!< 0x00000024 Descriptor synchronization pointers register */ 305 __IOM uint32_t DSCR_CHAIN; /*!< 0x00000028 Descriptor Chain Pointers Register */ 306 __IOM uint32_t DSCR_SIZE; /*!< 0x0000002C Descriptor Size Register */ 307 __IM uint32_t RESERVED1[19]; 308 __OM uint32_t EVENT; /*!< 0x0000007C Event Communication Register */ 309 } LVDSSS_LVDS_ADAPTER_DMA_SCK_V1_Type; /*!< Size = 128 (0x80) */ 310 311 /** 312 * \brief General DMA Registers (LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL) 313 */ 314 typedef struct { 315 __IM uint32_t SCK_INTR; /*!< 0x00000000 Socket Interrupt Request Register */ 316 __IM uint32_t RESERVED[59]; 317 __IOM uint32_t ADAPTER_CTRL; /*!< 0x000000F0 Adapter Control Register */ 318 __IM uint32_t ADAPTER_DEBUG; /*!< 0x000000F4 Adapter Debug Observation Register */ 319 __IOM uint32_t ADAPTER_CONF; /*!< 0x000000F8 Adapter Configuration Register */ 320 __IM uint32_t ADAPTER_STATUS; /*!< 0x000000FC Adapter Global Status Fields */ 321 } LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_V1_Type; /*!< Size = 256 (0x100) */ 322 323 /** 324 * \brief LVDS Adapter Registers 325 0x1_0000 is for Adapter-0 and 0x2_0000 is for Adapter-1 (LVDSSS_LVDS_ADAPTER_DMA) 326 */ 327 typedef struct { 328 __IM uint32_t RESERVED[8192]; 329 LVDSSS_LVDS_ADAPTER_DMA_SCK_V1_Type SCK[16]; /*!< 0x00008000 Socket Registers */ 330 __IM uint32_t RESERVED1[7616]; 331 LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_V1_Type SCK_GBL; /*!< 0x0000FF00 General DMA Registers */ 332 } LVDSSS_LVDS_ADAPTER_DMA_V1_Type; /*!< Size = 65536 (0x10000) */ 333 334 /** 335 * \brief LVDS IP register map (LVDSSS_LVDS) 336 */ 337 typedef struct { 338 __IOM uint32_t CTL; /*!< 0x00000000 IP Control Register */ 339 __IOM uint32_t LINK_CONFIG[2]; /*!< 0x00000004 Link Configuration Register */ 340 __IOM uint32_t THREAD_INTLV_CTL; /*!< 0x0000000C Thread interleave control register */ 341 __IOM uint32_t LVDS_INTR_WD0; /*!< 0x00000010 LVDS Interrupt Request Register */ 342 __IOM uint32_t LVDS_INTR_WD1; /*!< 0x00000014 LVDS Interrupt Request Register */ 343 __IM uint32_t RESERVED[2]; 344 __IOM uint32_t LVDS_INTR_MASK_WD0; /*!< 0x00000020 LVDS Interrupt Mask Register */ 345 __IOM uint32_t LVDS_INTR_MASK_WD1; /*!< 0x00000024 LVDS Interrupt Mask Register */ 346 __IM uint32_t RESERVED1[2]; 347 __IM uint32_t LVDS_INTR_MASKED_WD0; /*!< 0x00000030 LVDS Interrupt Generator */ 348 __IM uint32_t LVDS_INTR_MASKED_WD1; /*!< 0x00000034 LVDS Interrupt Generator */ 349 __IM uint32_t RESERVED2[2]; 350 __IOM uint32_t LVDS_INTR_SET_WD0; /*!< 0x00000040 LVDS Interrupt Set Register */ 351 __IOM uint32_t LVDS_INTR_SET_WD1; /*!< 0x00000044 LVDS Interrupt Set Register */ 352 __IM uint32_t RESERVED3[2]; 353 __IM uint32_t LVDS_ERROR; /*!< 0x00000050 LVDS Error Indicator Register */ 354 __IOM uint32_t LVDS_EOP_EOT; /*!< 0x00000054 LVDS EOP/EOT configuration */ 355 __IOM uint32_t LANE_FIFO_STS[2]; /*!< 0x00000058 Lane fifo status Register */ 356 __IOM uint32_t GPIF_CLK_SEL[2]; /*!< 0x00000060 GPIF Clock selection Register */ 357 __IM uint32_t RESERVED4; 358 __IOM uint32_t USB_FRM_CNTR_CFG; /*!< 0x0000006C USB frame counter config */ 359 __IM uint32_t TIME_STAMP_CLK_DW0; /*!< 0x00000070 Timestamp nanosecond counter */ 360 __IM uint32_t TIME_STAMP_CLK_DW1; /*!< 0x00000074 Timestamp nanosecond counter */ 361 __IM uint32_t RESERVED5[2]; 362 __IOM uint32_t SCRSS_VALUE_CFG[2]; /*!< 0x00000080 SCRSS value configuration select */ 363 __IM uint32_t RESERVED6[2]; 364 __IOM uint32_t TRAINING_BLK_CFG; /*!< 0x00000090 Training block configuration */ 365 __IOM uint32_t TRAINING_BLK; /*!< 0x00000094 Training block sequence bytes */ 366 __IOM uint32_t LINK_TRAINING_STS[2]; /*!< 0x00000098 Training block detection status register */ 367 __IOM uint32_t DDFT_MUX_SEL; /*!< 0x000000A0 Debug Mux select */ 368 __IOM uint32_t GPIO_DDFT_MUX_SEL; /*!< 0x000000A4 Debug Mux select */ 369 __IOM uint32_t LOOPBACK_CFG; /*!< 0x000000A8 Loopback Configuration register */ 370 __IM uint32_t RESERVED7; 371 __IOM uint32_t LVDS_CHAR_CFG[2]; /*!< 0x000000B0 LVDS lanes characterisation config register */ 372 __IOM uint32_t CLK_GATE_DIS; /*!< 0x000000B8 Thread controller Clock gate disable config register */ 373 __IOM uint32_t VERSION_SEL; /*!< 0x000000BC lvds ip version select */ 374 LVDSSS_LVDS_LVDS_LOW_PWR_INTR_V1_Type LVDS_LOW_PWR_INTR; /*!< 0x000000C0 LVDS Low power and Wakeup Interrupt registers */ 375 __IM uint32_t RESERVED8[8]; 376 __IOM uint32_t TH0_TH1_METADATA_RAM[64]; /*!< 0x00000100 Metadata Memory */ 377 __IOM uint32_t TH2_TH3_METADATA_RAM[64]; /*!< 0x00000200 Metadata Memory */ 378 __IM uint32_t RESERVED9[64]; 379 LVDSSS_LVDS_THREAD_V1_Type THREAD[4]; /*!< 0x00000400 Set of registers for a thread */ 380 __IM uint32_t RESERVED10[256]; 381 LVDSSS_LVDS_GPIF_V1_Type GPIF[2]; /*!< 0x00001000 GPIF-II Configuration Registers */ 382 LVDSSS_LVDS_AFE_V1_Type AFE[2]; /*!< 0x00007000 Phy Configuration Registers */ 383 __IM uint32_t RESERVED11[8192]; 384 LVDSSS_LVDS_ADAPTER_DMA_V1_Type ADAPTER_DMA[2]; /*!< 0x00010000 LVDS Adapter Registers 0x1_0000 is for Adapter-0 and 0x2_0000 385 is for Adapter-1 */ 386 __IM uint32_t RESERVED12[16384]; 387 } LVDSSS_LVDS_V1_Type; /*!< Size = 262144 (0x40000) */ 388 389 /** 390 * \brief LVDS IP Registers (LVDSSS) 391 */ 392 typedef struct { 393 LVDSSS_LVDS_V1_Type LVDS; /*!< 0x00000000 LVDS IP register map */ 394 } LVDSSS_V1_Type; /*!< Size = 262144 (0x40000) */ 395 396 397 /* LVDSSS_LVDS_LVDS_LOW_PWR_INTR.LVDS_WAKEUP_INTR */ 398 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_LNK0_L3_EXIT_Pos 0UL 399 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_LNK0_L3_EXIT_Msk 0x1UL 400 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_LNK1_L3_EXIT_Pos 1UL 401 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_LNK1_L3_EXIT_Msk 0x2UL 402 /* LVDSSS_LVDS_LVDS_LOW_PWR_INTR.LVDS_WAKEUP_INTR_MASK */ 403 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASK_LNK0_L3_EXIT_Pos 0UL 404 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASK_LNK0_L3_EXIT_Msk 0x1UL 405 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASK_LNK1_L3_EXIT_Pos 1UL 406 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASK_LNK1_L3_EXIT_Msk 0x2UL 407 /* LVDSSS_LVDS_LVDS_LOW_PWR_INTR.LVDS_WAKEUP_INTR_MASKED */ 408 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASKED_LNK0_L3_EXIT_Pos 0UL 409 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASKED_LNK0_L3_EXIT_Msk 0x1UL 410 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASKED_LNK1_L3_EXIT_Pos 1UL 411 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_MASKED_LNK1_L3_EXIT_Msk 0x2UL 412 /* LVDSSS_LVDS_LVDS_LOW_PWR_INTR.LVDS_WAKEUP_INTR_SET */ 413 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_SET_LNK0_L3_EXIT_Pos 0UL 414 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_SET_LNK0_L3_EXIT_Msk 0x1UL 415 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_SET_LNK1_L3_EXIT_Pos 1UL 416 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LVDS_WAKEUP_INTR_SET_LNK1_L3_EXIT_Msk 0x2UL 417 /* LVDSSS_LVDS_LVDS_LOW_PWR_INTR.LOW_PWR_CTL */ 418 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_MASK_L1_ENTRY_Pos 0UL 419 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_MASK_L1_ENTRY_Msk 0x1UL 420 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_MASK_L3_ENTRY_Pos 1UL 421 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_MASK_L3_ENTRY_Msk 0x2UL 422 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_AUTO_MODE_Pos 4UL 423 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_AUTO_MODE_Msk 0x10UL 424 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_SEL_ON_OFF_Pos 5UL 425 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_SEL_ON_OFF_Msk 0x20UL 426 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_IO_OFF_VALUE_Pos 6UL 427 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_IO_OFF_VALUE_Msk 0x40UL 428 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_IO_ON_VALUE_Pos 7UL 429 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_IO_ON_VALUE_Msk 0x80UL 430 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_L3_GPIO_CTL_Pos 8UL 431 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_L3_GPIO_CTL_Msk 0x100UL 432 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_L3_TO_IO_OFF_DLY_Pos 16UL 433 #define LVDSSS_LVDS_LVDS_LOW_PWR_INTR_LOW_PWR_CTL_L3_TO_IO_OFF_DLY_Msk 0x7F0000UL 434 435 436 /* LVDSSS_LVDS_THREAD.GPIF_DATA_CTRL */ 437 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_ING_DATA_VALID_Pos 0UL 438 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_ING_DATA_VALID_Msk 0x1UL 439 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_EG_DATA_VALID_Pos 1UL 440 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_EG_DATA_VALID_Msk 0x2UL 441 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_IN_ADDR_VALID_Pos 2UL 442 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_IN_ADDR_VALID_Msk 0x4UL 443 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_EG_ADDR_VALID_Pos 3UL 444 #define LVDSSS_LVDS_THREAD_GPIF_DATA_CTRL_EG_ADDR_VALID_Msk 0x8UL 445 /* LVDSSS_LVDS_THREAD.GPIF_INGRESS_DATA_WORD0 */ 446 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD0_DATA_Pos 0UL 447 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD0_DATA_Msk 0xFFFFFFFFUL 448 /* LVDSSS_LVDS_THREAD.GPIF_INGRESS_DATA_WORD1 */ 449 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD1_DATA_Pos 0UL 450 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD1_DATA_Msk 0xFFFFFFFFUL 451 /* LVDSSS_LVDS_THREAD.GPIF_INGRESS_DATA_WORD2 */ 452 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD2_DATA_Pos 0UL 453 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD2_DATA_Msk 0xFFFFFFFFUL 454 /* LVDSSS_LVDS_THREAD.GPIF_INGRESS_DATA_WORD3 */ 455 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD3_DATA_Pos 0UL 456 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_DATA_WORD3_DATA_Msk 0xFFFFFFFFUL 457 /* LVDSSS_LVDS_THREAD.GPIF_EGRESS_DATA_WORD0 */ 458 #define LVDSSS_LVDS_THREAD_GPIF_EGRESS_DATA_WORD0_DATA_Pos 0UL 459 #define LVDSSS_LVDS_THREAD_GPIF_EGRESS_DATA_WORD0_DATA_Msk 0xFFFFFFFFUL 460 /* LVDSSS_LVDS_THREAD.GPIF_EGRESS_DATA_WORD1 */ 461 #define LVDSSS_LVDS_THREAD_GPIF_EGRESS_DATA_WORD1_DATA_Pos 0UL 462 #define LVDSSS_LVDS_THREAD_GPIF_EGRESS_DATA_WORD1_DATA_Msk 0xFFFFFFFFUL 463 /* LVDSSS_LVDS_THREAD.GPIF_INGRESS_ADDRESS */ 464 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_ADDRESS_ADDRESS_Pos 0UL 465 #define LVDSSS_LVDS_THREAD_GPIF_INGRESS_ADDRESS_ADDRESS_Msk 0xFFFFFFFFUL 466 /* LVDSSS_LVDS_THREAD.GPIF_EGRESS_ADDRESS */ 467 #define LVDSSS_LVDS_THREAD_GPIF_EGRESS_ADDRESS_ADDRESS_Pos 0UL 468 #define LVDSSS_LVDS_THREAD_GPIF_EGRESS_ADDRESS_ADDRESS_Msk 0xFFFFFFFFUL 469 /* LVDSSS_LVDS_THREAD.GPIF_THREAD_CONFIG */ 470 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_THREAD_NUM_Pos 0UL 471 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_THREAD_NUM_Msk 0x1UL 472 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_THREAD_SOCK_Pos 1UL 473 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_THREAD_SOCK_Msk 0xEUL 474 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_ADAPTOR_NUM_Pos 4UL 475 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_ADAPTOR_NUM_Msk 0x10UL 476 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_WM_CFG_Pos 7UL 477 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_WM_CFG_Msk 0x80UL 478 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_BURST_SIZE_Pos 8UL 479 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_BURST_SIZE_Msk 0xF00UL 480 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_WATERMARK_Pos 16UL 481 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_WATERMARK_Msk 0x3FFF0000UL 482 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_ENABLE_THREAD_CTLR_Pos 31UL 483 #define LVDSSS_LVDS_THREAD_GPIF_THREAD_CONFIG_ENABLE_THREAD_CTLR_Msk 0x80000000UL 484 /* LVDSSS_LVDS_THREAD.VARW0 */ 485 #define LVDSSS_LVDS_THREAD_VARW0_VARW0_Pos 0UL 486 #define LVDSSS_LVDS_THREAD_VARW0_VARW0_Msk 0xFFFFUL 487 /* LVDSSS_LVDS_THREAD.VARW1 */ 488 #define LVDSSS_LVDS_THREAD_VARW1_VARW1_Pos 0UL 489 #define LVDSSS_LVDS_THREAD_VARW1_VARW1_Msk 0xFFFFUL 490 /* LVDSSS_LVDS_THREAD.PTSSS */ 491 #define LVDSSS_LVDS_THREAD_PTSSS_PTSSS_WD0_Pos 0UL 492 #define LVDSSS_LVDS_THREAD_PTSSS_PTSSS_WD0_Msk 0xFFFFUL 493 #define LVDSSS_LVDS_THREAD_PTSSS_PTSSS_WD1_Pos 16UL 494 #define LVDSSS_LVDS_THREAD_PTSSS_PTSSS_WD1_Msk 0xFFFF0000UL 495 /* LVDSSS_LVDS_THREAD.SCRSS_DW0 */ 496 #define LVDSSS_LVDS_THREAD_SCRSS_DW0_SCRSS_WD0_Pos 0UL 497 #define LVDSSS_LVDS_THREAD_SCRSS_DW0_SCRSS_WD0_Msk 0xFFFFUL 498 #define LVDSSS_LVDS_THREAD_SCRSS_DW0_SCRSS_WD1_Pos 16UL 499 #define LVDSSS_LVDS_THREAD_SCRSS_DW0_SCRSS_WD1_Msk 0xFFFF0000UL 500 /* LVDSSS_LVDS_THREAD.SCRSS_DW1 */ 501 #define LVDSSS_LVDS_THREAD_SCRSS_DW1_SCRSS_WD2_Pos 0UL 502 #define LVDSSS_LVDS_THREAD_SCRSS_DW1_SCRSS_WD2_Msk 0xFFFFUL 503 /* LVDSSS_LVDS_THREAD.HDR_FLGS */ 504 #define LVDSSS_LVDS_THREAD_HDR_FLGS_FLG_Pos 0UL 505 #define LVDSSS_LVDS_THREAD_HDR_FLGS_FLG_Msk 0xFUL 506 /* LVDSSS_LVDS_THREAD.EVC_VAR0_DW0 */ 507 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW0_EVC_V0_WD0_Pos 0UL 508 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW0_EVC_V0_WD0_Msk 0xFFFFUL 509 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW0_EVC_V0_WD1_Pos 16UL 510 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW0_EVC_V0_WD1_Msk 0xFFFF0000UL 511 /* LVDSSS_LVDS_THREAD.EVC_VAR0_DW1 */ 512 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW1_EVC_V0_WD2_Pos 0UL 513 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW1_EVC_V0_WD2_Msk 0xFFFFUL 514 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW1_EVC_V0_WD3_Pos 16UL 515 #define LVDSSS_LVDS_THREAD_EVC_VAR0_DW1_EVC_V0_WD3_Msk 0xFFFF0000UL 516 /* LVDSSS_LVDS_THREAD.EVC_VAR1_DW0 */ 517 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW0_EVC_V1_WD0_Pos 0UL 518 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW0_EVC_V1_WD0_Msk 0xFFFFUL 519 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW0_EVC_V1_WD1_Pos 16UL 520 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW0_EVC_V1_WD1_Msk 0xFFFF0000UL 521 /* LVDSSS_LVDS_THREAD.EVC_VAR1_DW1 */ 522 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW1_EVC_V1_WD2_Pos 0UL 523 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW1_EVC_V1_WD2_Msk 0xFFFFUL 524 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW1_EVC_V1_WD3_Pos 16UL 525 #define LVDSSS_LVDS_THREAD_EVC_VAR1_DW1_EVC_V1_WD3_Msk 0xFFFF0000UL 526 /* LVDSSS_LVDS_THREAD.PLC_DW0 */ 527 #define LVDSSS_LVDS_THREAD_PLC_DW0_PLC_WD0_Pos 0UL 528 #define LVDSSS_LVDS_THREAD_PLC_DW0_PLC_WD0_Msk 0xFFFFUL 529 #define LVDSSS_LVDS_THREAD_PLC_DW0_PLC_WD1_Pos 16UL 530 #define LVDSSS_LVDS_THREAD_PLC_DW0_PLC_WD1_Msk 0xFFFF0000UL 531 /* LVDSSS_LVDS_THREAD.PLC_DW1 */ 532 #define LVDSSS_LVDS_THREAD_PLC_DW1_PLC_WD2_Pos 0UL 533 #define LVDSSS_LVDS_THREAD_PLC_DW1_PLC_WD2_Msk 0xFFFFUL 534 #define LVDSSS_LVDS_THREAD_PLC_DW1_PLC_WD3_Pos 16UL 535 #define LVDSSS_LVDS_THREAD_PLC_DW1_PLC_WD3_Msk 0xFFFF0000UL 536 /* LVDSSS_LVDS_THREAD.PAYLOAD_CFG */ 537 #define LVDSSS_LVDS_THREAD_PAYLOAD_CFG_CNT_MDATA_AS_PAYLOAD_Pos 0UL 538 #define LVDSSS_LVDS_THREAD_PAYLOAD_CFG_CNT_MDATA_AS_PAYLOAD_Msk 0x1UL 539 #define LVDSSS_LVDS_THREAD_PAYLOAD_CFG_CNT_CRC_AS_PAYLOAD_Pos 1UL 540 #define LVDSSS_LVDS_THREAD_PAYLOAD_CFG_CNT_CRC_AS_PAYLOAD_Msk 0x2UL 541 /* LVDSSS_LVDS_THREAD.DCRC_CONFIG */ 542 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_BIT_ENDIAN_Pos 0UL 543 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_BIT_ENDIAN_Msk 0x1UL 544 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_BYTE_ENDIAN_Pos 1UL 545 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_BYTE_ENDIAN_Msk 0x2UL 546 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_CRC_ENABLE_Pos 2UL 547 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_CRC_ENABLE_Msk 0x4UL 548 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_CRC_VAL_BIT_ENDIAN_Pos 4UL 549 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_CRC_VAL_BIT_ENDIAN_Msk 0x10UL 550 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_CRC_VAL_BYTE_ENDIAN_Pos 5UL 551 #define LVDSSS_LVDS_THREAD_DCRC_CONFIG_CRC_VAL_BYTE_ENDIAN_Msk 0x20UL 552 /* LVDSSS_LVDS_THREAD.DCRC */ 553 #define LVDSSS_LVDS_THREAD_DCRC_INITIAL_VALUE_Pos 0UL 554 #define LVDSSS_LVDS_THREAD_DCRC_INITIAL_VALUE_Msk 0xFFFFUL 555 #define LVDSSS_LVDS_THREAD_DCRC_CRC_VALUE_Pos 16UL 556 #define LVDSSS_LVDS_THREAD_DCRC_CRC_VALUE_Msk 0xFFFF0000UL 557 /* LVDSSS_LVDS_THREAD.DCRC_STS */ 558 #define LVDSSS_LVDS_THREAD_DCRC_STS_CRC_RECEIVED_Pos 0UL 559 #define LVDSSS_LVDS_THREAD_DCRC_STS_CRC_RECEIVED_Msk 0xFFFFUL 560 #define LVDSSS_LVDS_THREAD_DCRC_STS_CRC_ERR_CNT_Pos 16UL 561 #define LVDSSS_LVDS_THREAD_DCRC_STS_CRC_ERR_CNT_Msk 0xFF0000UL 562 #define LVDSSS_LVDS_THREAD_DCRC_STS_CRC_ERROR_Pos 31UL 563 #define LVDSSS_LVDS_THREAD_DCRC_STS_CRC_ERROR_Msk 0x80000000UL 564 /* LVDSSS_LVDS_THREAD.MCRC_CONFIG */ 565 #define LVDSSS_LVDS_THREAD_MCRC_CONFIG_MCRC_BIT_ENDIAN_Pos 0UL 566 #define LVDSSS_LVDS_THREAD_MCRC_CONFIG_MCRC_BIT_ENDIAN_Msk 0x1UL 567 #define LVDSSS_LVDS_THREAD_MCRC_CONFIG_MCRC_BYTE_ENDIAN_Pos 1UL 568 #define LVDSSS_LVDS_THREAD_MCRC_CONFIG_MCRC_BYTE_ENDIAN_Msk 0x2UL 569 #define LVDSSS_LVDS_THREAD_MCRC_CONFIG_MCRC_ENABLE_Pos 2UL 570 #define LVDSSS_LVDS_THREAD_MCRC_CONFIG_MCRC_ENABLE_Msk 0x4UL 571 /* LVDSSS_LVDS_THREAD.MCRC */ 572 #define LVDSSS_LVDS_THREAD_MCRC_INITIAL_VALUE_Pos 0UL 573 #define LVDSSS_LVDS_THREAD_MCRC_INITIAL_VALUE_Msk 0xFFFFUL 574 #define LVDSSS_LVDS_THREAD_MCRC_CRC_VALUE_Pos 16UL 575 #define LVDSSS_LVDS_THREAD_MCRC_CRC_VALUE_Msk 0xFFFF0000UL 576 /* LVDSSS_LVDS_THREAD.THREAD_DMA_INTF_CFG */ 577 #define LVDSSS_LVDS_THREAD_THREAD_DMA_INTF_CFG_RQ_EMPTY_DLY_Pos 0UL 578 #define LVDSSS_LVDS_THREAD_THREAD_DMA_INTF_CFG_RQ_EMPTY_DLY_Msk 0x7UL 579 /* LVDSSS_LVDS_THREAD.MD0_CTRL */ 580 #define LVDSSS_LVDS_THREAD_MD0_CTRL_MD_REF_CTL_Pos 0UL 581 #define LVDSSS_LVDS_THREAD_MD0_CTRL_MD_REF_CTL_Msk 0x7FFFFFFUL 582 #define LVDSSS_LVDS_THREAD_MD0_CTRL_MD_SIZE_Pos 27UL 583 #define LVDSSS_LVDS_THREAD_MD0_CTRL_MD_SIZE_Msk 0xF8000000UL 584 /* LVDSSS_LVDS_THREAD.MD1_CTRL */ 585 #define LVDSSS_LVDS_THREAD_MD1_CTRL_MD_REF_CTL_Pos 0UL 586 #define LVDSSS_LVDS_THREAD_MD1_CTRL_MD_REF_CTL_Msk 0x7FFFFFFUL 587 #define LVDSSS_LVDS_THREAD_MD1_CTRL_MD_SIZE_Pos 27UL 588 #define LVDSSS_LVDS_THREAD_MD1_CTRL_MD_SIZE_Msk 0xF8000000UL 589 /* LVDSSS_LVDS_THREAD.MD2_CTRL */ 590 #define LVDSSS_LVDS_THREAD_MD2_CTRL_MD_REF_CTL_Pos 0UL 591 #define LVDSSS_LVDS_THREAD_MD2_CTRL_MD_REF_CTL_Msk 0x7FFFFFFUL 592 #define LVDSSS_LVDS_THREAD_MD2_CTRL_MD_SIZE_Pos 27UL 593 #define LVDSSS_LVDS_THREAD_MD2_CTRL_MD_SIZE_Msk 0xF8000000UL 594 /* LVDSSS_LVDS_THREAD.MD3_CTRL */ 595 #define LVDSSS_LVDS_THREAD_MD3_CTRL_MD_REF_CTL_Pos 0UL 596 #define LVDSSS_LVDS_THREAD_MD3_CTRL_MD_REF_CTL_Msk 0x7FFFFFFUL 597 #define LVDSSS_LVDS_THREAD_MD3_CTRL_MD_SIZE_Pos 27UL 598 #define LVDSSS_LVDS_THREAD_MD3_CTRL_MD_SIZE_Msk 0xF8000000UL 599 600 601 /* LVDSSS_LVDS_GPIF_LEFT_WAVEFORM.WAVEFORM0 */ 602 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_NEXT_STATE_Pos 0UL 603 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_NEXT_STATE_Msk 0xFFUL 604 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FA_Pos 8UL 605 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FA_Msk 0x1F00UL 606 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FB_Pos 13UL 607 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FB_Msk 0x3E000UL 608 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FC_Pos 18UL 609 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FC_Msk 0x7C0000UL 610 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FD_Pos 23UL 611 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_FD_Msk 0xF800000UL 612 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_F0_L_Pos 28UL 613 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM0_F0_L_Msk 0xF0000000UL 614 /* LVDSSS_LVDS_GPIF_LEFT_WAVEFORM.WAVEFORM1 */ 615 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_F0_U_Pos 0UL 616 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_F0_U_Msk 0x1UL 617 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_F1_Pos 1UL 618 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_F1_Msk 0x3EUL 619 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_ALPHA_LEFT_Pos 6UL 620 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_ALPHA_LEFT_Msk 0x3FC0UL 621 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_ALPHA_RIGHT_Pos 14UL 622 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_ALPHA_RIGHT_Msk 0x3FC000UL 623 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_BETA_L_Pos 22UL 624 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM1_BETA_L_Msk 0xFFC00000UL 625 /* LVDSSS_LVDS_GPIF_LEFT_WAVEFORM.WAVEFORM2 */ 626 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_BETA_U_Pos 0UL 627 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_BETA_U_Msk 0x3FFFFFUL 628 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_REPEAT_COUNT_Pos 22UL 629 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_REPEAT_COUNT_Msk 0x3FC00000UL 630 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_BETA_DEASSERT_Pos 30UL 631 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_BETA_DEASSERT_Msk 0x40000000UL 632 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_VALID_Pos 31UL 633 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM2_VALID_Msk 0x80000000UL 634 /* LVDSSS_LVDS_GPIF_LEFT_WAVEFORM.WAVEFORM3 */ 635 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FA_5_Pos 0UL 636 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FA_5_Msk 0x1UL 637 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FB_5_Pos 1UL 638 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FB_5_Msk 0x2UL 639 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FC_5_Pos 2UL 640 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FC_5_Msk 0x4UL 641 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FD_5_Pos 3UL 642 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_FD_5_Msk 0x8UL 643 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_RESERVED_Pos 4UL 644 #define LVDSSS_LVDS_GPIF_LEFT_WAVEFORM_WAVEFORM3_RESERVED_Msk 0xFFFFFFF0UL 645 646 647 /* LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM.WAVEFORM0 */ 648 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_NEXT_STATE_Pos 0UL 649 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_NEXT_STATE_Msk 0xFFUL 650 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FA_Pos 8UL 651 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FA_Msk 0x1F00UL 652 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FB_Pos 13UL 653 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FB_Msk 0x3E000UL 654 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FC_Pos 18UL 655 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FC_Msk 0x7C0000UL 656 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FD_Pos 23UL 657 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_FD_Msk 0xF800000UL 658 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_F0_L_Pos 28UL 659 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM0_F0_L_Msk 0xF0000000UL 660 /* LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM.WAVEFORM1 */ 661 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_F0_U_Pos 0UL 662 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_F0_U_Msk 0x1UL 663 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_F1_Pos 1UL 664 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_F1_Msk 0x3EUL 665 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_ALPHA_LEFT_Pos 6UL 666 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_ALPHA_LEFT_Msk 0x3FC0UL 667 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_ALPHA_RIGHT_Pos 14UL 668 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_ALPHA_RIGHT_Msk 0x3FC000UL 669 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_BETA_L_Pos 22UL 670 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM1_BETA_L_Msk 0xFFC00000UL 671 /* LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM.WAVEFORM2 */ 672 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_BETA_U_Pos 0UL 673 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_BETA_U_Msk 0x3FFFFFUL 674 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_REPEAT_COUNT_Pos 22UL 675 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_REPEAT_COUNT_Msk 0x3FC00000UL 676 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_BETA_DEASSERT_Pos 30UL 677 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_BETA_DEASSERT_Msk 0x40000000UL 678 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_VALID_Pos 31UL 679 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM2_VALID_Msk 0x80000000UL 680 /* LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM.WAVEFORM3 */ 681 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FA_5_Pos 0UL 682 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FA_5_Msk 0x1UL 683 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FB_5_Pos 1UL 684 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FB_5_Msk 0x2UL 685 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FC_5_Pos 2UL 686 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FC_5_Msk 0x4UL 687 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FD_5_Pos 3UL 688 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_FD_5_Msk 0x8UL 689 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_RESERVED_Pos 4UL 690 #define LVDSSS_LVDS_GPIF_RIGHT_WAVEFORM_WAVEFORM3_RESERVED_Msk 0xFFFFFFF0UL 691 692 693 /* LVDSSS_LVDS_GPIF.GPIF_CONFIG */ 694 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_CTRL_COMP_ENABLE_Pos 0UL 695 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_CTRL_COMP_ENABLE_Msk 0x1UL 696 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_ADDR_COMP_ENABLE_Pos 1UL 697 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_ADDR_COMP_ENABLE_Msk 0x2UL 698 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_DATA_COMP_ENABLE_Pos 2UL 699 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_DATA_COMP_ENABLE_Msk 0x4UL 700 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_CLK_SOURCE_Pos 4UL 701 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_CLK_SOURCE_Msk 0x10UL 702 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_SPARE0_Pos 5UL 703 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_SPARE0_Msk 0x20UL 704 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_EN_CLK_IN_Pos 6UL 705 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_EN_CLK_IN_Msk 0x40UL 706 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_DOUT_POP_EN_Pos 7UL 707 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_DOUT_POP_EN_Msk 0x80UL 708 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_ENDIAN_Pos 10UL 709 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_ENDIAN_Msk 0x400UL 710 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_ADDR_COMP_TOGGLE_Pos 11UL 711 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_ADDR_COMP_TOGGLE_Msk 0x800UL 712 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_CTRL_COMP_TOGGLE_Pos 12UL 713 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_CTRL_COMP_TOGGLE_Msk 0x1000UL 714 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_DATA_COMP_TOGGLE_Pos 13UL 715 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_DATA_COMP_TOGGLE_Msk 0x2000UL 716 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_THREAD_IN_STATE_Pos 15UL 717 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_THREAD_IN_STATE_Msk 0x8000UL 718 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_THREAD_IN_CTL_BYT_Pos 16UL 719 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_THREAD_IN_CTL_BYT_Msk 0x10000UL 720 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_SOCKET_IN_CTL_BYT_Pos 17UL 721 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_SOCKET_IN_CTL_BYT_Msk 0x20000UL 722 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_EOP_4M_FSM_Pos 18UL 723 #define LVDSSS_LVDS_GPIF_GPIF_CONFIG_EOP_4M_FSM_Msk 0x40000UL 724 /* LVDSSS_LVDS_GPIF.GPIF_BUS_CONFIG */ 725 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH0_PTS_TRIG_PRESENT_Pos 0UL 726 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH0_PTS_TRIG_PRESENT_Msk 0x1UL 727 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH1_PTS_TRIG_PRESENT_Pos 1UL 728 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH1_PTS_TRIG_PRESENT_Msk 0x2UL 729 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH2_PTS_TRIG_PRESENT_Pos 2UL 730 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH2_PTS_TRIG_PRESENT_Msk 0x4UL 731 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH3_PTS_TRIG_PRESENT_Pos 3UL 732 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_TH3_PTS_TRIG_PRESENT_Msk 0x8UL 733 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_ADR_CTRL_Pos 4UL 734 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_ADR_CTRL_Msk 0x1F0UL 735 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_CE_PRESENT_Pos 9UL 736 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_CE_PRESENT_Msk 0x200UL 737 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_WE_PRESENT_Pos 10UL 738 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_WE_PRESENT_Msk 0x400UL 739 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_EM_VLD_PRESENT_Pos 11UL 740 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_EM_VLD_PRESENT_Msk 0x800UL 741 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_OE_PRESENT_Pos 12UL 742 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_OE_PRESENT_Msk 0x1000UL 743 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_EM_VLD_MASK_CS_WR_Pos 13UL 744 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_EM_VLD_MASK_CS_WR_Msk 0x2000UL 745 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO0_PRESENT_Pos 14UL 746 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO0_PRESENT_Msk 0x4000UL 747 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO1_PRESENT_Pos 15UL 748 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO1_PRESENT_Msk 0x8000UL 749 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_CNTR_PRESENT_Pos 16UL 750 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_CNTR_PRESENT_Msk 0x10000UL 751 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_SPARE2_Pos 18UL 752 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_SPARE2_Msk 0xC0000UL 753 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_SPARE3_Pos 20UL 754 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_SPARE3_Msk 0x100000UL 755 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO0_CONF_Pos 24UL 756 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO0_CONF_Msk 0xF000000UL 757 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO1_CONF_Pos 28UL 758 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG_FIO1_CONF_Msk 0xF0000000UL 759 /* LVDSSS_LVDS_GPIF.GPIF_BUS_CONFIG2 */ 760 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE_FROM_CTRL_Pos 0UL 761 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE_FROM_CTRL_Msk 0x7UL 762 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE5_Pos 8UL 763 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE5_Msk 0x3F00UL 764 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE6_Pos 16UL 765 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE6_Msk 0x3F0000UL 766 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE7_Pos 24UL 767 #define LVDSSS_LVDS_GPIF_GPIF_BUS_CONFIG2_STATE7_Msk 0x3F000000UL 768 /* LVDSSS_LVDS_GPIF.GPIF_AD_CONFIG */ 769 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DQ_OEN_CFG_Pos 0UL 770 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DQ_OEN_CFG_Msk 0x3UL 771 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_A_OEN_CFG_Pos 2UL 772 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_A_OEN_CFG_Msk 0xCUL 773 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_AIN_SELECT_Pos 4UL 774 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_AIN_SELECT_Msk 0x30UL 775 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_AOUT_SELECT_Pos 6UL 776 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_AOUT_SELECT_Msk 0xC0UL 777 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DOUT_SELECT_Pos 8UL 778 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DOUT_SELECT_Msk 0x100UL 779 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_AIN_DATA_Pos 9UL 780 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_AIN_DATA_Msk 0x200UL 781 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_ADDRESS_THREAD_Pos 16UL 782 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_ADDRESS_THREAD_Msk 0x30000UL 783 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DATA_THREAD_Pos 18UL 784 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DATA_THREAD_Msk 0xC0000UL 785 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DQ_INP_EN_CFG_Pos 20UL 786 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_DQ_INP_EN_CFG_Msk 0x300000UL 787 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_A_INP_EN_CFG_Pos 22UL 788 #define LVDSSS_LVDS_GPIF_GPIF_AD_CONFIG_A_INP_EN_CFG_Msk 0xC00000UL 789 /* LVDSSS_LVDS_GPIF.GPIF_CTL_FUNC0 */ 790 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_CE_CTL_SEL_Pos 0UL 791 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_CE_CTL_SEL_Msk 0x1FUL 792 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_WE_CTL_SEL_Pos 8UL 793 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_WE_CTL_SEL_Msk 0x1F00UL 794 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_OE_CTL_SEL_Pos 16UL 795 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_OE_CTL_SEL_Msk 0x1F0000UL 796 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_L3_ENTRY_SEL_Pos 24UL 797 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC0_L3_ENTRY_SEL_Msk 0x1F000000UL 798 /* LVDSSS_LVDS_GPIF.GPIF_CTL_FUNC1 */ 799 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_PKTEND_SEL_Pos 0UL 800 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_PKTEND_SEL_Msk 0x1FUL 801 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_EM_VLD_CTL_SEL_Pos 8UL 802 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_EM_VLD_CTL_SEL_Msk 0x1F00UL 803 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_TH0_PTS_TRIG_CTL_SEL_Pos 16UL 804 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_TH0_PTS_TRIG_CTL_SEL_Msk 0x1F0000UL 805 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_TH1_PTS_TRIG_CTL_SEL_Pos 24UL 806 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC1_TH1_PTS_TRIG_CTL_SEL_Msk 0x1F000000UL 807 /* LVDSSS_LVDS_GPIF.GPIF_CTL_FUNC2 */ 808 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_TH2_PTS_TRIG_CTL_SEL_Pos 0UL 809 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_TH2_PTS_TRIG_CTL_SEL_Msk 0x1FUL 810 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_TH3_PTS_TRIG_CTL_SEL_Pos 8UL 811 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_TH3_PTS_TRIG_CTL_SEL_Msk 0x1F00UL 812 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_CTL_2_LAMBDA10_SEL_Pos 16UL 813 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_CTL_2_LAMBDA10_SEL_Msk 0x1F0000UL 814 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_CTL_2_LAMBDA11_SEL_Pos 24UL 815 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC2_CTL_2_LAMBDA11_SEL_Msk 0x1F000000UL 816 /* LVDSSS_LVDS_GPIF.GPIF_CTL_FUNC3 */ 817 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA12_SEL_Pos 0UL 818 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA12_SEL_Msk 0x1FUL 819 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA13_SEL_Pos 8UL 820 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA13_SEL_Msk 0x1F00UL 821 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA14_SEL_Pos 16UL 822 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA14_SEL_Msk 0x1F0000UL 823 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA15_SEL_Pos 24UL 824 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC3_CTL_2_LAMBDA15_SEL_Msk 0x1F000000UL 825 /* LVDSSS_LVDS_GPIF.GPIF_CTL_FUNC4 */ 826 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA16_SEL_Pos 0UL 827 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA16_SEL_Msk 0x1FUL 828 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA17_SEL_Pos 8UL 829 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA17_SEL_Msk 0x1F00UL 830 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA18_SEL_Pos 16UL 831 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA18_SEL_Msk 0x1F0000UL 832 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA19_SEL_Pos 24UL 833 #define LVDSSS_LVDS_GPIF_GPIF_CTL_FUNC4_CTL_2_LAMBDA19_SEL_Msk 0x1F000000UL 834 /* LVDSSS_LVDS_GPIF.GPIF_STATUS */ 835 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_GPIF_DONE_Pos 0UL 836 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_GPIF_DONE_Msk 0x1UL 837 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_GPIF_FSM_INTR_Pos 1UL 838 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_GPIF_FSM_INTR_Msk 0x2UL 839 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_SWITCH_TIMEOUT_Pos 2UL 840 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_SWITCH_TIMEOUT_Msk 0x4UL 841 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_CRC_ERROR_Pos 3UL 842 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_CRC_ERROR_Msk 0x8UL 843 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_ADDR_COUNT_HIT_Pos 4UL 844 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_ADDR_COUNT_HIT_Msk 0x10UL 845 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_DATA_COUNT_HIT_Pos 5UL 846 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_DATA_COUNT_HIT_Msk 0x20UL 847 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_CTRL_COUNT_HIT_Pos 6UL 848 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_CTRL_COUNT_HIT_Msk 0x40UL 849 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_ADDR_COMP_HIT_Pos 7UL 850 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_ADDR_COMP_HIT_Msk 0x80UL 851 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_DATA_COMP_HIT_Pos 8UL 852 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_DATA_COMP_HIT_Msk 0x100UL 853 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_CTRL_COMP_HIT_Pos 9UL 854 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_CTRL_COMP_HIT_Msk 0x200UL 855 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_WAVEFORM_BUSY_Pos 10UL 856 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_WAVEFORM_BUSY_Msk 0x400UL 857 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_EG_DATA_EMPTY_Pos 16UL 858 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_EG_DATA_EMPTY_Msk 0xF0000UL 859 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_IN_DATA_VALID_Pos 20UL 860 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_IN_DATA_VALID_Msk 0xF00000UL 861 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_INTERRUPT_STATE_Pos 24UL 862 #define LVDSSS_LVDS_GPIF_GPIF_STATUS_INTERRUPT_STATE_Msk 0xFF000000UL 863 /* LVDSSS_LVDS_GPIF.GPIF_INTR */ 864 #define LVDSSS_LVDS_GPIF_GPIF_INTR_GPIF_DONE_Pos 0UL 865 #define LVDSSS_LVDS_GPIF_GPIF_INTR_GPIF_DONE_Msk 0x1UL 866 #define LVDSSS_LVDS_GPIF_GPIF_INTR_GPIF_FSM_INTR_Pos 1UL 867 #define LVDSSS_LVDS_GPIF_GPIF_INTR_GPIF_FSM_INTR_Msk 0x2UL 868 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SWITCH_TIMEOUT_Pos 2UL 869 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SWITCH_TIMEOUT_Msk 0x4UL 870 #define LVDSSS_LVDS_GPIF_GPIF_INTR_CRC_ERROR_Pos 3UL 871 #define LVDSSS_LVDS_GPIF_GPIF_INTR_CRC_ERROR_Msk 0x8UL 872 #define LVDSSS_LVDS_GPIF_GPIF_INTR_ADDR_COUNT_HIT_Pos 4UL 873 #define LVDSSS_LVDS_GPIF_GPIF_INTR_ADDR_COUNT_HIT_Msk 0x10UL 874 #define LVDSSS_LVDS_GPIF_GPIF_INTR_DATA_COUNT_HIT_Pos 5UL 875 #define LVDSSS_LVDS_GPIF_GPIF_INTR_DATA_COUNT_HIT_Msk 0x20UL 876 #define LVDSSS_LVDS_GPIF_GPIF_INTR_CTRL_COUNT_HIT_Pos 6UL 877 #define LVDSSS_LVDS_GPIF_GPIF_INTR_CTRL_COUNT_HIT_Msk 0x40UL 878 #define LVDSSS_LVDS_GPIF_GPIF_INTR_ADDR_COMP_HIT_Pos 7UL 879 #define LVDSSS_LVDS_GPIF_GPIF_INTR_ADDR_COMP_HIT_Msk 0x80UL 880 #define LVDSSS_LVDS_GPIF_GPIF_INTR_DATA_COMP_HIT_Pos 8UL 881 #define LVDSSS_LVDS_GPIF_GPIF_INTR_DATA_COMP_HIT_Msk 0x100UL 882 #define LVDSSS_LVDS_GPIF_GPIF_INTR_CTRL_COMP_HIT_Pos 9UL 883 #define LVDSSS_LVDS_GPIF_GPIF_INTR_CTRL_COMP_HIT_Msk 0x200UL 884 #define LVDSSS_LVDS_GPIF_GPIF_INTR_WAVEFORM_BUSY_Pos 10UL 885 #define LVDSSS_LVDS_GPIF_GPIF_INTR_WAVEFORM_BUSY_Msk 0x400UL 886 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT0_Pos 16UL 887 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT0_Msk 0x10000UL 888 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT1_Pos 17UL 889 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT1_Msk 0x20000UL 890 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT2_Pos 18UL 891 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT2_Msk 0x40000UL 892 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT3_Pos 19UL 893 #define LVDSSS_LVDS_GPIF_GPIF_INTR_EG_DATA_EMPTY_BIT3_Msk 0x80000UL 894 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT0_Pos 20UL 895 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT0_Msk 0x100000UL 896 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT1_Pos 21UL 897 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT1_Msk 0x200000UL 898 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT2_Pos 22UL 899 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT2_Msk 0x400000UL 900 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT3_Pos 23UL 901 #define LVDSSS_LVDS_GPIF_GPIF_INTR_IN_DATA_VALID_BIT3_Msk 0x800000UL 902 #define LVDSSS_LVDS_GPIF_GPIF_INTR_GPIF_ERR_Pos 24UL 903 #define LVDSSS_LVDS_GPIF_GPIF_INTR_GPIF_ERR_Msk 0x1000000UL 904 #define LVDSSS_LVDS_GPIF_GPIF_INTR_INVLD_CMD_DET_Pos 25UL 905 #define LVDSSS_LVDS_GPIF_GPIF_INTR_INVLD_CMD_DET_Msk 0x2000000UL 906 #define LVDSSS_LVDS_GPIF_GPIF_INTR_LINK_IDLE_Pos 26UL 907 #define LVDSSS_LVDS_GPIF_GPIF_INTR_LINK_IDLE_Msk 0x4000000UL 908 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SPARE4_Pos 27UL 909 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SPARE4_Msk 0x8000000UL 910 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SPARE5_Pos 28UL 911 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SPARE5_Msk 0x10000000UL 912 /* LVDSSS_LVDS_GPIF.GPIF_INTR_MASK */ 913 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_GPIF_DONE_Pos 0UL 914 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_GPIF_DONE_Msk 0x1UL 915 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_GPIF_FSM_INTR_Pos 1UL 916 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_GPIF_FSM_INTR_Msk 0x2UL 917 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_SWITCH_TIMEOUT_Pos 2UL 918 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_SWITCH_TIMEOUT_Msk 0x4UL 919 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_CRC_ERROR_Pos 3UL 920 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_CRC_ERROR_Msk 0x8UL 921 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_ADDR_COUNT_HIT_Pos 4UL 922 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_ADDR_COUNT_HIT_Msk 0x10UL 923 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_DATA_COUNT_HIT_Pos 5UL 924 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_DATA_COUNT_HIT_Msk 0x20UL 925 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_CTRL_COUNT_HIT_Pos 6UL 926 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_CTRL_COUNT_HIT_Msk 0x40UL 927 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_ADDR_COMP_HIT_Pos 7UL 928 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_ADDR_COMP_HIT_Msk 0x80UL 929 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_DATA_COMP_HIT_Pos 8UL 930 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_DATA_COMP_HIT_Msk 0x100UL 931 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_CTRL_COMP_HIT_Pos 9UL 932 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_CTRL_COMP_HIT_Msk 0x200UL 933 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_WAVEFORM_BUSY_Pos 10UL 934 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_WAVEFORM_BUSY_Msk 0x400UL 935 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_EG_DATA_EMPTY_Pos 16UL 936 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_EG_DATA_EMPTY_Msk 0xF0000UL 937 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_IN_DATA_VALID_Pos 20UL 938 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_IN_DATA_VALID_Msk 0xF00000UL 939 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_GPIF_ERR_Pos 24UL 940 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_GPIF_ERR_Msk 0x1000000UL 941 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_INVLD_CMD_DET_Pos 25UL 942 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_INVLD_CMD_DET_Msk 0x2000000UL 943 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_LINK_IDLE_Pos 26UL 944 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_LINK_IDLE_Msk 0x4000000UL 945 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_SPARE4_Pos 27UL 946 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_SPARE4_Msk 0x8000000UL 947 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_SPARE5_Pos 28UL 948 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASK_SPARE5_Msk 0x10000000UL 949 /* LVDSSS_LVDS_GPIF.GPIF_INTR_MASKED */ 950 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_GPIF_DONE_Pos 0UL 951 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_GPIF_DONE_Msk 0x1UL 952 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_GPIF_FSM_INTR_Pos 1UL 953 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_GPIF_FSM_INTR_Msk 0x2UL 954 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_SWITCH_TIMEOUT_Pos 2UL 955 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_SWITCH_TIMEOUT_Msk 0x4UL 956 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_CRC_ERROR_Pos 3UL 957 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_CRC_ERROR_Msk 0x8UL 958 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_ADDR_COUNT_HIT_Pos 4UL 959 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_ADDR_COUNT_HIT_Msk 0x10UL 960 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_DATA_COUNT_HIT_Pos 5UL 961 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_DATA_COUNT_HIT_Msk 0x20UL 962 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_CTRL_COUNT_HIT_Pos 6UL 963 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_CTRL_COUNT_HIT_Msk 0x40UL 964 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_ADDR_COMP_HIT_Pos 7UL 965 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_ADDR_COMP_HIT_Msk 0x80UL 966 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_DATA_COMP_HIT_Pos 8UL 967 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_DATA_COMP_HIT_Msk 0x100UL 968 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_CTRL_COMP_HIT_Pos 9UL 969 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_CTRL_COMP_HIT_Msk 0x200UL 970 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_WAVEFORM_BUSY_Pos 10UL 971 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_WAVEFORM_BUSY_Msk 0x400UL 972 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_EG_DATA_EMPTY_Pos 16UL 973 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_EG_DATA_EMPTY_Msk 0xF0000UL 974 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_IN_DATA_VALID_Pos 20UL 975 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_IN_DATA_VALID_Msk 0xF00000UL 976 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_GPIF_ERR_Pos 24UL 977 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_GPIF_ERR_Msk 0x1000000UL 978 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_INVLD_CMD_DET_Pos 25UL 979 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_INVLD_CMD_DET_Msk 0x2000000UL 980 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_LINK_IDLE_Pos 26UL 981 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_LINK_IDLE_Msk 0x4000000UL 982 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_SPARE4_Pos 27UL 983 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_SPARE4_Msk 0x8000000UL 984 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_SPARE5_Pos 28UL 985 #define LVDSSS_LVDS_GPIF_GPIF_INTR_MASKED_SPARE5_Msk 0x10000000UL 986 /* LVDSSS_LVDS_GPIF.GPIF_INTR_SET */ 987 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_GPIF_DONE_Pos 0UL 988 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_GPIF_DONE_Msk 0x1UL 989 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_GPIF_FSM_INTR_Pos 1UL 990 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_GPIF_FSM_INTR_Msk 0x2UL 991 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_SWITCH_TIMEOUT_Pos 2UL 992 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_SWITCH_TIMEOUT_Msk 0x4UL 993 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_CRC_ERROR_Pos 3UL 994 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_CRC_ERROR_Msk 0x8UL 995 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_ADDR_COUNT_HIT_Pos 4UL 996 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_ADDR_COUNT_HIT_Msk 0x10UL 997 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_DATA_COUNT_HIT_Pos 5UL 998 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_DATA_COUNT_HIT_Msk 0x20UL 999 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_CTRL_COUNT_HIT_Pos 6UL 1000 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_CTRL_COUNT_HIT_Msk 0x40UL 1001 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_ADDR_COMP_HIT_Pos 7UL 1002 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_ADDR_COMP_HIT_Msk 0x80UL 1003 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_DATA_COMP_HIT_Pos 8UL 1004 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_DATA_COMP_HIT_Msk 0x100UL 1005 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_CTRL_COMP_HIT_Pos 9UL 1006 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_CTRL_COMP_HIT_Msk 0x200UL 1007 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_WAVEFORM_BUSY_Pos 10UL 1008 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_WAVEFORM_BUSY_Msk 0x400UL 1009 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_EG_DATA_EMPTY_Pos 16UL 1010 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_EG_DATA_EMPTY_Msk 0xF0000UL 1011 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_IN_DATA_VALID_Pos 20UL 1012 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_IN_DATA_VALID_Msk 0xF00000UL 1013 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_GPIF_ERR_Pos 24UL 1014 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_GPIF_ERR_Msk 0x1000000UL 1015 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_INVLD_CMD_DET_Pos 25UL 1016 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_INVLD_CMD_DET_Msk 0x2000000UL 1017 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_LINK_IDLE_Pos 26UL 1018 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_LINK_IDLE_Msk 0x4000000UL 1019 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_SPARE4_Pos 27UL 1020 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_SPARE4_Msk 0x8000000UL 1021 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_SPARE5_Pos 28UL 1022 #define LVDSSS_LVDS_GPIF_GPIF_INTR_SET_SPARE5_Msk 0x10000000UL 1023 /* LVDSSS_LVDS_GPIF.GPIF_ERROR */ 1024 #define LVDSSS_LVDS_GPIF_GPIF_ERROR_GPIF_ERR_CODE_Pos 0UL 1025 #define LVDSSS_LVDS_GPIF_GPIF_ERROR_GPIF_ERR_CODE_Msk 0x1FUL 1026 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_BUS_DIRECTION */ 1027 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_INP_EN_Pos 0UL 1028 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_INP_EN_Msk 0x1UL 1029 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_OEN_Pos 1UL 1030 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_OEN_Msk 0x2UL 1031 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_BIDI_EN_Pos 2UL 1032 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_BIDI_EN_Msk 0x4UL 1033 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_OPEN_DRAIN_EN_Pos 3UL 1034 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DIRECTION_OPEN_DRAIN_EN_Msk 0x8UL 1035 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_BUS_DEFAULT */ 1036 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DEFAULT_DEFAULT_Pos 0UL 1037 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_DEFAULT_DEFAULT_Msk 0xFFFFFUL 1038 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_BUS_POLARITY */ 1039 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_POLARITY_POLARITY_Pos 0UL 1040 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_POLARITY_POLARITY_Msk 0xFFFFFUL 1041 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_BUS_TOGGLE */ 1042 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_TOGGLE_TOGGLE_Pos 0UL 1043 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_TOGGLE_TOGGLE_Msk 0xFFFFFUL 1044 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_BUS_SELECT */ 1045 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_SELECT_OMEGA_INDEX_Pos 0UL 1046 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_BUS_SELECT_OMEGA_INDEX_Msk 0x1FUL 1047 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_COUNT_CONFIG */ 1048 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_ENABLE_Pos 0UL 1049 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_ENABLE_Msk 0x1UL 1050 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_DOWN_UP_CNTR_Pos 1UL 1051 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_DOWN_UP_CNTR_Msk 0x2UL 1052 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_RELOAD_CNTR_Pos 2UL 1053 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_RELOAD_CNTR_Msk 0x4UL 1054 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_SW_RESET_CNTR_Pos 3UL 1055 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_SW_RESET_CNTR_Msk 0x8UL 1056 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_CONNECT_Pos 4UL 1057 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_CONFIG_CONNECT_Msk 0xF0UL 1058 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_COUNT_RESET */ 1059 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_RESET_RESET_LOAD_VAL_Pos 0UL 1060 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_RESET_RESET_LOAD_VAL_Msk 0xFFFFUL 1061 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_COUNT_LIMIT */ 1062 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_LIMIT_LIMIT_VAL_Pos 0UL 1063 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COUNT_LIMIT_LIMIT_VAL_Msk 0xFFFFUL 1064 /* LVDSSS_LVDS_GPIF.GPIF_ADDR_COUNT_CONFIG */ 1065 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_ENABLE_Pos 0UL 1066 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_ENABLE_Msk 0x1UL 1067 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_RELOAD_Pos 1UL 1068 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_RELOAD_Msk 0x2UL 1069 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_SW_RESET_Pos 2UL 1070 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_SW_RESET_Msk 0x4UL 1071 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_DOWN_UP_Pos 3UL 1072 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_DOWN_UP_Msk 0x8UL 1073 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_INCREMENT_Pos 8UL 1074 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_CONFIG_INCREMENT_Msk 0xFF00UL 1075 /* LVDSSS_LVDS_GPIF.GPIF_ADDR_COUNT_RESET */ 1076 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_RESET_RESET_LOAD_Pos 0UL 1077 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_RESET_RESET_LOAD_Msk 0xFFFFFFFFUL 1078 /* LVDSSS_LVDS_GPIF.GPIF_ADDR_COUNT_LIMIT */ 1079 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_LIMIT_LIMIT_Pos 0UL 1080 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COUNT_LIMIT_LIMIT_Msk 0xFFFFFFFFUL 1081 /* LVDSSS_LVDS_GPIF.GPIF_STATE_COUNT_CONFIG */ 1082 #define LVDSSS_LVDS_GPIF_GPIF_STATE_COUNT_CONFIG_ENABLE_Pos 0UL 1083 #define LVDSSS_LVDS_GPIF_GPIF_STATE_COUNT_CONFIG_ENABLE_Msk 0x1UL 1084 #define LVDSSS_LVDS_GPIF_GPIF_STATE_COUNT_CONFIG_SW_RESET_STATE_CNT_Pos 1UL 1085 #define LVDSSS_LVDS_GPIF_GPIF_STATE_COUNT_CONFIG_SW_RESET_STATE_CNT_Msk 0x2UL 1086 /* LVDSSS_LVDS_GPIF.GPIF_STATE_COUNT_LIMIT */ 1087 #define LVDSSS_LVDS_GPIF_GPIF_STATE_COUNT_LIMIT_LIMIT_VAL_Pos 0UL 1088 #define LVDSSS_LVDS_GPIF_GPIF_STATE_COUNT_LIMIT_LIMIT_VAL_Msk 0xFFFFUL 1089 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COUNT_CONFIG */ 1090 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_ENABLE_Pos 0UL 1091 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_ENABLE_Msk 0x1UL 1092 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_RELOAD_Pos 1UL 1093 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_RELOAD_Msk 0x2UL 1094 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_SW_RESET_Pos 2UL 1095 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_SW_RESET_Msk 0x4UL 1096 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_DOWN_UP_Pos 3UL 1097 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_DOWN_UP_Msk 0x8UL 1098 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_INCREMENT_Pos 8UL 1099 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_CONFIG_INCREMENT_Msk 0xFF00UL 1100 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COUNT_RESET_LSB */ 1101 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_RESET_LSB_RESET_LOAD_Pos 0UL 1102 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_RESET_LSB_RESET_LOAD_Msk 0xFFFFFFFFUL 1103 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COUNT_RESET_MSB */ 1104 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_RESET_MSB_RESET_LOAD_Pos 0UL 1105 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_RESET_MSB_RESET_LOAD_Msk 0xFFFFFFFFUL 1106 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COUNT_LIMIT_LSB */ 1107 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_LIMIT_LSB_LIMIT_Pos 0UL 1108 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_LIMIT_LSB_LIMIT_Msk 0xFFFFFFFFUL 1109 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COUNT_LIMIT_MSB */ 1110 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_LIMIT_MSB_LIMIT_Pos 0UL 1111 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COUNT_LIMIT_MSB_LIMIT_Msk 0xFFFFFFFFUL 1112 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_COMP_VALUE */ 1113 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COMP_VALUE_COMP_VALUE_Pos 0UL 1114 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COMP_VALUE_COMP_VALUE_Msk 0xFFFFFUL 1115 /* LVDSSS_LVDS_GPIF.GPIF_CTRL_COMP_MASK */ 1116 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COMP_MASK_CTRL_COMP_MASK_Pos 0UL 1117 #define LVDSSS_LVDS_GPIF_GPIF_CTRL_COMP_MASK_CTRL_COMP_MASK_Msk 0xFFFFFUL 1118 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_VALUE_WORD0 */ 1119 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD0_VALUE_Pos 0UL 1120 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD0_VALUE_Msk 0xFFFFFFFFUL 1121 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_VALUE_WORD1 */ 1122 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD1_VALUE_Pos 0UL 1123 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD1_VALUE_Msk 0xFFFFFFFFUL 1124 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_VALUE_WORD2 */ 1125 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD2_VALUE_Pos 0UL 1126 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD2_VALUE_Msk 0xFFFFFFFFUL 1127 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_VALUE_WORD3 */ 1128 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD3_VALUE_Pos 0UL 1129 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_VALUE_WORD3_VALUE_Msk 0xFFFFFFFFUL 1130 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_MASK_WORD0 */ 1131 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD0_MASK_Pos 0UL 1132 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD0_MASK_Msk 0xFFFFFFFFUL 1133 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_MASK_WORD1 */ 1134 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD1_MASK_Pos 0UL 1135 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD1_MASK_Msk 0xFFFFFFFFUL 1136 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_MASK_WORD2 */ 1137 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD2_MASK_Pos 0UL 1138 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD2_MASK_Msk 0xFFFFFFFFUL 1139 /* LVDSSS_LVDS_GPIF.GPIF_DATA_COMP_MASK_WORD3 */ 1140 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD3_MASK_Pos 0UL 1141 #define LVDSSS_LVDS_GPIF_GPIF_DATA_COMP_MASK_WORD3_MASK_Msk 0xFFFFFFFFUL 1142 /* LVDSSS_LVDS_GPIF.GPIF_ADDR_COMP_VALUE */ 1143 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COMP_VALUE_VALUE_Pos 0UL 1144 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COMP_VALUE_VALUE_Msk 0xFFFFFFFFUL 1145 /* LVDSSS_LVDS_GPIF.GPIF_ADDR_COMP_MASK */ 1146 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COMP_MASK_MASK_Pos 0UL 1147 #define LVDSSS_LVDS_GPIF_GPIF_ADDR_COMP_MASK_MASK_Msk 0xFFFFFFFFUL 1148 /* LVDSSS_LVDS_GPIF.GPIF_LAMBDA_STAT0 */ 1149 #define LVDSSS_LVDS_GPIF_GPIF_LAMBDA_STAT0_LAMBDA_Pos 0UL 1150 #define LVDSSS_LVDS_GPIF_GPIF_LAMBDA_STAT0_LAMBDA_Msk 0xFFFFFFFFUL 1151 /* LVDSSS_LVDS_GPIF.GPIF_LAMBDA_STAT1 */ 1152 #define LVDSSS_LVDS_GPIF_GPIF_LAMBDA_STAT1_LAMBDA_Pos 0UL 1153 #define LVDSSS_LVDS_GPIF_GPIF_LAMBDA_STAT1_LAMBDA_Msk 0xFFFFFFFFUL 1154 /* LVDSSS_LVDS_GPIF.GPIF_ALPHA_STAT */ 1155 #define LVDSSS_LVDS_GPIF_GPIF_ALPHA_STAT_ALPHA_Pos 0UL 1156 #define LVDSSS_LVDS_GPIF_GPIF_ALPHA_STAT_ALPHA_Msk 0xFFUL 1157 /* LVDSSS_LVDS_GPIF.GPIF_BETA_STAT */ 1158 #define LVDSSS_LVDS_GPIF_GPIF_BETA_STAT_BETA_VAL_Pos 0UL 1159 #define LVDSSS_LVDS_GPIF_GPIF_BETA_STAT_BETA_VAL_Msk 0xFFFFFFFFUL 1160 /* LVDSSS_LVDS_GPIF.GPIF_WAVEFORM_CTRL_STAT */ 1161 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_WAVEFORM_VALID_Pos 0UL 1162 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_WAVEFORM_VALID_Msk 0x1UL 1163 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_PAUSE_Pos 1UL 1164 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_PAUSE_Msk 0x2UL 1165 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_Pos 8UL 1166 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_GPIF_STAT_Msk 0x700UL 1167 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_CPU_LAMBDA_Pos 11UL 1168 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_CPU_LAMBDA_Msk 0x800UL 1169 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_ALPHA_INIT_Pos 16UL 1170 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_ALPHA_INIT_Msk 0xFF0000UL 1171 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_Pos 24UL 1172 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_CTRL_STAT_CURRENT_STATE_Msk 0xFF000000UL 1173 /* LVDSSS_LVDS_GPIF.GPIF_WAVEFORM_SWITCH */ 1174 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_WAVEFORM_SWITCH_Pos 0UL 1175 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_WAVEFORM_SWITCH_Msk 0x1UL 1176 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_DONE_ENABLE_Pos 1UL 1177 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_DONE_ENABLE_Msk 0x2UL 1178 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_SWITCH_NOW_Pos 2UL 1179 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_SWITCH_NOW_Msk 0x4UL 1180 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TIMEOUT_MODE_Pos 3UL 1181 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TIMEOUT_MODE_Msk 0x38UL 1182 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TIMEOUT_REACHED_Pos 6UL 1183 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TIMEOUT_REACHED_Msk 0x40UL 1184 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TERMINATED_Pos 7UL 1185 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TERMINATED_Msk 0x80UL 1186 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TERMINAL_STATE_Pos 8UL 1187 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TERMINAL_STATE_Msk 0xFF00UL 1188 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_Pos 16UL 1189 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_DESTINATION_STATE_Msk 0xFF0000UL 1190 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_DONE_STATE_Pos 24UL 1191 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_DONE_STATE_Msk 0xFF000000UL 1192 /* LVDSSS_LVDS_GPIF.GPIF_WAVEFORM_SWITCH_TIMEOUT */ 1193 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TIMEOUT_RESET_LOAD_Pos 0UL 1194 #define LVDSSS_LVDS_GPIF_GPIF_WAVEFORM_SWITCH_TIMEOUT_RESET_LOAD_Msk 0xFFFFFFFFUL 1195 /* LVDSSS_LVDS_GPIF.GPIF_CRC_CALC_CONFIG */ 1196 #define LVDSSS_LVDS_GPIF_GPIF_CRC_CALC_CONFIG_INIT_CRC_CTL_4MFSM_Pos 0UL 1197 #define LVDSSS_LVDS_GPIF_GPIF_CRC_CALC_CONFIG_INIT_CRC_CTL_4MFSM_Msk 0x1UL 1198 #define LVDSSS_LVDS_GPIF_GPIF_CRC_CALC_CONFIG_USE_CRC_CTL_4MFSM_Pos 1UL 1199 #define LVDSSS_LVDS_GPIF_GPIF_CRC_CALC_CONFIG_USE_CRC_CTL_4MFSM_Msk 0x2UL 1200 #define LVDSSS_LVDS_GPIF_GPIF_CRC_CALC_CONFIG_USE_CALC_CRC_4MFSM_Pos 2UL 1201 #define LVDSSS_LVDS_GPIF_GPIF_CRC_CALC_CONFIG_USE_CALC_CRC_4MFSM_Msk 0x4UL 1202 /* LVDSSS_LVDS_GPIF.GPIF_BETA_DEASSERT */ 1203 #define LVDSSS_LVDS_GPIF_GPIF_BETA_DEASSERT_APPLY_DEASSERT_Pos 0UL 1204 #define LVDSSS_LVDS_GPIF_GPIF_BETA_DEASSERT_APPLY_DEASSERT_Msk 0xFFFFFFFFUL 1205 /* LVDSSS_LVDS_GPIF.GPIF_FUNCTION */ 1206 #define LVDSSS_LVDS_GPIF_GPIF_FUNCTION_FUNCTION_Pos 0UL 1207 #define LVDSSS_LVDS_GPIF_GPIF_FUNCTION_FUNCTION_Msk 0xFFFFUL 1208 /* LVDSSS_LVDS_GPIF.LINK_IDLE_CFG */ 1209 #define LVDSSS_LVDS_GPIF_LINK_IDLE_CFG_IDLE_CMD_CNT_Pos 0UL 1210 #define LVDSSS_LVDS_GPIF_LINK_IDLE_CFG_IDLE_CMD_CNT_Msk 0xFFFFUL 1211 /* LVDSSS_LVDS_GPIF.LVCMOS_CLK_OUT_CFG */ 1212 #define LVDSSS_LVDS_GPIF_LVCMOS_CLK_OUT_CFG_CLK_SRC_Pos 0UL 1213 #define LVDSSS_LVDS_GPIF_LVCMOS_CLK_OUT_CFG_CLK_SRC_Msk 0x3UL 1214 #define LVDSSS_LVDS_GPIF_LVCMOS_CLK_OUT_CFG_CLK_SRC_DIV_VAL_Pos 4UL 1215 #define LVDSSS_LVDS_GPIF_LVCMOS_CLK_OUT_CFG_CLK_SRC_DIV_VAL_Msk 0x3F0UL 1216 1217 1218 /* LVDSSS_LVDS_AFE.DLL_DFTLPF */ 1219 #define LVDSSS_LVDS_AFE_DLL_DFTLPF_EN_Pos 0UL 1220 #define LVDSSS_LVDS_AFE_DLL_DFTLPF_EN_Msk 0x1UL 1221 #define LVDSSS_LVDS_AFE_DLL_DFTLPF_FILT_SEL_Pos 1UL 1222 #define LVDSSS_LVDS_AFE_DLL_DFTLPF_FILT_SEL_Msk 0x2UL 1223 /* LVDSSS_LVDS_AFE.DLL_CONFIG */ 1224 #define LVDSSS_LVDS_AFE_DLL_CONFIG_DFT_RINGO_RST_Pos 0UL 1225 #define LVDSSS_LVDS_AFE_DLL_CONFIG_DFT_RINGO_RST_Msk 0x1UL 1226 /* LVDSSS_LVDS_AFE.DLL_STATUS */ 1227 #define LVDSSS_LVDS_AFE_DLL_STATUS_FT_Pos 0UL 1228 #define LVDSSS_LVDS_AFE_DLL_STATUS_FT_Msk 0x3FUL 1229 /* LVDSSS_LVDS_AFE.DLL_M_CONFIG */ 1230 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_EN_Pos 0UL 1231 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_EN_Msk 0x1UL 1232 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_CLK_SEL_Pos 1UL 1233 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_CLK_SEL_Msk 0x2UL 1234 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_INV_CLK_MUX_Pos 2UL 1235 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_INV_CLK_MUX_Msk 0x4UL 1236 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_EN_Pos 3UL 1237 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_EN_Msk 0x8UL 1238 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_TEST_CLK_EN_Pos 4UL 1239 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_TEST_CLK_EN_Msk 0x10UL 1240 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_BBPD_EN_Pos 5UL 1241 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_BBPD_EN_Msk 0x20UL 1242 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_BBPD_SEL_Pos 6UL 1243 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_DFT_BBPD_SEL_Msk 0xC0UL 1244 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_SPEED_MODE_Pos 8UL 1245 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_SPEED_MODE_Msk 0x100UL 1246 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_ADFT_EN_LV_Pos 9UL 1247 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_ADFT_EN_LV_Msk 0x200UL 1248 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_FLT_EN_Pos 10UL 1249 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_FLT_EN_Msk 0x400UL 1250 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_MDLL_SEL_PH_Pos 11UL 1251 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_MDLL_SEL_PH_Msk 0x7800UL 1252 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_MDLL_OW_PH_Pos 15UL 1253 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_MDLL_OW_PH_Msk 0x8000UL 1254 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_HSPEED_MFREQ_SEL_Pos 16UL 1255 #define LVDSSS_LVDS_AFE_DLL_M_CONFIG_HSPEED_MFREQ_SEL_Msk 0x10000UL 1256 /* LVDSSS_LVDS_AFE.DLL_M_STATUS */ 1257 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_SEL_PH_Pos 0UL 1258 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_SEL_PH_Msk 0xFUL 1259 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_CT_Pos 4UL 1260 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_CT_Msk 0xF0UL 1261 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_BBPD_Pos 8UL 1262 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_BBPD_Msk 0x100UL 1263 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_DFT_BBPD_Pos 9UL 1264 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_DFT_BBPD_Msk 0x200UL 1265 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_CORRECT_PERIOD_Pos 10UL 1266 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_CORRECT_PERIOD_Msk 0x400UL 1267 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_DLL_LOCK_Pos 11UL 1268 #define LVDSSS_LVDS_AFE_DLL_M_STATUS_DLL_LOCK_Msk 0x800UL 1269 /* LVDSSS_LVDS_AFE.DLL_S_CONFIG */ 1270 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_INV_CLK_MUXED_Pos 0UL 1271 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_INV_CLK_MUXED_Msk 0x1UL 1272 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_DFT_EN_Pos 1UL 1273 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_DFT_EN_Msk 0x2UL 1274 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_EN_Pos 2UL 1275 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_EN_Msk 0x4UL 1276 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_DFT_LPF_EN_Pos 3UL 1277 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_DFT_LPF_EN_Msk 0x8UL 1278 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_SEL_PH_Pos 4UL 1279 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_SEL_PH_Msk 0xF0UL 1280 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_OW_PH_Pos 8UL 1281 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_OW_PH_Msk 0x100UL 1282 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_SPEED_MODE_Pos 9UL 1283 #define LVDSSS_LVDS_AFE_DLL_S_CONFIG_SDLL_SPEED_MODE_Msk 0x200UL 1284 /* LVDSSS_LVDS_AFE.DLL_S_STATUS */ 1285 #define LVDSSS_LVDS_AFE_DLL_S_STATUS_SEL_PH_Pos 0UL 1286 #define LVDSSS_LVDS_AFE_DLL_S_STATUS_SEL_PH_Msk 0xFUL 1287 #define LVDSSS_LVDS_AFE_DLL_S_STATUS_CLK_DFT_Pos 4UL 1288 #define LVDSSS_LVDS_AFE_DLL_S_STATUS_CLK_DFT_Msk 0x10UL 1289 /* LVDSSS_LVDS_AFE.GENERAL_LICIO_CIO */ 1290 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_CIO_LVDS_RTERM_EN_Pos 0UL 1291 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_CIO_LVDS_RTERM_EN_Msk 0x3FFUL 1292 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_CIO_LVCMOS_LB_EN_Pos 10UL 1293 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_CIO_LVCMOS_LB_EN_Msk 0x400UL 1294 /* LVDSSS_LVDS_AFE.LICIO_CIO */ 1295 #define LVDSSS_LVDS_AFE_LICIO_CIO_LVCMOS_RX_EN_Pos 0UL 1296 #define LVDSSS_LVDS_AFE_LICIO_CIO_LVCMOS_RX_EN_Msk 0x1UL 1297 #define LVDSSS_LVDS_AFE_LICIO_CIO_LVCMOS_TX_EN_Pos 1UL 1298 #define LVDSSS_LVDS_AFE_LICIO_CIO_LVCMOS_TX_EN_Msk 0x2UL 1299 /* LVDSSS_LVDS_AFE.GENERAL_LICIO_LI */ 1300 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_LI_LVDS_LB_EN_Pos 0UL 1301 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_LI_LVDS_LB_EN_Msk 0x1UL 1302 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_LI_LVDS_CONFIG_Pos 1UL 1303 #define LVDSSS_LVDS_AFE_GENERAL_LICIO_LI_LVDS_CONFIG_Msk 0x6UL 1304 /* LVDSSS_LVDS_AFE.LICIO_LI */ 1305 #define LVDSSS_LVDS_AFE_LICIO_LI_LVDS_RX_EN_Pos 0UL 1306 #define LVDSSS_LVDS_AFE_LICIO_LI_LVDS_RX_EN_Msk 0x1UL 1307 #define LVDSSS_LVDS_AFE_LICIO_LI_ATST_Pos 7UL 1308 #define LVDSSS_LVDS_AFE_LICIO_LI_ATST_Msk 0x380UL 1309 /* LVDSSS_LVDS_AFE.LICIO_VSSIO_IREF */ 1310 #define LVDSSS_LVDS_AFE_LICIO_VSSIO_IREF_EN_Pos 0UL 1311 #define LVDSSS_LVDS_AFE_LICIO_VSSIO_IREF_EN_Msk 0x1UL 1312 #define LVDSSS_LVDS_AFE_LICIO_VSSIO_IREF_IN_SEL_Pos 1UL 1313 #define LVDSSS_LVDS_AFE_LICIO_VSSIO_IREF_IN_SEL_Msk 0x6UL 1314 #define LVDSSS_LVDS_AFE_LICIO_VSSIO_IREF_ATST_EN_Pos 3UL 1315 #define LVDSSS_LVDS_AFE_LICIO_VSSIO_IREF_ATST_EN_Msk 0x8UL 1316 /* LVDSSS_LVDS_AFE.LICIO_LI_OUT_STATUS */ 1317 #define LVDSSS_LVDS_AFE_LICIO_LI_OUT_STATUS_LVDS_DATA_Pos 0UL 1318 #define LVDSSS_LVDS_AFE_LICIO_LI_OUT_STATUS_LVDS_DATA_Msk 0xFFUL 1319 #define LVDSSS_LVDS_AFE_LICIO_LI_OUT_STATUS_LVDS_CTRL_Pos 8UL 1320 #define LVDSSS_LVDS_AFE_LICIO_LI_OUT_STATUS_LVDS_CTRL_Msk 0x100UL 1321 #define LVDSSS_LVDS_AFE_LICIO_LI_OUT_STATUS_LVDS_CLK_Pos 9UL 1322 #define LVDSSS_LVDS_AFE_LICIO_LI_OUT_STATUS_LVDS_CLK_Msk 0x200UL 1323 /* LVDSSS_LVDS_AFE.PLL_CONFIG */ 1324 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_CP_CUR_TRIM_Pos 0UL 1325 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_CP_CUR_TRIM_Msk 0x3UL 1326 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_BYPASS_Pos 2UL 1327 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_BYPASS_Msk 0x4UL 1328 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_PFD_DELAY_Pos 3UL 1329 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_PFD_DELAY_Msk 0x18UL 1330 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_LD_DELAY_Pos 5UL 1331 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_LD_DELAY_Msk 0x60UL 1332 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_EN_Pos 7UL 1333 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_EN_Msk 0x80UL 1334 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_REG_VCO_BYPASS_Pos 8UL 1335 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_REG_VCO_BYPASS_Msk 0x100UL 1336 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_REF_SEL_Pos 9UL 1337 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_REF_SEL_Msk 0x600UL 1338 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_SUPPLY_EN_Pos 11UL 1339 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_SUPPLY_EN_Msk 0x800UL 1340 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_IN_DIV_Pos 12UL 1341 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_IN_DIV_Msk 0x3000UL 1342 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_SERIAL_DIV_Pos 15UL 1343 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_SERIAL_DIV_Msk 0x18000UL 1344 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_FRAME_DIV_Pos 17UL 1345 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_FRAME_DIV_Msk 0x20000UL 1346 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_FB_DIV_Pos 18UL 1347 #define LVDSSS_LVDS_AFE_PLL_CONFIG_N_FB_DIV_Msk 0x3C0000UL 1348 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_ATST_SEL_Pos 22UL 1349 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_ATST_SEL_Msk 0x3C00000UL 1350 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_RUN_AWAY_DIS_Pos 26UL 1351 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_RUN_AWAY_DIS_Msk 0x4000000UL 1352 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_RUN_AWAY_TRIM_Pos 27UL 1353 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_RUN_AWAY_TRIM_Msk 0x18000000UL 1354 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_RUN_AWAY_DEL_Pos 29UL 1355 #define LVDSSS_LVDS_AFE_PLL_CONFIG_PLL_RUN_AWAY_DEL_Msk 0x60000000UL 1356 /* LVDSSS_LVDS_AFE.PLL_CONFIG_2 */ 1357 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_REG_CORE_TRIM_Pos 0UL 1358 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_REG_CORE_TRIM_Msk 0x7UL 1359 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CAL_UP_DN_Pos 3UL 1360 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CAL_UP_DN_Msk 0x78UL 1361 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_RA_UP_TR_Pos 7UL 1362 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_RA_UP_TR_Msk 0x180UL 1363 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_VCO_GAIN_Pos 9UL 1364 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_VCO_GAIN_Msk 0x1E00UL 1365 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_FB_SEL_Pos 13UL 1366 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_FB_SEL_Msk 0x6000UL 1367 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_MD_Pos 15UL 1368 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_MD_Msk 0x8000UL 1369 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_LOCK_DELAY_Pos 16UL 1370 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_LOCK_DELAY_Msk 0xFF0000UL 1371 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_LOCK_LOSS_DELAY_Pos 24UL 1372 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_LOCK_LOSS_DELAY_Msk 0x1F000000UL 1373 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_EN_OVRDE_Pos 29UL 1374 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_EN_OVRDE_Msk 0x20000000UL 1375 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_OVRDE_LOCK_VAL_Pos 30UL 1376 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_OVRDE_LOCK_VAL_Msk 0x40000000UL 1377 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_SOURCE_LOCK_Pos 31UL 1378 #define LVDSSS_LVDS_AFE_PLL_CONFIG_2_PLL_CTRL_SOURCE_LOCK_Msk 0x80000000UL 1379 /* LVDSSS_LVDS_AFE.PLL_STATUS */ 1380 #define LVDSSS_LVDS_AFE_PLL_STATUS_PLL_DFT_Pos 0UL 1381 #define LVDSSS_LVDS_AFE_PLL_STATUS_PLL_DFT_Msk 0x1UL 1382 #define LVDSSS_LVDS_AFE_PLL_STATUS_PLL_LOCK_Pos 1UL 1383 #define LVDSSS_LVDS_AFE_PLL_STATUS_PLL_LOCK_Msk 0x2UL 1384 #define LVDSSS_LVDS_AFE_PLL_STATUS_PLL_RUN_AWAY_STICKY_Pos 2UL 1385 #define LVDSSS_LVDS_AFE_PLL_STATUS_PLL_RUN_AWAY_STICKY_Msk 0x4UL 1386 /* LVDSSS_LVDS_AFE.REG_1P25 */ 1387 #define LVDSSS_LVDS_AFE_REG_1P25_IREF_DLL_SEL_Pos 0UL 1388 #define LVDSSS_LVDS_AFE_REG_1P25_IREF_DLL_SEL_Msk 0x7UL 1389 #define LVDSSS_LVDS_AFE_REG_1P25_ENABLE_Pos 3UL 1390 #define LVDSSS_LVDS_AFE_REG_1P25_ENABLE_Msk 0x8UL 1391 #define LVDSSS_LVDS_AFE_REG_1P25_USE_REG_Pos 4UL 1392 #define LVDSSS_LVDS_AFE_REG_1P25_USE_REG_Msk 0x10UL 1393 #define LVDSSS_LVDS_AFE_REG_1P25_ADFT_CTRL_Pos 5UL 1394 #define LVDSSS_LVDS_AFE_REG_1P25_ADFT_CTRL_Msk 0x1E0UL 1395 #define LVDSSS_LVDS_AFE_REG_1P25_ADFT_EN_Pos 9UL 1396 #define LVDSSS_LVDS_AFE_REG_1P25_ADFT_EN_Msk 0x200UL 1397 #define LVDSSS_LVDS_AFE_REG_1P25_BURN_IN_EN_Pos 10UL 1398 #define LVDSSS_LVDS_AFE_REG_1P25_BURN_IN_EN_Msk 0x400UL 1399 #define LVDSSS_LVDS_AFE_REG_1P25_TRIM_VREG_1P25_Pos 11UL 1400 #define LVDSSS_LVDS_AFE_REG_1P25_TRIM_VREG_1P25_Msk 0x7800UL 1401 /* LVDSSS_LVDS_AFE.RX */ 1402 #define LVDSSS_LVDS_AFE_RX_FIXTIME_FRAMECLK_Pos 0UL 1403 #define LVDSSS_LVDS_AFE_RX_FIXTIME_FRAMECLK_Msk 0x1UL 1404 #define LVDSSS_LVDS_AFE_RX_EN_DESER_Pos 1UL 1405 #define LVDSSS_LVDS_AFE_RX_EN_DESER_Msk 0x2UL 1406 #define LVDSSS_LVDS_AFE_RX_INV_CLK_FRAME_Pos 2UL 1407 #define LVDSSS_LVDS_AFE_RX_INV_CLK_FRAME_Msk 0x4UL 1408 #define LVDSSS_LVDS_AFE_RX_INV_CLK_SER_Pos 3UL 1409 #define LVDSSS_LVDS_AFE_RX_INV_CLK_SER_Msk 0x8UL 1410 #define LVDSSS_LVDS_AFE_RX_INV_DATA_SER_Pos 4UL 1411 #define LVDSSS_LVDS_AFE_RX_INV_DATA_SER_Msk 0x10UL 1412 #define LVDSSS_LVDS_AFE_RX_CLK_MUX_SEL_Pos 5UL 1413 #define LVDSSS_LVDS_AFE_RX_CLK_MUX_SEL_Msk 0x60UL 1414 /* LVDSSS_LVDS_AFE.GENERAL_RX */ 1415 #define LVDSSS_LVDS_AFE_GENERAL_RX_DR_MODE_Pos 0UL 1416 #define LVDSSS_LVDS_AFE_GENERAL_RX_DR_MODE_Msk 0x1UL 1417 #define LVDSSS_LVDS_AFE_GENERAL_RX_BER_RSTN_Pos 1UL 1418 #define LVDSSS_LVDS_AFE_GENERAL_RX_BER_RSTN_Msk 0x2UL 1419 #define LVDSSS_LVDS_AFE_GENERAL_RX_DLL_BYPASS_EN_Pos 2UL 1420 #define LVDSSS_LVDS_AFE_GENERAL_RX_DLL_BYPASS_EN_Msk 0x4UL 1421 #define LVDSSS_LVDS_AFE_GENERAL_RX_LSB_FIRST_MODE_Pos 3UL 1422 #define LVDSSS_LVDS_AFE_GENERAL_RX_LSB_FIRST_MODE_Msk 0x8UL 1423 /* LVDSSS_LVDS_AFE.GENERAL_RX_LVCMOS */ 1424 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_CLK_MODE_Pos 1UL 1425 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_CLK_MODE_Msk 0x2UL 1426 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_EN_DDR_Pos 2UL 1427 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_EN_DDR_Msk 0x4UL 1428 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_CLK_BYPASS_Pos 3UL 1429 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_CLK_BYPASS_Msk 0x8UL 1430 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_MUX_SEL_Pos 4UL 1431 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_MUX_SEL_Msk 0x10UL 1432 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_PLL_CLK_EN_Pos 5UL 1433 #define LVDSSS_LVDS_AFE_GENERAL_RX_LVCMOS_PLL_CLK_EN_Msk 0x20UL 1434 /* LVDSSS_LVDS_AFE.RX_LVCMOS */ 1435 #define LVDSSS_LVDS_AFE_RX_LVCMOS_EN_LVCMOS_Pos 0UL 1436 #define LVDSSS_LVDS_AFE_RX_LVCMOS_EN_LVCMOS_Msk 0x1UL 1437 /* LVDSSS_LVDS_AFE.PRBS_GEN */ 1438 #define LVDSSS_LVDS_AFE_PRBS_GEN_EN_Pos 0UL 1439 #define LVDSSS_LVDS_AFE_PRBS_GEN_EN_Msk 0x1UL 1440 #define LVDSSS_LVDS_AFE_PRBS_GEN_SEED_Pos 1UL 1441 #define LVDSSS_LVDS_AFE_PRBS_GEN_SEED_Msk 0x3EUL 1442 #define LVDSSS_LVDS_AFE_PRBS_GEN_DDR_EN_Pos 6UL 1443 #define LVDSSS_LVDS_AFE_PRBS_GEN_DDR_EN_Msk 0x40UL 1444 #define LVDSSS_LVDS_AFE_PRBS_GEN_MULT_ERR_EN_Pos 7UL 1445 #define LVDSSS_LVDS_AFE_PRBS_GEN_MULT_ERR_EN_Msk 0x80UL 1446 #define LVDSSS_LVDS_AFE_PRBS_GEN_CLK_SRC_Pos 8UL 1447 #define LVDSSS_LVDS_AFE_PRBS_GEN_CLK_SRC_Msk 0x100UL 1448 /* LVDSSS_LVDS_AFE.PHY_GENERAL_CONFIG */ 1449 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_DESKEW_ALGORITHM_Pos 0UL 1450 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_DESKEW_ALGORITHM_Msk 0x3UL 1451 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_SCANON_Pos 2UL 1452 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_SCANON_Msk 0x4UL 1453 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_V1P25_VCCD_Pos 3UL 1454 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_V1P25_VCCD_Msk 0x8UL 1455 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_V1P1_VCCD_Pos 4UL 1456 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_V1P1_VCCD_Msk 0x10UL 1457 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_VDDIO_Pos 5UL 1458 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_ENABLE_VDDIO_Msk 0x20UL 1459 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_LVCMOS_TX_CLKSEL_Pos 6UL 1460 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_LVCMOS_TX_CLKSEL_Msk 0xC0UL 1461 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_BERCLK_SKEW_MARGIN_Pos 8UL 1462 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_BERCLK_SKEW_MARGIN_Msk 0x300UL 1463 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_MONITOR_FREQ_Pos 10UL 1464 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_MONITOR_FREQ_Msk 0x1C00UL 1465 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_MONITOR_TIME_Pos 13UL 1466 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_MONITOR_TIME_Msk 0xE000UL 1467 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_MONITOR_NON_STOP_Pos 16UL 1468 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_MONITOR_NON_STOP_Msk 0x10000UL 1469 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_DESKEW_ERR_THRESH1_Pos 17UL 1470 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_DESKEW_ERR_THRESH1_Msk 0xFE0000UL 1471 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_DESKEW_ERR_THRESH2_Pos 24UL 1472 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_DESKEW_ERR_THRESH2_Msk 0x7F000000UL 1473 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_BIST_RLXD_MARGIN_SEL_Pos 31UL 1474 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_BIST_RLXD_MARGIN_SEL_Msk 0x80000000UL 1475 /* LVDSSS_LVDS_AFE.PHY_GENERAL_STATUS_1 */ 1476 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D0_Pos 0UL 1477 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D0_Msk 0x3UL 1478 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D1_Pos 2UL 1479 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D1_Msk 0xCUL 1480 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D2_Pos 4UL 1481 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D2_Msk 0x30UL 1482 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D3_Pos 6UL 1483 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D3_Msk 0xC0UL 1484 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D4_Pos 8UL 1485 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D4_Msk 0x300UL 1486 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D5_Pos 10UL 1487 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D5_Msk 0xC00UL 1488 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D6_Pos 12UL 1489 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D6_Msk 0x3000UL 1490 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D7_Pos 14UL 1491 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_D7_Msk 0xC000UL 1492 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_CTRL_Pos 16UL 1493 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_CHECKER_STATE_CTRL_Msk 0x30000UL 1494 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_RUN_STATUS_Pos 18UL 1495 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_1_PRBS_RUN_STATUS_Msk 0x40000UL 1496 /* LVDSSS_LVDS_AFE.PHY_GENERAL_STATUS_2 */ 1497 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_LOOPBACK_STOPPED_Pos 0UL 1498 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_LOOPBACK_STOPPED_Msk 0x1UL 1499 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MONITOR_RUNNING_Pos 1UL 1500 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MONITOR_RUNNING_Msk 0x2UL 1501 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MONITOR_COMPLETED_Pos 2UL 1502 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MONITOR_COMPLETED_Msk 0x4UL 1503 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_DESKEW_RUNNING_Pos 3UL 1504 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_DESKEW_RUNNING_Msk 0x8UL 1505 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_DESKEW_COMPLETED_Pos 4UL 1506 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_DESKEW_COMPLETED_Msk 0x10UL 1507 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MONITOR_ADJUST_FAIL_Pos 5UL 1508 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MONITOR_ADJUST_FAIL_Msk 0x20UL 1509 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_OK_DLL_VCCD_Pos 6UL 1510 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_OK_DLL_VCCD_Msk 0x40UL 1511 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_OK_V1P1_VCCD_Pos 7UL 1512 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_OK_V1P1_VCCD_Msk 0x80UL 1513 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_OK_V1P25_VCCD_Pos 8UL 1514 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_OK_V1P25_VCCD_Msk 0x100UL 1515 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_PLL_LOCK_ACQUIRED_Pos 10UL 1516 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_PLL_LOCK_ACQUIRED_Msk 0x400UL 1517 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_PLL_LOCK_LOST_Pos 11UL 1518 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_PLL_LOCK_LOST_Msk 0x800UL 1519 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MDLL_LOCK_ACQUIRED_Pos 12UL 1520 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MDLL_LOCK_ACQUIRED_Msk 0x1000UL 1521 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MDLL_LOCK_LOST_Pos 13UL 1522 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_MDLL_LOCK_LOST_Msk 0x2000UL 1523 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_BIST_MDLL_DONE_Pos 14UL 1524 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_BIST_MDLL_DONE_Msk 0x4000UL 1525 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_BIST_SDLL_DONE_Pos 15UL 1526 #define LVDSSS_LVDS_AFE_PHY_GENERAL_STATUS_2_BIST_SDLL_DONE_Msk 0x8000UL 1527 /* LVDSSS_LVDS_AFE.PHY_INTR */ 1528 #define LVDSSS_LVDS_AFE_PHY_INTR_LOOPBACK_STOPPED_Pos 0UL 1529 #define LVDSSS_LVDS_AFE_PHY_INTR_LOOPBACK_STOPPED_Msk 0x1UL 1530 #define LVDSSS_LVDS_AFE_PHY_INTR_MONITOR_RUNNING_Pos 1UL 1531 #define LVDSSS_LVDS_AFE_PHY_INTR_MONITOR_RUNNING_Msk 0x2UL 1532 #define LVDSSS_LVDS_AFE_PHY_INTR_MONITOR_COMPLETED_Pos 2UL 1533 #define LVDSSS_LVDS_AFE_PHY_INTR_MONITOR_COMPLETED_Msk 0x4UL 1534 #define LVDSSS_LVDS_AFE_PHY_INTR_DESKEW_RUNNING_Pos 3UL 1535 #define LVDSSS_LVDS_AFE_PHY_INTR_DESKEW_RUNNING_Msk 0x8UL 1536 #define LVDSSS_LVDS_AFE_PHY_INTR_DESKEW_COMPLETED_Pos 4UL 1537 #define LVDSSS_LVDS_AFE_PHY_INTR_DESKEW_COMPLETED_Msk 0x10UL 1538 #define LVDSSS_LVDS_AFE_PHY_INTR_MONITOR_ADJUST_FAIL_Pos 5UL 1539 #define LVDSSS_LVDS_AFE_PHY_INTR_MONITOR_ADJUST_FAIL_Msk 0x20UL 1540 #define LVDSSS_LVDS_AFE_PHY_INTR_OK_DLL_VCCD_Pos 6UL 1541 #define LVDSSS_LVDS_AFE_PHY_INTR_OK_DLL_VCCD_Msk 0x40UL 1542 #define LVDSSS_LVDS_AFE_PHY_INTR_OK_V1P1_VCCD_Pos 7UL 1543 #define LVDSSS_LVDS_AFE_PHY_INTR_OK_V1P1_VCCD_Msk 0x80UL 1544 #define LVDSSS_LVDS_AFE_PHY_INTR_OK_V1P25_VCCD_Pos 8UL 1545 #define LVDSSS_LVDS_AFE_PHY_INTR_OK_V1P25_VCCD_Msk 0x100UL 1546 #define LVDSSS_LVDS_AFE_PHY_INTR_GPIO_INTR_Pos 9UL 1547 #define LVDSSS_LVDS_AFE_PHY_INTR_GPIO_INTR_Msk 0x200UL 1548 #define LVDSSS_LVDS_AFE_PHY_INTR_PLL_LOCK_ACQUIRED_Pos 10UL 1549 #define LVDSSS_LVDS_AFE_PHY_INTR_PLL_LOCK_ACQUIRED_Msk 0x400UL 1550 #define LVDSSS_LVDS_AFE_PHY_INTR_PLL_LOCK_LOST_Pos 11UL 1551 #define LVDSSS_LVDS_AFE_PHY_INTR_PLL_LOCK_LOST_Msk 0x800UL 1552 #define LVDSSS_LVDS_AFE_PHY_INTR_MDLL_LOCK_ACQUIRED_Pos 12UL 1553 #define LVDSSS_LVDS_AFE_PHY_INTR_MDLL_LOCK_ACQUIRED_Msk 0x1000UL 1554 #define LVDSSS_LVDS_AFE_PHY_INTR_MDLL_LOCK_LOST_Pos 13UL 1555 #define LVDSSS_LVDS_AFE_PHY_INTR_MDLL_LOCK_LOST_Msk 0x2000UL 1556 #define LVDSSS_LVDS_AFE_PHY_INTR_BIST_MDLL_DONE_Pos 14UL 1557 #define LVDSSS_LVDS_AFE_PHY_INTR_BIST_MDLL_DONE_Msk 0x4000UL 1558 #define LVDSSS_LVDS_AFE_PHY_INTR_BIST_SDLL_DONE_Pos 15UL 1559 #define LVDSSS_LVDS_AFE_PHY_INTR_BIST_SDLL_DONE_Msk 0x8000UL 1560 #define LVDSSS_LVDS_AFE_PHY_INTR_SAR_DONE_Pos 16UL 1561 #define LVDSSS_LVDS_AFE_PHY_INTR_SAR_DONE_Msk 0x10000UL 1562 #define LVDSSS_LVDS_AFE_PHY_INTR_ADC_CMP_OUT_POS_EDGE_Pos 17UL 1563 #define LVDSSS_LVDS_AFE_PHY_INTR_ADC_CMP_OUT_POS_EDGE_Msk 0x20000UL 1564 #define LVDSSS_LVDS_AFE_PHY_INTR_ADC_CMP_OUT_FALL_EDGE_Pos 18UL 1565 #define LVDSSS_LVDS_AFE_PHY_INTR_ADC_CMP_OUT_FALL_EDGE_Msk 0x40000UL 1566 /* LVDSSS_LVDS_AFE.PHY_INTR_MASK */ 1567 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_LOOPBACK_STOPPED_Pos 0UL 1568 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_LOOPBACK_STOPPED_Msk 0x1UL 1569 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MONITOR_RUNNING_Pos 1UL 1570 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MONITOR_RUNNING_Msk 0x2UL 1571 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MONITOR_COMPLETED_Pos 2UL 1572 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MONITOR_COMPLETED_Msk 0x4UL 1573 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_DESKEW_RUNNING_Pos 3UL 1574 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_DESKEW_RUNNING_Msk 0x8UL 1575 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_DESKEW_COMPLETED_Pos 4UL 1576 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_DESKEW_COMPLETED_Msk 0x10UL 1577 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MONITOR_ADJUST_FAIL_Pos 5UL 1578 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MONITOR_ADJUST_FAIL_Msk 0x20UL 1579 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_OK_DLL_VCCD_Pos 6UL 1580 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_OK_DLL_VCCD_Msk 0x40UL 1581 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_OK_V1P1_VCCD_Pos 7UL 1582 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_OK_V1P1_VCCD_Msk 0x80UL 1583 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_OK_V1P25_VCCD_Pos 8UL 1584 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_OK_V1P25_VCCD_Msk 0x100UL 1585 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_GPIO_INTR_Pos 9UL 1586 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_GPIO_INTR_Msk 0x200UL 1587 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_PLL_LOCK_ACQUIRED_Pos 10UL 1588 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_PLL_LOCK_ACQUIRED_Msk 0x400UL 1589 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_PLL_LOCK_LOST_Pos 11UL 1590 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_PLL_LOCK_LOST_Msk 0x800UL 1591 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MDLL_LOCK_ACQUIRED_Pos 12UL 1592 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MDLL_LOCK_ACQUIRED_Msk 0x1000UL 1593 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MDLL_LOCK_LOST_Pos 13UL 1594 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_MDLL_LOCK_LOST_Msk 0x2000UL 1595 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_BIST_MDLL_DONE_Pos 14UL 1596 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_BIST_MDLL_DONE_Msk 0x4000UL 1597 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_BIST_SDLL_DONE_Pos 15UL 1598 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_BIST_SDLL_DONE_Msk 0x8000UL 1599 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_SAR_DONE_Pos 16UL 1600 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_SAR_DONE_Msk 0x10000UL 1601 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_ADC_CMP_OUT_POS_EDGE_Pos 17UL 1602 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_ADC_CMP_OUT_POS_EDGE_Msk 0x20000UL 1603 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_ADC_CMP_OUT_FALL_EDGE_Pos 18UL 1604 #define LVDSSS_LVDS_AFE_PHY_INTR_MASK_ADC_CMP_OUT_FALL_EDGE_Msk 0x40000UL 1605 /* LVDSSS_LVDS_AFE.PHY_INTR_MASKED */ 1606 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_LOOPBACK_STOPPED_Pos 0UL 1607 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_LOOPBACK_STOPPED_Msk 0x1UL 1608 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MONITOR_RUNNING_Pos 1UL 1609 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MONITOR_RUNNING_Msk 0x2UL 1610 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MONITOR_COMPLETED_Pos 2UL 1611 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MONITOR_COMPLETED_Msk 0x4UL 1612 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_DESKEW_RUNNING_Pos 3UL 1613 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_DESKEW_RUNNING_Msk 0x8UL 1614 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_DESKEW_COMPLETED_Pos 4UL 1615 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_DESKEW_COMPLETED_Msk 0x10UL 1616 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MONITOR_ADJUST_FAIL_Pos 5UL 1617 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MONITOR_ADJUST_FAIL_Msk 0x20UL 1618 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_OK_DLL_VCCD_Pos 6UL 1619 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_OK_DLL_VCCD_Msk 0x40UL 1620 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_OK_V1P1_VCCD_Pos 7UL 1621 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_OK_V1P1_VCCD_Msk 0x80UL 1622 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_OK_V1P25_VCCD_Pos 8UL 1623 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_OK_V1P25_VCCD_Msk 0x100UL 1624 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_GPIO_INTR_Pos 9UL 1625 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_GPIO_INTR_Msk 0x200UL 1626 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_PLL_LOCK_ACQUIRED_Pos 10UL 1627 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_PLL_LOCK_ACQUIRED_Msk 0x400UL 1628 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_PLL_LOCK_LOST_Pos 11UL 1629 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_PLL_LOCK_LOST_Msk 0x800UL 1630 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MDLL_LOCK_ACQUIRED_Pos 12UL 1631 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MDLL_LOCK_ACQUIRED_Msk 0x1000UL 1632 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MDLL_LOCK_LOST_Pos 13UL 1633 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_MDLL_LOCK_LOST_Msk 0x2000UL 1634 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_BIST_MDLL_DONE_Pos 14UL 1635 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_BIST_MDLL_DONE_Msk 0x4000UL 1636 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_BIST_SDLL_DONE_Pos 15UL 1637 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_BIST_SDLL_DONE_Msk 0x8000UL 1638 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_SAR_DONE_Pos 16UL 1639 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_SAR_DONE_Msk 0x10000UL 1640 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_ADC_CMP_OUT_POS_EDGE_Pos 17UL 1641 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_ADC_CMP_OUT_POS_EDGE_Msk 0x20000UL 1642 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_ADC_CMP_OUT_FALL_EDGE_Pos 18UL 1643 #define LVDSSS_LVDS_AFE_PHY_INTR_MASKED_ADC_CMP_OUT_FALL_EDGE_Msk 0x40000UL 1644 /* LVDSSS_LVDS_AFE.PHY_INTR_SET */ 1645 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_LOOPBACK_STOPPED_Pos 0UL 1646 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_LOOPBACK_STOPPED_Msk 0x1UL 1647 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MONITOR_RUNNING_Pos 1UL 1648 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MONITOR_RUNNING_Msk 0x2UL 1649 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MONITOR_COMPLETED_Pos 2UL 1650 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MONITOR_COMPLETED_Msk 0x4UL 1651 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_DESKEW_RUNNING_Pos 3UL 1652 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_DESKEW_RUNNING_Msk 0x8UL 1653 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_DESKEW_COMPLETED_Pos 4UL 1654 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_DESKEW_COMPLETED_Msk 0x10UL 1655 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MONITOR_ADJUST_FAIL_Pos 5UL 1656 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MONITOR_ADJUST_FAIL_Msk 0x20UL 1657 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_OK_DLL_VCCD_Pos 6UL 1658 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_OK_DLL_VCCD_Msk 0x40UL 1659 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_OK_V1P1_VCCD_Pos 7UL 1660 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_OK_V1P1_VCCD_Msk 0x80UL 1661 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_OK_V1P25_VCCD_Pos 8UL 1662 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_OK_V1P25_VCCD_Msk 0x100UL 1663 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_GPIO_INTR_Pos 9UL 1664 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_GPIO_INTR_Msk 0x200UL 1665 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_PLL_LOCK_ACQUIRED_Pos 10UL 1666 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_PLL_LOCK_ACQUIRED_Msk 0x400UL 1667 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_PLL_LOCK_LOST_Pos 11UL 1668 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_PLL_LOCK_LOST_Msk 0x800UL 1669 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MDLL_LOCK_ACQUIRED_Pos 12UL 1670 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MDLL_LOCK_ACQUIRED_Msk 0x1000UL 1671 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MDLL_LOCK_LOST_Pos 13UL 1672 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_MDLL_LOCK_LOST_Msk 0x2000UL 1673 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_BIST_MDLL_DONE_Pos 14UL 1674 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_BIST_MDLL_DONE_Msk 0x4000UL 1675 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_BIST_SDLL_DONE_Pos 15UL 1676 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_BIST_SDLL_DONE_Msk 0x8000UL 1677 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_SAR_DONE_Pos 16UL 1678 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_SAR_DONE_Msk 0x10000UL 1679 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_ADC_CMP_OUT_POS_EDGE_Pos 17UL 1680 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_ADC_CMP_OUT_POS_EDGE_Msk 0x20000UL 1681 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_ADC_CMP_OUT_FALL_EDGE_Pos 18UL 1682 #define LVDSSS_LVDS_AFE_PHY_INTR_SET_ADC_CMP_OUT_FALL_EDGE_Msk 0x40000UL 1683 /* LVDSSS_LVDS_AFE.PHY_TRAIN_CONFIG */ 1684 #define LVDSSS_LVDS_AFE_PHY_TRAIN_CONFIG_TRAIN_EN_Pos 0UL 1685 #define LVDSSS_LVDS_AFE_PHY_TRAIN_CONFIG_TRAIN_EN_Msk 0x1UL 1686 #define LVDSSS_LVDS_AFE_PHY_TRAIN_CONFIG_TRAIN_SEQ_Pos 1UL 1687 #define LVDSSS_LVDS_AFE_PHY_TRAIN_CONFIG_TRAIN_SEQ_Msk 0x1FEUL 1688 #define LVDSSS_LVDS_AFE_PHY_TRAIN_CONFIG_TRAIN_CYCLES_NO_Pos 9UL 1689 #define LVDSSS_LVDS_AFE_PHY_TRAIN_CONFIG_TRAIN_CYCLES_NO_Msk 0xFE00UL 1690 /* LVDSSS_LVDS_AFE.PHY_ADC_CONFIG */ 1691 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_DAC_CNTRL_Pos 0UL 1692 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_DAC_CNTRL_Msk 0xFFUL 1693 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_MID_VAL_Pos 8UL 1694 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_MID_VAL_Msk 0xFF00UL 1695 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_LDO_TRIM_Pos 16UL 1696 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_LDO_TRIM_Msk 0xF0000UL 1697 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_LDO_EN_Pos 20UL 1698 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_LDO_EN_Msk 0x100000UL 1699 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_ISO_N_Pos 21UL 1700 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_ISO_N_Msk 0x200000UL 1701 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_PD_LV_Pos 22UL 1702 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_PD_LV_Msk 0x400000UL 1703 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_DFT_MUXSEL_Pos 23UL 1704 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_DFT_MUXSEL_Msk 0x800000UL 1705 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_VSEL_Pos 24UL 1706 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_VSEL_Msk 0x7000000UL 1707 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_VREF_DAC_SEL_Pos 27UL 1708 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_VREF_DAC_SEL_Msk 0x18000000UL 1709 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_SAR_EN_Pos 29UL 1710 #define LVDSSS_LVDS_AFE_PHY_ADC_CONFIG_SAR_EN_Msk 0x20000000UL 1711 /* LVDSSS_LVDS_AFE.PHY_DDFT_MUX_SEL */ 1712 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT0_MUX_SEL_Pos 0UL 1713 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT0_MUX_SEL_Msk 0x3FUL 1714 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT0_LVCMOSOUT_SEL_Pos 6UL 1715 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT0_LVCMOSOUT_SEL_Msk 0x40UL 1716 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT0_LINK_SEL_Pos 7UL 1717 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT0_LINK_SEL_Msk 0x80UL 1718 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT1_MUX_SEL_Pos 8UL 1719 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT1_MUX_SEL_Msk 0x3F00UL 1720 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT1_LVCMOSOUT_SEL_Pos 14UL 1721 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT1_LVCMOSOUT_SEL_Msk 0x4000UL 1722 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT1_LINK_SEL_Pos 15UL 1723 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_DDFT1_LINK_SEL_Msk 0x8000UL 1724 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO0_MUX_SEL_Pos 16UL 1725 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO0_MUX_SEL_Msk 0x3F0000UL 1726 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO0_LINK_SEL_Pos 23UL 1727 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO0_LINK_SEL_Msk 0x800000UL 1728 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO1_MUX_SEL_Pos 24UL 1729 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO1_MUX_SEL_Msk 0x3F000000UL 1730 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO1_LINK_SEL_Pos 31UL 1731 #define LVDSSS_LVDS_AFE_PHY_DDFT_MUX_SEL_GPIO1_LINK_SEL_Msk 0x80000000UL 1732 /* LVDSSS_LVDS_AFE.LICIO_VCCD_V1P1 */ 1733 #define LVDSSS_LVDS_AFE_LICIO_VCCD_V1P1_EN_Pos 0UL 1734 #define LVDSSS_LVDS_AFE_LICIO_VCCD_V1P1_EN_Msk 0x1UL 1735 #define LVDSSS_LVDS_AFE_LICIO_VCCD_V1P1_ATST_EN_Pos 3UL 1736 #define LVDSSS_LVDS_AFE_LICIO_VCCD_V1P1_ATST_EN_Msk 0x8UL 1737 /* LVDSSS_LVDS_AFE.PHY_GPIO */ 1738 #define LVDSSS_LVDS_AFE_PHY_GPIO_OUT_VALUE_Pos 0UL 1739 #define LVDSSS_LVDS_AFE_PHY_GPIO_OUT_VALUE_Msk 0x1UL 1740 #define LVDSSS_LVDS_AFE_PHY_GPIO_IN_VALUE_Pos 1UL 1741 #define LVDSSS_LVDS_AFE_PHY_GPIO_IN_VALUE_Msk 0x2UL 1742 #define LVDSSS_LVDS_AFE_PHY_GPIO_OUTPUT_EN_Pos 2UL 1743 #define LVDSSS_LVDS_AFE_PHY_GPIO_OUTPUT_EN_Msk 0x4UL 1744 #define LVDSSS_LVDS_AFE_PHY_GPIO_INPUT_EN_Pos 3UL 1745 #define LVDSSS_LVDS_AFE_PHY_GPIO_INPUT_EN_Msk 0x8UL 1746 #define LVDSSS_LVDS_AFE_PHY_GPIO_GPIO_ENABLE_Pos 31UL 1747 #define LVDSSS_LVDS_AFE_PHY_GPIO_GPIO_ENABLE_Msk 0x80000000UL 1748 /* LVDSSS_LVDS_AFE.PHY_GPIO_INTR_CFG */ 1749 #define LVDSSS_LVDS_AFE_PHY_GPIO_INTR_CFG_GPIO_INTR_PIN_SEL_Pos 0UL 1750 #define LVDSSS_LVDS_AFE_PHY_GPIO_INTR_CFG_GPIO_INTR_PIN_SEL_Msk 0x1FUL 1751 #define LVDSSS_LVDS_AFE_PHY_GPIO_INTR_CFG_INTRMODE_Pos 8UL 1752 #define LVDSSS_LVDS_AFE_PHY_GPIO_INTR_CFG_INTRMODE_Msk 0x700UL 1753 /* LVDSSS_LVDS_AFE.PHY_GENERAL_CONFIG_2 */ 1754 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_2_CNT_10US24_VAL_Pos 0UL 1755 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_2_CNT_10US24_VAL_Msk 0xFFFFUL 1756 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_2_MONITOR_ERR_THRESH_Pos 16UL 1757 #define LVDSSS_LVDS_AFE_PHY_GENERAL_CONFIG_2_MONITOR_ERR_THRESH_Msk 0xFFFF0000UL 1758 /* LVDSSS_LVDS_AFE.PRBS_STATUS */ 1759 #define LVDSSS_LVDS_AFE_PRBS_STATUS_BER_COUNTER_Pos 0UL 1760 #define LVDSSS_LVDS_AFE_PRBS_STATUS_BER_COUNTER_Msk 0xFFFFFFFFUL 1761 /* LVDSSS_LVDS_AFE.LVDS_STATUS_MONITOR */ 1762 #define LVDSSS_LVDS_AFE_LVDS_STATUS_MONITOR_LVDS_PAD_VALUE_Pos 0UL 1763 #define LVDSSS_LVDS_AFE_LVDS_STATUS_MONITOR_LVDS_PAD_VALUE_Msk 0x1UL 1764 #define LVDSSS_LVDS_AFE_LVDS_STATUS_MONITOR_LVDS_PAD_RDEN_Pos 1UL 1765 #define LVDSSS_LVDS_AFE_LVDS_STATUS_MONITOR_LVDS_PAD_RDEN_Msk 0x2UL 1766 /* LVDSSS_LVDS_AFE.PHY_ADC_STATUS */ 1767 #define LVDSSS_LVDS_AFE_PHY_ADC_STATUS_CMP_OUT_Pos 0UL 1768 #define LVDSSS_LVDS_AFE_PHY_ADC_STATUS_CMP_OUT_Msk 0x1UL 1769 #define LVDSSS_LVDS_AFE_PHY_ADC_STATUS_SAR_OUT_Pos 8UL 1770 #define LVDSSS_LVDS_AFE_PHY_ADC_STATUS_SAR_OUT_Msk 0xFF00UL 1771 /* LVDSSS_LVDS_AFE.FRM_CLK_GLITCH_FILTER */ 1772 #define LVDSSS_LVDS_AFE_FRM_CLK_GLITCH_FILTER_CLKGATE_DURATION_Pos 0UL 1773 #define LVDSSS_LVDS_AFE_FRM_CLK_GLITCH_FILTER_CLKGATE_DURATION_Msk 0xFFUL 1774 #define LVDSSS_LVDS_AFE_FRM_CLK_GLITCH_FILTER_PHASE_CHNG_EFFECT_TIME_Pos 8UL 1775 #define LVDSSS_LVDS_AFE_FRM_CLK_GLITCH_FILTER_PHASE_CHNG_EFFECT_TIME_Msk 0xFF00UL 1776 #define LVDSSS_LVDS_AFE_FRM_CLK_GLITCH_FILTER_BYPASS_GLITCH_FILTER_Pos 16UL 1777 #define LVDSSS_LVDS_AFE_FRM_CLK_GLITCH_FILTER_BYPASS_GLITCH_FILTER_Msk 0x10000UL 1778 /* LVDSSS_LVDS_AFE.LICIO_CIO_CTRL_DS */ 1779 #define LVDSSS_LVDS_AFE_LICIO_CIO_CTRL_DS_DS_Pos 0UL 1780 #define LVDSSS_LVDS_AFE_LICIO_CIO_CTRL_DS_DS_Msk 0x1FUL 1781 #define LVDSSS_LVDS_AFE_LICIO_CIO_CTRL_DS_SR_Pos 8UL 1782 #define LVDSSS_LVDS_AFE_LICIO_CIO_CTRL_DS_SR_Msk 0x300UL 1783 /* LVDSSS_LVDS_AFE.LICIO_CIO_DATA_DS */ 1784 #define LVDSSS_LVDS_AFE_LICIO_CIO_DATA_DS_DS_Pos 0UL 1785 #define LVDSSS_LVDS_AFE_LICIO_CIO_DATA_DS_DS_Msk 0x1FUL 1786 #define LVDSSS_LVDS_AFE_LICIO_CIO_DATA_DS_SR_Pos 8UL 1787 #define LVDSSS_LVDS_AFE_LICIO_CIO_DATA_DS_SR_Msk 0x300UL 1788 /* LVDSSS_LVDS_AFE.DLY_CELL_LOAD */ 1789 #define LVDSSS_LVDS_AFE_DLY_CELL_LOAD_LOAD_Pos 0UL 1790 #define LVDSSS_LVDS_AFE_DLY_CELL_LOAD_LOAD_Msk 0x3UL 1791 /* LVDSSS_LVDS_AFE.SAR_CLK_FREQ_CFG */ 1792 #define LVDSSS_LVDS_AFE_SAR_CLK_FREQ_CFG_CLK_DIV_Pos 0UL 1793 #define LVDSSS_LVDS_AFE_SAR_CLK_FREQ_CFG_CLK_DIV_Msk 0x3UL 1794 /* LVDSSS_LVDS_AFE.STUCK_AT_CNTRS */ 1795 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR0_Pos 0UL 1796 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR0_Msk 0xFUL 1797 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR1_Pos 4UL 1798 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR1_Msk 0xF0UL 1799 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR2_Pos 8UL 1800 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR2_Msk 0xF00UL 1801 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR3_Pos 12UL 1802 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR3_Msk 0xF000UL 1803 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR4_Pos 16UL 1804 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR4_Msk 0xF0000UL 1805 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR5_Pos 20UL 1806 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR5_Msk 0xF00000UL 1807 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR6_Pos 24UL 1808 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR6_Msk 0xF000000UL 1809 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR7_Pos 28UL 1810 #define LVDSSS_LVDS_AFE_STUCK_AT_CNTRS_CNTR7_Msk 0xF0000000UL 1811 /* LVDSSS_LVDS_AFE.STUCK_CNTR_RST_CTL */ 1812 #define LVDSSS_LVDS_AFE_STUCK_CNTR_RST_CTL_CNTR_RST_Pos 0UL 1813 #define LVDSSS_LVDS_AFE_STUCK_CNTR_RST_CTL_CNTR_RST_Msk 0xFFUL 1814 /* LVDSSS_LVDS_AFE.STUCK_CNTR_SIG_SEL_0 */ 1815 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_0_Pos 0UL 1816 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_0_Msk 0xFFUL 1817 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_1_Pos 8UL 1818 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_1_Msk 0xFF00UL 1819 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_2_Pos 16UL 1820 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_2_Msk 0xFF0000UL 1821 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_3_Pos 24UL 1822 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_0_SIG_SEL_OF_CNTR_3_Msk 0xFF000000UL 1823 /* LVDSSS_LVDS_AFE.STUCK_CNTR_SIG_SEL_1 */ 1824 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_4_Pos 0UL 1825 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_4_Msk 0xFFUL 1826 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_5_Pos 8UL 1827 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_5_Msk 0xFF00UL 1828 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_6_Pos 16UL 1829 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_6_Msk 0xFF0000UL 1830 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_7_Pos 24UL 1831 #define LVDSSS_LVDS_AFE_STUCK_CNTR_SIG_SEL_1_SIG_SEL_OF_CNTR_7_Msk 0xFF000000UL 1832 /* LVDSSS_LVDS_AFE.CTL_PIN_SDLL_CFG */ 1833 #define LVDSSS_LVDS_AFE_CTL_PIN_SDLL_CFG_CTL_PIN_SEL_Pos 0UL 1834 #define LVDSSS_LVDS_AFE_CTL_PIN_SDLL_CFG_CTL_PIN_SEL_Msk 0xFUL 1835 #define LVDSSS_LVDS_AFE_CTL_PIN_SDLL_CFG_EN_SDLL_CLK_MON_Pos 4UL 1836 #define LVDSSS_LVDS_AFE_CTL_PIN_SDLL_CFG_EN_SDLL_CLK_MON_Msk 0x10UL 1837 /* LVDSSS_LVDS_AFE.LVDS_BER_STATUS */ 1838 #define LVDSSS_LVDS_AFE_LVDS_BER_STATUS_LVDS_DATA_BER_Pos 0UL 1839 #define LVDSSS_LVDS_AFE_LVDS_BER_STATUS_LVDS_DATA_BER_Msk 0xFFUL 1840 #define LVDSSS_LVDS_AFE_LVDS_BER_STATUS_LVDS_CTRL_BER_Pos 8UL 1841 #define LVDSSS_LVDS_AFE_LVDS_BER_STATUS_LVDS_CTRL_BER_Msk 0x100UL 1842 1843 1844 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.SCK_DSCR */ 1845 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_DSCR_NUMBER_Pos 0UL 1846 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_DSCR_NUMBER_Msk 0xFFFFUL 1847 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_DSCR_COUNT_Pos 16UL 1848 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_DSCR_COUNT_Msk 0xFF0000UL 1849 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_DSCR_LOW_Pos 24UL 1850 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_DSCR_LOW_Msk 0xFF000000UL 1851 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.SCK_SIZE */ 1852 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_SIZE_TRANS_SIZE_Pos 0UL 1853 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_SIZE_TRANS_SIZE_Msk 0xFFFFFFFFUL 1854 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.SCK_COUNT */ 1855 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_COUNT_TRANS_COUNT_Pos 0UL 1856 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_COUNT_TRANS_COUNT_Msk 0xFFFFFFFFUL 1857 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.SCK_STATUS */ 1858 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_AVL_COUNT_Pos 0UL 1859 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_AVL_COUNT_Msk 0x1FUL 1860 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_AVL_MIN_Pos 5UL 1861 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_AVL_MIN_Msk 0x3E0UL 1862 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_AVL_ENABLE_Pos 10UL 1863 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_AVL_ENABLE_Msk 0x400UL 1864 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SCK_ZLP_ALWAYS_Pos 11UL 1865 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SCK_ZLP_ALWAYS_Msk 0x800UL 1866 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_STATE_Pos 15UL 1867 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_STATE_Msk 0x38000UL 1868 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_ZLP_RCVD_Pos 18UL 1869 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_ZLP_RCVD_Msk 0x40000UL 1870 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSPENDED_Pos 19UL 1871 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSPENDED_Msk 0x80000UL 1872 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_ENABLED_Pos 20UL 1873 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_ENABLED_Msk 0x100000UL 1874 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_TRUNCATE_Pos 21UL 1875 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_TRUNCATE_Msk 0x200000UL 1876 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_EN_PROD_EVENTS_Pos 22UL 1877 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_EN_PROD_EVENTS_Msk 0x400000UL 1878 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_EN_CONS_EVENTS_Pos 23UL 1879 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_EN_CONS_EVENTS_Msk 0x800000UL 1880 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_PARTIAL_Pos 24UL 1881 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_PARTIAL_Msk 0x1000000UL 1882 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_LAST_Pos 25UL 1883 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_LAST_Msk 0x2000000UL 1884 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_TRANS_Pos 26UL 1885 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_TRANS_Msk 0x4000000UL 1886 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_EOP_Pos 27UL 1887 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_SUSP_EOP_Msk 0x8000000UL 1888 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_WRAPUP_Pos 28UL 1889 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_WRAPUP_Msk 0x10000000UL 1890 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_UNIT_Pos 29UL 1891 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_UNIT_Msk 0x20000000UL 1892 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_GO_SUSPEND_Pos 30UL 1893 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_GO_SUSPEND_Msk 0x40000000UL 1894 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_GO_ENABLE_Pos 31UL 1895 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_STATUS_GO_ENABLE_Msk 0x80000000UL 1896 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.SCK_INTR */ 1897 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_PRODUCE_EVENT_Pos 0UL 1898 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_PRODUCE_EVENT_Msk 0x1UL 1899 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_CONSUME_EVENT_Pos 1UL 1900 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_CONSUME_EVENT_Msk 0x2UL 1901 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_DSCR_IS_LOW_Pos 2UL 1902 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_DSCR_IS_LOW_Msk 0x4UL 1903 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_DSCR_NOT_AVL_Pos 3UL 1904 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_DSCR_NOT_AVL_Msk 0x8UL 1905 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_STALL_Pos 4UL 1906 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_STALL_Msk 0x10UL 1907 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_SUSPEND_Pos 5UL 1908 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_SUSPEND_Msk 0x20UL 1909 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_ERROR_Pos 6UL 1910 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_ERROR_Msk 0x40UL 1911 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_TRANS_DONE_Pos 7UL 1912 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_TRANS_DONE_Msk 0x80UL 1913 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_PARTIAL_BUF_Pos 8UL 1914 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_PARTIAL_BUF_Msk 0x100UL 1915 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_LAST_BUF_Pos 9UL 1916 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_LAST_BUF_Msk 0x200UL 1917 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_EVENT_RCVD_Pos 10UL 1918 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_EVENT_RCVD_Msk 0x400UL 1919 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.SCK_INTR_MASK */ 1920 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_PRODUCE_EVENT_Pos 0UL 1921 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_PRODUCE_EVENT_Msk 0x1UL 1922 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_CONSUME_EVENT_Pos 1UL 1923 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_CONSUME_EVENT_Msk 0x2UL 1924 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_DSCR_IS_LOW_Pos 2UL 1925 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_DSCR_IS_LOW_Msk 0x4UL 1926 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_DSCR_NOT_AVL_Pos 3UL 1927 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_DSCR_NOT_AVL_Msk 0x8UL 1928 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_STALL_Pos 4UL 1929 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_STALL_Msk 0x10UL 1930 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_SUSPEND_Pos 5UL 1931 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_SUSPEND_Msk 0x20UL 1932 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_ERROR_Pos 6UL 1933 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_ERROR_Msk 0x40UL 1934 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_TRANS_DONE_Pos 7UL 1935 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_TRANS_DONE_Msk 0x80UL 1936 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_PARTIAL_BUF_Pos 8UL 1937 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_PARTIAL_BUF_Msk 0x100UL 1938 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_LAST_BUF_Pos 9UL 1939 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_LAST_BUF_Msk 0x200UL 1940 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_EVENT_RCVD_Pos 10UL 1941 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_INTR_MASK_EVENT_RCVD_Msk 0x400UL 1942 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.DSCR_BUFFER */ 1943 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_BUFFER_BUFFER_ADDR_Pos 0UL 1944 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_BUFFER_BUFFER_ADDR_Msk 0x7FFFFFFFUL 1945 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_BUFFER_MARKER_Pos 31UL 1946 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_BUFFER_MARKER_Msk 0x80000000UL 1947 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.DSCR_SYNC */ 1948 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_SCK_Pos 0UL 1949 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_SCK_Msk 0xFFUL 1950 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_IP_Pos 8UL 1951 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_CONS_IP_Msk 0x3F00UL 1952 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_EVENT_Pos 14UL 1953 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_EVENT_Msk 0x4000UL 1954 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_INT_Pos 15UL 1955 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_CONS_INT_Msk 0x8000UL 1956 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_SCK_Pos 16UL 1957 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_SCK_Msk 0xFF0000UL 1958 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_IP_Pos 24UL 1959 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_PROD_IP_Msk 0x3F000000UL 1960 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_EVENT_Pos 30UL 1961 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_EVENT_Msk 0x40000000UL 1962 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_INT_Pos 31UL 1963 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SYNC_EN_PROD_INT_Msk 0x80000000UL 1964 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.DSCR_CHAIN */ 1965 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_CHAIN_RD_NEXT_DSCR_Pos 0UL 1966 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_CHAIN_RD_NEXT_DSCR_Msk 0xFFFFUL 1967 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_CHAIN_WR_NEXT_DSCR_Pos 16UL 1968 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_CHAIN_WR_NEXT_DSCR_Msk 0xFFFF0000UL 1969 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.DSCR_SIZE */ 1970 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_MSB_Pos 0UL 1971 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_MSB_Msk 0x1UL 1972 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_EOP_Pos 1UL 1973 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_EOP_Msk 0x2UL 1974 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_ERROR_Pos 2UL 1975 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_ERROR_Msk 0x4UL 1976 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_OCCUPIED_Pos 3UL 1977 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_OCCUPIED_Msk 0x8UL 1978 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_SIZE_Pos 4UL 1979 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BUFFER_SIZE_Msk 0xFFF0UL 1980 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_Pos 16UL 1981 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_DSCR_SIZE_BYTE_COUNT_Msk 0xFFFF0000UL 1982 /* LVDSSS_LVDS_ADAPTER_DMA_SCK.EVENT */ 1983 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_EVENT_ACTIVE_DSCR_Pos 0UL 1984 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_EVENT_ACTIVE_DSCR_Msk 0xFFFFUL 1985 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_EVENT_EVENT_TYPE_Pos 16UL 1986 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_EVENT_EVENT_TYPE_Msk 0x10000UL 1987 1988 1989 /* LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL.SCK_INTR */ 1990 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_SCK_INTR_SCKINTR_Pos 0UL 1991 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_SCK_INTR_SCKINTR_Msk 0xFFFFFFFFUL 1992 /* LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL.ADAPTER_CTRL */ 1993 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAPTER_EN_Pos 0UL 1994 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAPTER_EN_Msk 0x1UL 1995 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_WR_PRIO_Pos 4UL 1996 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_WR_PRIO_Msk 0x10UL 1997 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_RD_PRIO_Pos 5UL 1998 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DATA_RD_PRIO_Msk 0x20UL 1999 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_WR_PRIO_N_Pos 6UL 2000 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_WR_PRIO_N_Msk 0x40UL 2001 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_RD_PRIO_N_Pos 7UL 2002 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_ADAP_DESC_RD_PRIO_N_Msk 0x80UL 2003 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_SUSP_PARTIAL_NO_EVT_N_Pos 10UL 2004 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_SUSP_PARTIAL_NO_EVT_N_Msk 0x400UL 2005 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_FQ_DEPTH_CTRL_Pos 12UL 2006 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_FQ_DEPTH_CTRL_Msk 0x3F000UL 2007 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_DEBUG_CAPTURE_Pos 20UL 2008 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_DEBUG_CAPTURE_Msk 0x100000UL 2009 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_EN_UNALIGNED_READ_N_Pos 21UL 2010 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_EN_UNALIGNED_READ_N_Msk 0x200000UL 2011 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_TR_OUT_DELAY_Pos 24UL 2012 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CTRL_TR_OUT_DELAY_Msk 0x3F000000UL 2013 /* LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL.ADAPTER_DEBUG */ 2014 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_COUNT_Pos 0UL 2015 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_COUNT_Msk 0xFUL 2016 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_STATE_Pos 4UL 2017 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_STATE_Msk 0x70UL 2018 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ID_Pos 7UL 2019 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ID_Msk 0x1F80UL 2020 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_COUNT_Pos 13UL 2021 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_COUNT_Msk 0x3FE000UL 2022 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_STATE_Pos 22UL 2023 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_STATE_Msk 0x400000UL 2024 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_ID_Pos 23UL 2025 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_SS_ID_Msk 0x1F800000UL 2026 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ABORT_Pos 29UL 2027 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_TS_ABORT_Msk 0x20000000UL 2028 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_BS_STATE_Pos 30UL 2029 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_DEBUG_BS_STATE_Msk 0xC0000000UL 2030 /* LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL.ADAPTER_CONF */ 2031 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SOCKET_ACTIVE_THRSHLD_Pos 0UL 2032 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SOCKET_ACTIVE_THRSHLD_Msk 0x3FUL 2033 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAM_COUNT_Pos 6UL 2034 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAM_COUNT_Msk 0x7FC0UL 2035 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAMING_MODE_Pos 15UL 2036 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_STREAMING_MODE_Msk 0x8000UL 2037 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_CYCLES_Pos 16UL 2038 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_CYCLES_Msk 0xF0000UL 2039 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_ES_CYCLES_Pos 20UL 2040 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_ES_CYCLES_Msk 0xF00000UL 2041 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_GBL_CYCLES_Pos 24UL 2042 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_GBL_CYCLES_Msk 0xF000000UL 2043 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_MMIO_LOW_PRIORITY_Pos 28UL 2044 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_MMIO_LOW_PRIORITY_Msk 0x10000000UL 2045 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SWITCH_HIGH_PRIORITY_Pos 29UL 2046 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_SWITCH_HIGH_PRIORITY_Msk 0x20000000UL 2047 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_ABORT_EN_Pos 30UL 2048 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_TS_ABORT_EN_Msk 0x40000000UL 2049 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_DESCR_PF_EN_N_Pos 31UL 2050 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_CONF_DESCR_PF_EN_N_Msk 0x80000000UL 2051 /* LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL.ADAPTER_STATUS */ 2052 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_TTL_SOCKETS_Pos 0UL 2053 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_TTL_SOCKETS_Msk 0xFFUL 2054 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_IG_ONLY_Pos 8UL 2055 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_IG_ONLY_Msk 0xFF00UL 2056 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_FQ_SIZE_Pos 16UL 2057 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_FQ_SIZE_Msk 0x1FF0000UL 2058 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_WORD_SIZE_Pos 25UL 2059 #define LVDSSS_LVDS_ADAPTER_DMA_SCK_GBL_ADAPTER_STATUS_WORD_SIZE_Msk 0x6000000UL 2060 2061 2062 /* LVDSSS_LVDS.CTL */ 2063 #define LVDSSS_LVDS_CTL_PHY_ENABLED_Pos 0UL 2064 #define LVDSSS_LVDS_CTL_PHY_ENABLED_Msk 0x1UL 2065 #define LVDSSS_LVDS_CTL_LINK_ENABLED_Pos 1UL 2066 #define LVDSSS_LVDS_CTL_LINK_ENABLED_Msk 0x2UL 2067 #define LVDSSS_LVDS_CTL_DMA_ENABLED_Pos 2UL 2068 #define LVDSSS_LVDS_CTL_DMA_ENABLED_Msk 0x4UL 2069 #define LVDSSS_LVDS_CTL_IP_ENABLED_Pos 31UL 2070 #define LVDSSS_LVDS_CTL_IP_ENABLED_Msk 0x80000000UL 2071 /* LVDSSS_LVDS.LINK_CONFIG */ 2072 #define LVDSSS_LVDS_LINK_CONFIG_LVDS_MODE_Pos 0UL 2073 #define LVDSSS_LVDS_LINK_CONFIG_LVDS_MODE_Msk 0x1UL 2074 #define LVDSSS_LVDS_LINK_CONFIG_GEARING_RATIO_Pos 1UL 2075 #define LVDSSS_LVDS_LINK_CONFIG_GEARING_RATIO_Msk 0x6UL 2076 #define LVDSSS_LVDS_LINK_CONFIG_WIDE_LINK_Pos 3UL 2077 #define LVDSSS_LVDS_LINK_CONFIG_WIDE_LINK_Msk 0x8UL 2078 #define LVDSSS_LVDS_LINK_CONFIG_NUM_LANES_Pos 4UL 2079 #define LVDSSS_LVDS_LINK_CONFIG_NUM_LANES_Msk 0xF0UL 2080 #define LVDSSS_LVDS_LINK_CONFIG_TWO_BIT_SLV_FF_Pos 8UL 2081 #define LVDSSS_LVDS_LINK_CONFIG_TWO_BIT_SLV_FF_Msk 0x100UL 2082 #define LVDSSS_LVDS_LINK_CONFIG_LINK_ENABLE_Pos 15UL 2083 #define LVDSSS_LVDS_LINK_CONFIG_LINK_ENABLE_Msk 0x8000UL 2084 #define LVDSSS_LVDS_LINK_CONFIG_BYPASS_DDR_PHY_Pos 16UL 2085 #define LVDSSS_LVDS_LINK_CONFIG_BYPASS_DDR_PHY_Msk 0x10000UL 2086 /* LVDSSS_LVDS.THREAD_INTLV_CTL */ 2087 #define LVDSSS_LVDS_THREAD_INTLV_CTL_TH0_TH1_INTERLEAVED_Pos 0UL 2088 #define LVDSSS_LVDS_THREAD_INTLV_CTL_TH0_TH1_INTERLEAVED_Msk 0x1UL 2089 #define LVDSSS_LVDS_THREAD_INTLV_CTL_TH2_TH3_INTERLEAVED_Pos 1UL 2090 #define LVDSSS_LVDS_THREAD_INTLV_CTL_TH2_TH3_INTERLEAVED_Msk 0x2UL 2091 /* LVDSSS_LVDS.LVDS_INTR_WD0 */ 2092 #define LVDSSS_LVDS_LVDS_INTR_WD0_GPIF0_INTERRUPT_Pos 0UL 2093 #define LVDSSS_LVDS_LVDS_INTR_WD0_GPIF0_INTERRUPT_Msk 0x1UL 2094 #define LVDSSS_LVDS_LVDS_INTR_WD0_GPIF1_INTERRUPT_Pos 1UL 2095 #define LVDSSS_LVDS_LVDS_INTR_WD0_GPIF1_INTERRUPT_Msk 0x2UL 2096 #define LVDSSS_LVDS_LVDS_INTR_WD0_PHY_LINK0_INTERRUPT_Pos 2UL 2097 #define LVDSSS_LVDS_LVDS_INTR_WD0_PHY_LINK0_INTERRUPT_Msk 0x4UL 2098 #define LVDSSS_LVDS_LVDS_INTR_WD0_PHY_LINK1_INTERRUPT_Pos 3UL 2099 #define LVDSSS_LVDS_LVDS_INTR_WD0_PHY_LINK1_INTERRUPT_Msk 0x8UL 2100 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD0_ERR_Pos 4UL 2101 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD0_ERR_Msk 0x10UL 2102 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD1_ERR_Pos 5UL 2103 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD1_ERR_Msk 0x20UL 2104 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD2_ERR_Pos 6UL 2105 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD2_ERR_Msk 0x40UL 2106 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD3_ERR_Pos 7UL 2107 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD3_ERR_Msk 0x80UL 2108 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_FF_OVER_FLOW_Pos 8UL 2109 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_FF_OVER_FLOW_Msk 0x100UL 2110 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_FF_OVER_FLOW_Pos 9UL 2111 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_FF_OVER_FLOW_Msk 0x200UL 2112 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_TRAINING_DONE_Pos 10UL 2113 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_TRAINING_DONE_Msk 0x400UL 2114 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_TRAINING_DONE_Pos 11UL 2115 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_TRAINING_DONE_Msk 0x800UL 2116 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_TRAINING_BLK_DETECTED_Pos 12UL 2117 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_TRAINING_BLK_DETECTED_Msk 0x1000UL 2118 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_TRAINING_BLK_DETECTED_Pos 13UL 2119 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_TRAINING_BLK_DETECTED_Msk 0x2000UL 2120 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_TRAINING_BLK_DET_FAILD_Pos 14UL 2121 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_TRAINING_BLK_DET_FAILD_Msk 0x4000UL 2122 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_TRAINING_BLK_DET_FAILD_Pos 15UL 2123 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_TRAINING_BLK_DET_FAILD_Msk 0x8000UL 2124 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD0_DATA_CRC_ERR_Pos 16UL 2125 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD0_DATA_CRC_ERR_Msk 0x10000UL 2126 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD1_DATA_CRC_ERR_Pos 17UL 2127 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD1_DATA_CRC_ERR_Msk 0x20000UL 2128 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD2_DATA_CRC_ERR_Pos 18UL 2129 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD2_DATA_CRC_ERR_Msk 0x40000UL 2130 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD3_DATA_CRC_ERR_Pos 19UL 2131 #define LVDSSS_LVDS_LVDS_INTR_WD0_THREAD3_DATA_CRC_ERR_Msk 0x80000UL 2132 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_L1_ENTRY_Pos 26UL 2133 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_L1_ENTRY_Msk 0x4000000UL 2134 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_L1_ENTRY_Pos 27UL 2135 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_L1_ENTRY_Msk 0x8000000UL 2136 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_L1_EXIT_Pos 28UL 2137 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_L1_EXIT_Msk 0x10000000UL 2138 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_L1_EXIT_Pos 29UL 2139 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_L1_EXIT_Msk 0x20000000UL 2140 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_L3_ENTRY_Pos 30UL 2141 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK0_L3_ENTRY_Msk 0x40000000UL 2142 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_L3_ENTRY_Pos 31UL 2143 #define LVDSSS_LVDS_LVDS_INTR_WD0_LNK1_L3_ENTRY_Msk 0x80000000UL 2144 /* LVDSSS_LVDS.LVDS_INTR_WD1 */ 2145 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT0_Pos 0UL 2146 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT0_Msk 0x1UL 2147 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT1_Pos 1UL 2148 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT1_Msk 0x2UL 2149 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT2_Pos 2UL 2150 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT2_Msk 0x4UL 2151 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT3_Pos 3UL 2152 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_CLR_BIT3_Msk 0x8UL 2153 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT0_Pos 4UL 2154 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT0_Msk 0x10UL 2155 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT1_Pos 5UL 2156 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT1_Msk 0x20UL 2157 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT2_Pos 6UL 2158 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT2_Msk 0x40UL 2159 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT3_Pos 7UL 2160 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_CLR_BIT3_Msk 0x80UL 2161 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT0_Pos 8UL 2162 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT0_Msk 0x100UL 2163 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT1_Pos 9UL 2164 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT1_Msk 0x200UL 2165 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT2_Pos 10UL 2166 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT2_Msk 0x400UL 2167 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT3_Pos 11UL 2168 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_CLR_BIT3_Msk 0x800UL 2169 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT0_Pos 12UL 2170 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT0_Msk 0x1000UL 2171 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT1_Pos 13UL 2172 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT1_Msk 0x2000UL 2173 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT2_Pos 14UL 2174 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT2_Msk 0x4000UL 2175 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT3_Pos 15UL 2176 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_CLR_BIT3_Msk 0x8000UL 2177 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT0_Pos 16UL 2178 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT0_Msk 0x10000UL 2179 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT1_Pos 17UL 2180 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT1_Msk 0x20000UL 2181 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT2_Pos 18UL 2182 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT2_Msk 0x40000UL 2183 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT3_Pos 19UL 2184 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH0_HDR_FLGS_SET_BIT3_Msk 0x80000UL 2185 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT0_Pos 20UL 2186 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT0_Msk 0x100000UL 2187 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT1_Pos 21UL 2188 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT1_Msk 0x200000UL 2189 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT2_Pos 22UL 2190 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT2_Msk 0x400000UL 2191 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT3_Pos 23UL 2192 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH1_HDR_FLGS_SET_BIT3_Msk 0x800000UL 2193 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT0_Pos 24UL 2194 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT0_Msk 0x1000000UL 2195 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT1_Pos 25UL 2196 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT1_Msk 0x2000000UL 2197 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT2_Pos 26UL 2198 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT2_Msk 0x4000000UL 2199 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT3_Pos 27UL 2200 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH2_HDR_FLGS_SET_BIT3_Msk 0x8000000UL 2201 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT0_Pos 28UL 2202 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT0_Msk 0x10000000UL 2203 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT1_Pos 29UL 2204 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT1_Msk 0x20000000UL 2205 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT2_Pos 30UL 2206 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT2_Msk 0x40000000UL 2207 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT3_Pos 31UL 2208 #define LVDSSS_LVDS_LVDS_INTR_WD1_TH3_HDR_FLGS_SET_BIT3_Msk 0x80000000UL 2209 /* LVDSSS_LVDS.LVDS_INTR_MASK_WD0 */ 2210 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_GPIF0_INTERRUPT_Pos 0UL 2211 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_GPIF0_INTERRUPT_Msk 0x1UL 2212 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_GPIF1_INTERRUPT_Pos 1UL 2213 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_GPIF1_INTERRUPT_Msk 0x2UL 2214 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_PHY_LINK0_INTERRUPT_Pos 2UL 2215 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_PHY_LINK0_INTERRUPT_Msk 0x4UL 2216 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_PHY_LINK1_INTERRUPT_Pos 3UL 2217 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_PHY_LINK1_INTERRUPT_Msk 0x8UL 2218 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD0_ERR_Pos 4UL 2219 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD0_ERR_Msk 0x10UL 2220 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD1_ERR_Pos 5UL 2221 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD1_ERR_Msk 0x20UL 2222 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD2_ERR_Pos 6UL 2223 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD2_ERR_Msk 0x40UL 2224 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD3_ERR_Pos 7UL 2225 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD3_ERR_Msk 0x80UL 2226 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_FF_OVER_FLOW_Pos 8UL 2227 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_FF_OVER_FLOW_Msk 0x100UL 2228 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_FF_OVER_FLOW_Pos 9UL 2229 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_FF_OVER_FLOW_Msk 0x200UL 2230 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_TRAINING_DONE_Pos 10UL 2231 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_TRAINING_DONE_Msk 0x400UL 2232 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_TRAINING_DONE_Pos 11UL 2233 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_TRAINING_DONE_Msk 0x800UL 2234 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_TRAINING_BLK_DETECTED_Pos 12UL 2235 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_TRAINING_BLK_DETECTED_Msk 0x1000UL 2236 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_TRAINING_BLK_DETECTED_Pos 13UL 2237 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_TRAINING_BLK_DETECTED_Msk 0x2000UL 2238 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_TRAINING_BLK_DET_FAILD_Pos 14UL 2239 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_TRAINING_BLK_DET_FAILD_Msk 0x4000UL 2240 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_TRAINING_BLK_DET_FAILD_Pos 15UL 2241 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_TRAINING_BLK_DET_FAILD_Msk 0x8000UL 2242 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD0_DATA_CRC_ERR_Pos 16UL 2243 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD0_DATA_CRC_ERR_Msk 0x10000UL 2244 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD1_DATA_CRC_ERR_Pos 17UL 2245 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD1_DATA_CRC_ERR_Msk 0x20000UL 2246 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD2_DATA_CRC_ERR_Pos 18UL 2247 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD2_DATA_CRC_ERR_Msk 0x40000UL 2248 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD3_DATA_CRC_ERR_Pos 19UL 2249 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_THREAD3_DATA_CRC_ERR_Msk 0x80000UL 2250 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_L1_ENTRY_Pos 26UL 2251 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_L1_ENTRY_Msk 0x4000000UL 2252 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_L1_ENTRY_Pos 27UL 2253 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_L1_ENTRY_Msk 0x8000000UL 2254 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_L1_EXIT_Pos 28UL 2255 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_L1_EXIT_Msk 0x10000000UL 2256 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_L1_EXIT_Pos 29UL 2257 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_L1_EXIT_Msk 0x20000000UL 2258 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_L3_ENTRY_Pos 30UL 2259 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK0_L3_ENTRY_Msk 0x40000000UL 2260 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_L3_ENTRY_Pos 31UL 2261 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD0_LNK1_L3_ENTRY_Msk 0x80000000UL 2262 /* LVDSSS_LVDS.LVDS_INTR_MASK_WD1 */ 2263 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH0_HDR_FLGS_CLR_Pos 0UL 2264 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH0_HDR_FLGS_CLR_Msk 0xFUL 2265 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH1_HDR_FLGS_CLR_Pos 4UL 2266 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH1_HDR_FLGS_CLR_Msk 0xF0UL 2267 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH2_HDR_FLGS_CLR_Pos 8UL 2268 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH2_HDR_FLGS_CLR_Msk 0xF00UL 2269 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH3_HDR_FLGS_CLR_Pos 12UL 2270 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH3_HDR_FLGS_CLR_Msk 0xF000UL 2271 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH0_HDR_FLGS_SET_Pos 16UL 2272 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH0_HDR_FLGS_SET_Msk 0xF0000UL 2273 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH1_HDR_FLGS_SET_Pos 20UL 2274 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH1_HDR_FLGS_SET_Msk 0xF00000UL 2275 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH2_HDR_FLGS_SET_Pos 24UL 2276 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH2_HDR_FLGS_SET_Msk 0xF000000UL 2277 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH3_HDR_FLGS_SET_Pos 28UL 2278 #define LVDSSS_LVDS_LVDS_INTR_MASK_WD1_TH3_HDR_FLGS_SET_Msk 0xF0000000UL 2279 /* LVDSSS_LVDS.LVDS_INTR_MASKED_WD0 */ 2280 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_GPIF0_INTERRUPT_Pos 0UL 2281 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_GPIF0_INTERRUPT_Msk 0x1UL 2282 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_GPIF1_INTERRUPT_Pos 1UL 2283 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_GPIF1_INTERRUPT_Msk 0x2UL 2284 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_PHY_LINK0_INTERRUPT_Pos 2UL 2285 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_PHY_LINK0_INTERRUPT_Msk 0x4UL 2286 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_PHY_LINK1_INTERRUPT_Pos 3UL 2287 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_PHY_LINK1_INTERRUPT_Msk 0x8UL 2288 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD0_ERR_Pos 4UL 2289 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD0_ERR_Msk 0x10UL 2290 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD1_ERR_Pos 5UL 2291 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD1_ERR_Msk 0x20UL 2292 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD2_ERR_Pos 6UL 2293 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD2_ERR_Msk 0x40UL 2294 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD3_ERR_Pos 7UL 2295 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD3_ERR_Msk 0x80UL 2296 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_FF_OVER_FLOW_Pos 8UL 2297 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_FF_OVER_FLOW_Msk 0x100UL 2298 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_FF_OVER_FLOW_Pos 9UL 2299 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_FF_OVER_FLOW_Msk 0x200UL 2300 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_TRAINING_DONE_Pos 10UL 2301 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_TRAINING_DONE_Msk 0x400UL 2302 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_TRAINING_DONE_Pos 11UL 2303 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_TRAINING_DONE_Msk 0x800UL 2304 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_TRAINING_BLK_DETECTED_Pos 12UL 2305 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_TRAINING_BLK_DETECTED_Msk 0x1000UL 2306 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_TRAINING_BLK_DETECTED_Pos 13UL 2307 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_TRAINING_BLK_DETECTED_Msk 0x2000UL 2308 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_TRAINING_BLK_DET_FAILD_Pos 14UL 2309 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_TRAINING_BLK_DET_FAILD_Msk 0x4000UL 2310 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_TRAINING_BLK_DET_FAILD_Pos 15UL 2311 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_TRAINING_BLK_DET_FAILD_Msk 0x8000UL 2312 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD0_DATA_CRC_ERR_Pos 16UL 2313 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD0_DATA_CRC_ERR_Msk 0x10000UL 2314 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD1_DATA_CRC_ERR_Pos 17UL 2315 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD1_DATA_CRC_ERR_Msk 0x20000UL 2316 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD2_DATA_CRC_ERR_Pos 18UL 2317 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD2_DATA_CRC_ERR_Msk 0x40000UL 2318 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD3_DATA_CRC_ERR_Pos 19UL 2319 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_THREAD3_DATA_CRC_ERR_Msk 0x80000UL 2320 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_L1_ENTRY_Pos 26UL 2321 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_L1_ENTRY_Msk 0x4000000UL 2322 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_L1_ENTRY_Pos 27UL 2323 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_L1_ENTRY_Msk 0x8000000UL 2324 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_L1_EXIT_Pos 28UL 2325 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_L1_EXIT_Msk 0x10000000UL 2326 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_L1_EXIT_Pos 29UL 2327 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_L1_EXIT_Msk 0x20000000UL 2328 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_L3_ENTRY_Pos 30UL 2329 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK0_L3_ENTRY_Msk 0x40000000UL 2330 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_L3_ENTRY_Pos 31UL 2331 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD0_LNK1_L3_ENTRY_Msk 0x80000000UL 2332 /* LVDSSS_LVDS.LVDS_INTR_MASKED_WD1 */ 2333 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH0_HDR_FLGS_CLR_Pos 0UL 2334 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH0_HDR_FLGS_CLR_Msk 0xFUL 2335 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH1_HDR_FLGS_CLR_Pos 4UL 2336 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH1_HDR_FLGS_CLR_Msk 0xF0UL 2337 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH2_HDR_FLGS_CLR_Pos 8UL 2338 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH2_HDR_FLGS_CLR_Msk 0xF00UL 2339 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH3_HDR_FLGS_CLR_Pos 12UL 2340 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH3_HDR_FLGS_CLR_Msk 0xF000UL 2341 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH0_HDR_FLGS_SET_Pos 16UL 2342 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH0_HDR_FLGS_SET_Msk 0xF0000UL 2343 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH1_HDR_FLGS_SET_Pos 20UL 2344 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH1_HDR_FLGS_SET_Msk 0xF00000UL 2345 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH2_HDR_FLGS_SET_Pos 24UL 2346 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH2_HDR_FLGS_SET_Msk 0xF000000UL 2347 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH3_HDR_FLGS_SET_Pos 28UL 2348 #define LVDSSS_LVDS_LVDS_INTR_MASKED_WD1_TH3_HDR_FLGS_SET_Msk 0xF0000000UL 2349 /* LVDSSS_LVDS.LVDS_INTR_SET_WD0 */ 2350 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD0_ERR_Pos 4UL 2351 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD0_ERR_Msk 0x10UL 2352 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD1_ERR_Pos 5UL 2353 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD1_ERR_Msk 0x20UL 2354 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD2_ERR_Pos 6UL 2355 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD2_ERR_Msk 0x40UL 2356 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD3_ERR_Pos 7UL 2357 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD3_ERR_Msk 0x80UL 2358 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_FF_OVER_FLOW_Pos 8UL 2359 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_FF_OVER_FLOW_Msk 0x100UL 2360 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_FF_OVER_FLOW_Pos 9UL 2361 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_FF_OVER_FLOW_Msk 0x200UL 2362 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_TRAINING_DONE_Pos 10UL 2363 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_TRAINING_DONE_Msk 0x400UL 2364 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_TRAINING_DONE_Pos 11UL 2365 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_TRAINING_DONE_Msk 0x800UL 2366 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_TRAINING_BLK_DETECTED_Pos 12UL 2367 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_TRAINING_BLK_DETECTED_Msk 0x1000UL 2368 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_TRAINING_BLK_DETECTED_Pos 13UL 2369 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_TRAINING_BLK_DETECTED_Msk 0x2000UL 2370 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_TRAINING_BLK_DET_FAILD_Pos 14UL 2371 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_TRAINING_BLK_DET_FAILD_Msk 0x4000UL 2372 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_TRAINING_BLK_DET_FAILD_Pos 15UL 2373 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_TRAINING_BLK_DET_FAILD_Msk 0x8000UL 2374 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD0_DATA_CRC_ERR_Pos 16UL 2375 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD0_DATA_CRC_ERR_Msk 0x10000UL 2376 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD1_DATA_CRC_ERR_Pos 17UL 2377 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD1_DATA_CRC_ERR_Msk 0x20000UL 2378 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD2_DATA_CRC_ERR_Pos 18UL 2379 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD2_DATA_CRC_ERR_Msk 0x40000UL 2380 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD3_DATA_CRC_ERR_Pos 19UL 2381 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_THREAD3_DATA_CRC_ERR_Msk 0x80000UL 2382 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_L1_ENTRY_Pos 26UL 2383 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_L1_ENTRY_Msk 0x4000000UL 2384 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_L1_ENTRY_Pos 27UL 2385 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_L1_ENTRY_Msk 0x8000000UL 2386 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_L1_EXIT_Pos 28UL 2387 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_L1_EXIT_Msk 0x10000000UL 2388 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_L1_EXIT_Pos 29UL 2389 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_L1_EXIT_Msk 0x20000000UL 2390 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_L3_ENTRY_Pos 30UL 2391 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK0_L3_ENTRY_Msk 0x40000000UL 2392 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_L3_ENTRY_Pos 31UL 2393 #define LVDSSS_LVDS_LVDS_INTR_SET_WD0_LNK1_L3_ENTRY_Msk 0x80000000UL 2394 /* LVDSSS_LVDS.LVDS_INTR_SET_WD1 */ 2395 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH0_HDR_FLGS_CLR_Pos 0UL 2396 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH0_HDR_FLGS_CLR_Msk 0xFUL 2397 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH1_HDR_FLGS_CLR_Pos 4UL 2398 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH1_HDR_FLGS_CLR_Msk 0xF0UL 2399 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH2_HDR_FLGS_CLR_Pos 8UL 2400 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH2_HDR_FLGS_CLR_Msk 0xF00UL 2401 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH3_HDR_FLGS_CLR_Pos 12UL 2402 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH3_HDR_FLGS_CLR_Msk 0xF000UL 2403 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH0_HDR_FLGS_SET_Pos 16UL 2404 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH0_HDR_FLGS_SET_Msk 0xF0000UL 2405 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH1_HDR_FLGS_SET_Pos 20UL 2406 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH1_HDR_FLGS_SET_Msk 0xF00000UL 2407 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH2_HDR_FLGS_SET_Pos 24UL 2408 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH2_HDR_FLGS_SET_Msk 0xF000000UL 2409 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH3_HDR_FLGS_SET_Pos 28UL 2410 #define LVDSSS_LVDS_LVDS_INTR_SET_WD1_TH3_HDR_FLGS_SET_Msk 0xF0000000UL 2411 /* LVDSSS_LVDS.LVDS_ERROR */ 2412 #define LVDSSS_LVDS_LVDS_ERROR_THREAD0_ERR_CODE_Pos 0UL 2413 #define LVDSSS_LVDS_LVDS_ERROR_THREAD0_ERR_CODE_Msk 0xFUL 2414 #define LVDSSS_LVDS_LVDS_ERROR_THREAD1_ERR_CODE_Pos 4UL 2415 #define LVDSSS_LVDS_LVDS_ERROR_THREAD1_ERR_CODE_Msk 0xF0UL 2416 #define LVDSSS_LVDS_LVDS_ERROR_THREAD2_ERR_CODE_Pos 8UL 2417 #define LVDSSS_LVDS_LVDS_ERROR_THREAD2_ERR_CODE_Msk 0xF00UL 2418 #define LVDSSS_LVDS_LVDS_ERROR_THREAD3_ERR_CODE_Pos 12UL 2419 #define LVDSSS_LVDS_LVDS_ERROR_THREAD3_ERR_CODE_Msk 0xF000UL 2420 /* LVDSSS_LVDS.LVDS_EOP_EOT */ 2421 #define LVDSSS_LVDS_LVDS_EOP_EOT_EOP_EOT_CFG_Pos 0UL 2422 #define LVDSSS_LVDS_LVDS_EOP_EOT_EOP_EOT_CFG_Msk 0xFFFFFFFFUL 2423 /* LVDSSS_LVDS.LANE_FIFO_STS */ 2424 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE0_FF_OVERFLOW_Pos 0UL 2425 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE0_FF_OVERFLOW_Msk 0x1UL 2426 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE1_FF_OVERFLOW_Pos 1UL 2427 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE1_FF_OVERFLOW_Msk 0x2UL 2428 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE2_FF_OVERFLOW_Pos 2UL 2429 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE2_FF_OVERFLOW_Msk 0x4UL 2430 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE3_FF_OVERFLOW_Pos 3UL 2431 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE3_FF_OVERFLOW_Msk 0x8UL 2432 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE4_FF_OVERFLOW_Pos 4UL 2433 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE4_FF_OVERFLOW_Msk 0x10UL 2434 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE5_FF_OVERFLOW_Pos 5UL 2435 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE5_FF_OVERFLOW_Msk 0x20UL 2436 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE6_FF_OVERFLOW_Pos 6UL 2437 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE6_FF_OVERFLOW_Msk 0x40UL 2438 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE7_FF_OVERFLOW_Pos 7UL 2439 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE7_FF_OVERFLOW_Msk 0x80UL 2440 #define LVDSSS_LVDS_LANE_FIFO_STS_CTRL_LANE_FF_OVERFLOW_Pos 8UL 2441 #define LVDSSS_LVDS_LANE_FIFO_STS_CTRL_LANE_FF_OVERFLOW_Msk 0x100UL 2442 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE0_FF_UNDERFLOW_Pos 16UL 2443 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE0_FF_UNDERFLOW_Msk 0x10000UL 2444 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE1_FF_UNDERFLOW_Pos 17UL 2445 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE1_FF_UNDERFLOW_Msk 0x20000UL 2446 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE2_FF_UNDERFLOW_Pos 18UL 2447 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE2_FF_UNDERFLOW_Msk 0x40000UL 2448 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE3_FF_UNDERFLOW_Pos 19UL 2449 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE3_FF_UNDERFLOW_Msk 0x80000UL 2450 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE4_FF_UNDERFLOW_Pos 20UL 2451 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE4_FF_UNDERFLOW_Msk 0x100000UL 2452 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE5_FF_UNDERFLOW_Pos 21UL 2453 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE5_FF_UNDERFLOW_Msk 0x200000UL 2454 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE6_FF_UNDERFLOW_Pos 22UL 2455 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE6_FF_UNDERFLOW_Msk 0x400000UL 2456 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE7_FF_UNDERFLOW_Pos 23UL 2457 #define LVDSSS_LVDS_LANE_FIFO_STS_LANE7_FF_UNDERFLOW_Msk 0x800000UL 2458 #define LVDSSS_LVDS_LANE_FIFO_STS_CTRL_LANE_FF_UNDERFLOW_Pos 24UL 2459 #define LVDSSS_LVDS_LANE_FIFO_STS_CTRL_LANE_FF_UNDERFLOW_Msk 0x1000000UL 2460 #define LVDSSS_LVDS_LANE_FIFO_STS_LNK_FF_UNDERFLOW_Pos 31UL 2461 #define LVDSSS_LVDS_LANE_FIFO_STS_LNK_FF_UNDERFLOW_Msk 0x80000000UL 2462 /* LVDSSS_LVDS.GPIF_CLK_SEL */ 2463 #define LVDSSS_LVDS_GPIF_CLK_SEL_GPIF_CLK_SRC_Pos 0UL 2464 #define LVDSSS_LVDS_GPIF_CLK_SEL_GPIF_CLK_SRC_Msk 0x3UL 2465 #define LVDSSS_LVDS_GPIF_CLK_SEL_USB_CLK_DIV_VAL_Pos 2UL 2466 #define LVDSSS_LVDS_GPIF_CLK_SEL_USB_CLK_DIV_VAL_Msk 0xCUL 2467 #define LVDSSS_LVDS_GPIF_CLK_SEL_GATE_WAVEFORM_MEM_CLK_Pos 4UL 2468 #define LVDSSS_LVDS_GPIF_CLK_SEL_GATE_WAVEFORM_MEM_CLK_Msk 0x10UL 2469 #define LVDSSS_LVDS_GPIF_CLK_SEL_LVCMOS_IF_CLK_100MHZ_Pos 5UL 2470 #define LVDSSS_LVDS_GPIF_CLK_SEL_LVCMOS_IF_CLK_100MHZ_Msk 0x20UL 2471 #define LVDSSS_LVDS_GPIF_CLK_SEL_WAVEFORM_RAM_CG_DURATION_Pos 8UL 2472 #define LVDSSS_LVDS_GPIF_CLK_SEL_WAVEFORM_RAM_CG_DURATION_Msk 0xF00UL 2473 /* LVDSSS_LVDS.USB_FRM_CNTR_CFG */ 2474 #define LVDSSS_LVDS_USB_FRM_CNTR_CFG_SEL_USB32_FRM_CNT_Pos 0UL 2475 #define LVDSSS_LVDS_USB_FRM_CNTR_CFG_SEL_USB32_FRM_CNT_Msk 0x1UL 2476 /* LVDSSS_LVDS.TIME_STAMP_CLK_DW0 */ 2477 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW0_TS_WD0_Pos 0UL 2478 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW0_TS_WD0_Msk 0xFFFFUL 2479 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW0_TS_WD1_Pos 16UL 2480 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW0_TS_WD1_Msk 0xFFFF0000UL 2481 /* LVDSSS_LVDS.TIME_STAMP_CLK_DW1 */ 2482 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW1_TS_WD2_Pos 0UL 2483 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW1_TS_WD2_Msk 0xFFFFUL 2484 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW1_TS_WD3_Pos 16UL 2485 #define LVDSSS_LVDS_TIME_STAMP_CLK_DW1_TS_WD3_Msk 0xFFFF0000UL 2486 /* LVDSSS_LVDS.SCRSS_VALUE_CFG */ 2487 #define LVDSSS_LVDS_SCRSS_VALUE_CFG_TS_CNTR_BITS_4SCRSS_Pos 0UL 2488 #define LVDSSS_LVDS_SCRSS_VALUE_CFG_TS_CNTR_BITS_4SCRSS_Msk 0x3UL 2489 #define LVDSSS_LVDS_SCRSS_VALUE_CFG_BUS_INTRVL_BITS_4SCRSS_Pos 2UL 2490 #define LVDSSS_LVDS_SCRSS_VALUE_CFG_BUS_INTRVL_BITS_4SCRSS_Msk 0xCUL 2491 /* LVDSSS_LVDS.TRAINING_BLK_CFG */ 2492 #define LVDSSS_LVDS_TRAINING_BLK_CFG_ENABLE_LNK0_DESKEW_Pos 0UL 2493 #define LVDSSS_LVDS_TRAINING_BLK_CFG_ENABLE_LNK0_DESKEW_Msk 0x1UL 2494 #define LVDSSS_LVDS_TRAINING_BLK_CFG_ENABLE_LNK1_DESKEW_Pos 1UL 2495 #define LVDSSS_LVDS_TRAINING_BLK_CFG_ENABLE_LNK1_DESKEW_Msk 0x2UL 2496 /* LVDSSS_LVDS.TRAINING_BLK */ 2497 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT0_Pos 0UL 2498 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT0_Msk 0xFFUL 2499 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT1_Pos 8UL 2500 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT1_Msk 0xFF00UL 2501 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT2_Pos 16UL 2502 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT2_Msk 0xFF0000UL 2503 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT3_Pos 24UL 2504 #define LVDSSS_LVDS_TRAINING_BLK_TRAINING_BLK_BYT3_Msk 0xFF000000UL 2505 /* LVDSSS_LVDS.LINK_TRAINING_STS */ 2506 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE0_TRAINING_BLK_DTCTD_Pos 0UL 2507 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE0_TRAINING_BLK_DTCTD_Msk 0x1UL 2508 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE1_TRAINING_BLK_DTCTD_Pos 1UL 2509 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE1_TRAINING_BLK_DTCTD_Msk 0x2UL 2510 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE2_TRAINING_BLK_DTCTD_Pos 2UL 2511 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE2_TRAINING_BLK_DTCTD_Msk 0x4UL 2512 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE3_TRAINING_BLK_DTCTD_Pos 3UL 2513 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE3_TRAINING_BLK_DTCTD_Msk 0x8UL 2514 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE4_TRAINING_BLK_DTCTD_Pos 4UL 2515 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE4_TRAINING_BLK_DTCTD_Msk 0x10UL 2516 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE5_TRAINING_BLK_DTCTD_Pos 5UL 2517 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE5_TRAINING_BLK_DTCTD_Msk 0x20UL 2518 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE6_TRAINING_BLK_DTCTD_Pos 6UL 2519 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE6_TRAINING_BLK_DTCTD_Msk 0x40UL 2520 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE7_TRAINING_BLK_DTCTD_Pos 7UL 2521 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE7_TRAINING_BLK_DTCTD_Msk 0x80UL 2522 #define LVDSSS_LVDS_LINK_TRAINING_STS_CTRL_LANE_TRAINING_BLK_DTCTD_Pos 8UL 2523 #define LVDSSS_LVDS_LINK_TRAINING_STS_CTRL_LANE_TRAINING_BLK_DTCTD_Msk 0x100UL 2524 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE0_TRAINING_BLK_DTCT_FAILED_Pos 16UL 2525 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE0_TRAINING_BLK_DTCT_FAILED_Msk 0x10000UL 2526 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE1_TRAINING_BLK_DTCT_FAILED_Pos 17UL 2527 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE1_TRAINING_BLK_DTCT_FAILED_Msk 0x20000UL 2528 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE2_TRAINING_BLK_DTCT_FAILED_Pos 18UL 2529 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE2_TRAINING_BLK_DTCT_FAILED_Msk 0x40000UL 2530 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE3_TRAINING_BLK_DTCT_FAILED_Pos 19UL 2531 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE3_TRAINING_BLK_DTCT_FAILED_Msk 0x80000UL 2532 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE4_TRAINING_BLK_DTCT_FAILED_Pos 20UL 2533 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE4_TRAINING_BLK_DTCT_FAILED_Msk 0x100000UL 2534 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE5_TRAINING_BLK_DTCT_FAILED_Pos 21UL 2535 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE5_TRAINING_BLK_DTCT_FAILED_Msk 0x200000UL 2536 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE6_TRAINING_BLK_DTCT_FAILED_Pos 22UL 2537 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE6_TRAINING_BLK_DTCT_FAILED_Msk 0x400000UL 2538 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE7_TRAINING_BLK_DTCT_FAILED_Pos 23UL 2539 #define LVDSSS_LVDS_LINK_TRAINING_STS_LANE7_TRAINING_BLK_DTCT_FAILED_Msk 0x800000UL 2540 #define LVDSSS_LVDS_LINK_TRAINING_STS_CTRL_LANE_TRAINING_BLK_DTCT_FAILED_Pos 24UL 2541 #define LVDSSS_LVDS_LINK_TRAINING_STS_CTRL_LANE_TRAINING_BLK_DTCT_FAILED_Msk 0x1000000UL 2542 /* LVDSSS_LVDS.DDFT_MUX_SEL */ 2543 #define LVDSSS_LVDS_DDFT_MUX_SEL_DDFT0_MUX_SEL_Pos 0UL 2544 #define LVDSSS_LVDS_DDFT_MUX_SEL_DDFT0_MUX_SEL_Msk 0xFFFUL 2545 #define LVDSSS_LVDS_DDFT_MUX_SEL_DDFT1_MUX_SEL_Pos 15UL 2546 #define LVDSSS_LVDS_DDFT_MUX_SEL_DDFT1_MUX_SEL_Msk 0x7FF8000UL 2547 /* LVDSSS_LVDS.GPIO_DDFT_MUX_SEL */ 2548 #define LVDSSS_LVDS_GPIO_DDFT_MUX_SEL_GPIO_DDFT0_MUX_SEL_Pos 0UL 2549 #define LVDSSS_LVDS_GPIO_DDFT_MUX_SEL_GPIO_DDFT0_MUX_SEL_Msk 0xFFFUL 2550 #define LVDSSS_LVDS_GPIO_DDFT_MUX_SEL_GPIO_DDFT1_MUX_SEL_Pos 15UL 2551 #define LVDSSS_LVDS_GPIO_DDFT_MUX_SEL_GPIO_DDFT1_MUX_SEL_Msk 0x7FF8000UL 2552 /* LVDSSS_LVDS.LOOPBACK_CFG */ 2553 #define LVDSSS_LVDS_LOOPBACK_CFG_LINK0_PUT_LNK1_TESTER_EN_Pos 0UL 2554 #define LVDSSS_LVDS_LOOPBACK_CFG_LINK0_PUT_LNK1_TESTER_EN_Msk 0x1UL 2555 #define LVDSSS_LVDS_LOOPBACK_CFG_LINK1_PUT_LNK0_TESTER_EN_Pos 1UL 2556 #define LVDSSS_LVDS_LOOPBACK_CFG_LINK1_PUT_LNK0_TESTER_EN_Msk 0x2UL 2557 /* LVDSSS_LVDS.LVDS_CHAR_CFG */ 2558 #define LVDSSS_LVDS_LVDS_CHAR_CFG_LVDS_DATA_LANE_EN_Pos 0UL 2559 #define LVDSSS_LVDS_LVDS_CHAR_CFG_LVDS_DATA_LANE_EN_Msk 0xFFUL 2560 #define LVDSSS_LVDS_LVDS_CHAR_CFG_LVDS_CTRL_LANE_EN_Pos 8UL 2561 #define LVDSSS_LVDS_LVDS_CHAR_CFG_LVDS_CTRL_LANE_EN_Msk 0x100UL 2562 #define LVDSSS_LVDS_LVDS_CHAR_CFG_LVDS_CHAR_EN_Pos 31UL 2563 #define LVDSSS_LVDS_LVDS_CHAR_CFG_LVDS_CHAR_EN_Msk 0x80000000UL 2564 /* LVDSSS_LVDS.CLK_GATE_DIS */ 2565 #define LVDSSS_LVDS_CLK_GATE_DIS_TH0_CLK_GATE_DISABLE_Pos 0UL 2566 #define LVDSSS_LVDS_CLK_GATE_DIS_TH0_CLK_GATE_DISABLE_Msk 0x1UL 2567 #define LVDSSS_LVDS_CLK_GATE_DIS_TH1_CLK_GATE_DISABLE_Pos 1UL 2568 #define LVDSSS_LVDS_CLK_GATE_DIS_TH1_CLK_GATE_DISABLE_Msk 0x2UL 2569 #define LVDSSS_LVDS_CLK_GATE_DIS_TH2_CLK_GATE_DISABLE_Pos 2UL 2570 #define LVDSSS_LVDS_CLK_GATE_DIS_TH2_CLK_GATE_DISABLE_Msk 0x4UL 2571 #define LVDSSS_LVDS_CLK_GATE_DIS_TH3_CLK_GATE_DISABLE_Pos 3UL 2572 #define LVDSSS_LVDS_CLK_GATE_DIS_TH3_CLK_GATE_DISABLE_Msk 0x8UL 2573 /* LVDSSS_LVDS.VERSION_SEL */ 2574 #define LVDSSS_LVDS_VERSION_SEL_A0_SEL_Pos 0UL 2575 #define LVDSSS_LVDS_VERSION_SEL_A0_SEL_Msk 0x1UL 2576 #define LVDSSS_LVDS_VERSION_SEL_SKEW_MONITOR_A0_SEL_Pos 1UL 2577 #define LVDSSS_LVDS_VERSION_SEL_SKEW_MONITOR_A0_SEL_Msk 0x2UL 2578 /* LVDSSS_LVDS.TH0_TH1_METADATA_RAM */ 2579 #define LVDSSS_LVDS_TH0_TH1_METADATA_RAM_METADATA_Pos 0UL 2580 #define LVDSSS_LVDS_TH0_TH1_METADATA_RAM_METADATA_Msk 0xFFFFFFFFUL 2581 /* LVDSSS_LVDS.TH2_TH3_METADATA_RAM */ 2582 #define LVDSSS_LVDS_TH2_TH3_METADATA_RAM_METADATA_Pos 0UL 2583 #define LVDSSS_LVDS_TH2_TH3_METADATA_RAM_METADATA_Msk 0xFFFFFFFFUL 2584 2585 2586 #endif /* _CYIP_LVDSSS_H_ */ 2587 2588 2589 /* [] END OF FILE */ 2590
