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Searched refs:PCLK_TCPWM0_CLOCKS256 (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_04_config.h44 PCLK_TCPWM0_CLOCKS256 = 0x000Bu, /* tcpwm[0].clocks[256] */ enumerator
Dtviibe1m_config.h127 PCLK_TCPWM0_CLOCKS256 = 0x005Eu, /* tcpwm[0].clocks[256] */ enumerator
Dtviibe2m_config.h137 PCLK_TCPWM0_CLOCKS256 = 0x0068u, /* tcpwm[0].clocks[256] */ enumerator
Dtviibe4m_config.h137 PCLK_TCPWM0_CLOCKS256 = 0x0068u, /* tcpwm[0].clocks[256] */ enumerator
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h140 PCLK_TCPWM0_CLOCKS256 = 0x0165u, /* tcpwm[0].clocks[256] */ enumerator
Dtviic2d6m_config.h73 PCLK_TCPWM0_CLOCKS256 = 0x0028u, /* tcpwm[0].clocks[256] */ enumerator
Dxmc7200_config.h42 PCLK_TCPWM0_CLOCKS256 = 0x0009u, /* tcpwm[0].clocks[256] */ enumerator