1 /***************************************************************************//** 2 * \file cyip_promc.h 3 * 4 * \brief 5 * PROMC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_PROMC_H_ 28 #define _CYIP_PROMC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * PROMC 34 *******************************************************************************/ 35 36 #define PROMC_MPC_SECTION_SIZE 0x00001000UL 37 #define PROMC_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief MPC Memory Protection Controller registers (PROMC_MPC) 41 */ 42 typedef struct { 43 __IOM uint32_t CFG; /*!< 0x00000000 Config register with error response, RegionID PPC_MPC_MAIN is 44 the security owner PC. The error response configuration is 45 located in CFG.RESPONSE, only one such configuration exists 46 applying to all protection contexts in the system. */ 47 __IM uint32_t RESERVED[3]; 48 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt */ 49 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */ 50 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */ 51 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */ 52 __IM uint32_t INTR_INFO1; /*!< 0x00000020 Infor about violation */ 53 __IM uint32_t INTR_INFO2; /*!< 0x00000024 Infor about violation */ 54 __IM uint32_t RESERVED1[54]; 55 __IOM uint32_t CTRL; /*!< 0x00000100 Control register with lock bit and auto-increment only 56 (Separate CTRL for each PC depends on access_pc) */ 57 __IM uint32_t BLK_MAX; /*!< 0x00000104 Max value of block-based index register */ 58 __IM uint32_t BLK_CFG; /*!< 0x00000108 Block size & initialization in progress */ 59 __IOM uint32_t BLK_IDX; /*!< 0x0000010C Index of 32-block group accessed through BLK_LUT (Separate IDX 60 for each PC depending on access_pc) */ 61 __IOM uint32_t BLK_LUT; /*!< 0x00000110 NS status for 32 blocks at BLK_IDX with PC=<access_pc> */ 62 __IM uint32_t RESERVED2[59]; 63 __IOM uint32_t ROT_CTRL; /*!< 0x00000200 Control register with lock bit and auto-increment only */ 64 __IOM uint32_t ROT_CFG; /*!< 0x00000204 Sets block-size to match memory size (external memory only) */ 65 __IM uint32_t ROT_BLK_MAX; /*!< 0x00000208 Max value of block-based index register for ROT */ 66 __IM uint32_t ROT_BLK_CFG; /*!< 0x0000020C Same as BLK_CFG */ 67 __IOM uint32_t ROT_BLK_IDX; /*!< 0x00000210 Index of 8-block group accessed through ROT_BLK_LUT_* */ 68 __IOM uint32_t ROT_BLK_PC; /*!< 0x00000214 Protection context of 8-block group accesses through 69 ROT_BLK_LUT */ 70 __IOM uint32_t ROT_BLK_LUT; /*!< 0x00000218 (R,W,NS) bits for 8 blocks at ROT_BLK_IDX for PC=ROT_BKL_PC */ 71 __IM uint32_t RESERVED3[889]; 72 } PROMC_MPC_Type; /*!< Size = 4096 (0x1000) */ 73 74 /** 75 * \brief Patchable ROM Controller (PROMC) 76 */ 77 typedef struct { 78 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 79 __IM uint32_t RESERVED[63]; 80 __IOM uint32_t PATCH_CTL; /*!< 0x00000100 Patch control */ 81 __IM uint32_t PATCH_STATUS; /*!< 0x00000104 Patch status */ 82 __IM uint32_t RESERVED1[2]; 83 __IM uint32_t PATCH_CFG; /*!< 0x00000110 Patch design time configuration info */ 84 __IM uint32_t RESERVED2[3]; 85 __IOM uint32_t PATCH_SROM; /*!< 0x00000120 Patch SROM boundary */ 86 __IM uint32_t RESERVED3[439]; 87 __IOM uint32_t PATCH_STRUCT_CTL[512]; /*!< 0x00000800 Patch structure control */ 88 PROMC_MPC_Type MPC[1]; /*!< 0x00001000 MPC Memory Protection Controller registers */ 89 __IM uint32_t RESERVED4[6144]; 90 __IOM uint32_t PATCH_DATA[8192]; /*!< 0x00008000 Patch data RAM */ 91 } PROMC_Type; /*!< Size = 65536 (0x10000) */ 92 93 94 /* PROMC_MPC.CFG */ 95 #define PROMC_MPC_CFG_RESPONSE_Pos 4UL 96 #define PROMC_MPC_CFG_RESPONSE_Msk 0x10UL 97 /* PROMC_MPC.INTR */ 98 #define PROMC_MPC_INTR_VIOLATION_Pos 0UL 99 #define PROMC_MPC_INTR_VIOLATION_Msk 0x1UL 100 /* PROMC_MPC.INTR_SET */ 101 #define PROMC_MPC_INTR_SET_VIOLATION_Pos 0UL 102 #define PROMC_MPC_INTR_SET_VIOLATION_Msk 0x1UL 103 /* PROMC_MPC.INTR_MASK */ 104 #define PROMC_MPC_INTR_MASK_VIOLATION_Pos 0UL 105 #define PROMC_MPC_INTR_MASK_VIOLATION_Msk 0x1UL 106 /* PROMC_MPC.INTR_MASKED */ 107 #define PROMC_MPC_INTR_MASKED_VIOLATION_Pos 0UL 108 #define PROMC_MPC_INTR_MASKED_VIOLATION_Msk 0x1UL 109 /* PROMC_MPC.INTR_INFO1 */ 110 #define PROMC_MPC_INTR_INFO1_VALUE_Pos 0UL 111 #define PROMC_MPC_INTR_INFO1_VALUE_Msk 0xFFFFFFFFUL 112 /* PROMC_MPC.INTR_INFO2 */ 113 #define PROMC_MPC_INTR_INFO2_HMASTER_Pos 0UL 114 #define PROMC_MPC_INTR_INFO2_HMASTER_Msk 0xFFFFUL 115 #define PROMC_MPC_INTR_INFO2_HNONSEC_Pos 16UL 116 #define PROMC_MPC_INTR_INFO2_HNONSEC_Msk 0x10000UL 117 #define PROMC_MPC_INTR_INFO2_CFG_NS_Pos 17UL 118 #define PROMC_MPC_INTR_INFO2_CFG_NS_Msk 0x20000UL 119 #define PROMC_MPC_INTR_INFO2_HWRITE_Pos 18UL 120 #define PROMC_MPC_INTR_INFO2_HWRITE_Msk 0x40000UL 121 #define PROMC_MPC_INTR_INFO2_HAUSER_Pos 24UL 122 #define PROMC_MPC_INTR_INFO2_HAUSER_Msk 0xF000000UL 123 #define PROMC_MPC_INTR_INFO2_SECURITY_VIOLATION_Pos 30UL 124 #define PROMC_MPC_INTR_INFO2_SECURITY_VIOLATION_Msk 0x40000000UL 125 #define PROMC_MPC_INTR_INFO2_ACCESS_VIOLATION_Pos 31UL 126 #define PROMC_MPC_INTR_INFO2_ACCESS_VIOLATION_Msk 0x80000000UL 127 /* PROMC_MPC.CTRL */ 128 #define PROMC_MPC_CTRL_AUTO_INC_Pos 8UL 129 #define PROMC_MPC_CTRL_AUTO_INC_Msk 0x100UL 130 #define PROMC_MPC_CTRL_LOCK_Pos 31UL 131 #define PROMC_MPC_CTRL_LOCK_Msk 0x80000000UL 132 /* PROMC_MPC.BLK_MAX */ 133 #define PROMC_MPC_BLK_MAX_VALUE_Pos 0UL 134 #define PROMC_MPC_BLK_MAX_VALUE_Msk 0xFFFFFFFFUL 135 /* PROMC_MPC.BLK_CFG */ 136 #define PROMC_MPC_BLK_CFG_BLOCK_SIZE_Pos 0UL 137 #define PROMC_MPC_BLK_CFG_BLOCK_SIZE_Msk 0xFUL 138 #define PROMC_MPC_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL 139 #define PROMC_MPC_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL 140 /* PROMC_MPC.BLK_IDX */ 141 #define PROMC_MPC_BLK_IDX_VALUE_Pos 0UL 142 #define PROMC_MPC_BLK_IDX_VALUE_Msk 0xFFFFFFFFUL 143 /* PROMC_MPC.BLK_LUT */ 144 #define PROMC_MPC_BLK_LUT_ATTR_NS0_Pos 0UL 145 #define PROMC_MPC_BLK_LUT_ATTR_NS0_Msk 0x1UL 146 #define PROMC_MPC_BLK_LUT_ATTR_NS1_Pos 1UL 147 #define PROMC_MPC_BLK_LUT_ATTR_NS1_Msk 0x2UL 148 #define PROMC_MPC_BLK_LUT_ATTR_NS2_Pos 2UL 149 #define PROMC_MPC_BLK_LUT_ATTR_NS2_Msk 0x4UL 150 #define PROMC_MPC_BLK_LUT_ATTR_NS3_Pos 3UL 151 #define PROMC_MPC_BLK_LUT_ATTR_NS3_Msk 0x8UL 152 #define PROMC_MPC_BLK_LUT_ATTR_NS4_Pos 4UL 153 #define PROMC_MPC_BLK_LUT_ATTR_NS4_Msk 0x10UL 154 #define PROMC_MPC_BLK_LUT_ATTR_NS5_Pos 5UL 155 #define PROMC_MPC_BLK_LUT_ATTR_NS5_Msk 0x20UL 156 #define PROMC_MPC_BLK_LUT_ATTR_NS6_Pos 6UL 157 #define PROMC_MPC_BLK_LUT_ATTR_NS6_Msk 0x40UL 158 #define PROMC_MPC_BLK_LUT_ATTR_NS7_Pos 7UL 159 #define PROMC_MPC_BLK_LUT_ATTR_NS7_Msk 0x80UL 160 #define PROMC_MPC_BLK_LUT_ATTR_NS8_Pos 8UL 161 #define PROMC_MPC_BLK_LUT_ATTR_NS8_Msk 0x100UL 162 #define PROMC_MPC_BLK_LUT_ATTR_NS9_Pos 9UL 163 #define PROMC_MPC_BLK_LUT_ATTR_NS9_Msk 0x200UL 164 #define PROMC_MPC_BLK_LUT_ATTR_NS10_Pos 10UL 165 #define PROMC_MPC_BLK_LUT_ATTR_NS10_Msk 0x400UL 166 #define PROMC_MPC_BLK_LUT_ATTR_NS11_Pos 11UL 167 #define PROMC_MPC_BLK_LUT_ATTR_NS11_Msk 0x800UL 168 #define PROMC_MPC_BLK_LUT_ATTR_NS12_Pos 12UL 169 #define PROMC_MPC_BLK_LUT_ATTR_NS12_Msk 0x1000UL 170 #define PROMC_MPC_BLK_LUT_ATTR_NS13_Pos 13UL 171 #define PROMC_MPC_BLK_LUT_ATTR_NS13_Msk 0x2000UL 172 #define PROMC_MPC_BLK_LUT_ATTR_NS14_Pos 14UL 173 #define PROMC_MPC_BLK_LUT_ATTR_NS14_Msk 0x4000UL 174 #define PROMC_MPC_BLK_LUT_ATTR_NS15_Pos 15UL 175 #define PROMC_MPC_BLK_LUT_ATTR_NS15_Msk 0x8000UL 176 #define PROMC_MPC_BLK_LUT_ATTR_NS16_Pos 16UL 177 #define PROMC_MPC_BLK_LUT_ATTR_NS16_Msk 0x10000UL 178 #define PROMC_MPC_BLK_LUT_ATTR_NS17_Pos 17UL 179 #define PROMC_MPC_BLK_LUT_ATTR_NS17_Msk 0x20000UL 180 #define PROMC_MPC_BLK_LUT_ATTR_NS18_Pos 18UL 181 #define PROMC_MPC_BLK_LUT_ATTR_NS18_Msk 0x40000UL 182 #define PROMC_MPC_BLK_LUT_ATTR_NS19_Pos 19UL 183 #define PROMC_MPC_BLK_LUT_ATTR_NS19_Msk 0x80000UL 184 #define PROMC_MPC_BLK_LUT_ATTR_NS20_Pos 20UL 185 #define PROMC_MPC_BLK_LUT_ATTR_NS20_Msk 0x100000UL 186 #define PROMC_MPC_BLK_LUT_ATTR_NS21_Pos 21UL 187 #define PROMC_MPC_BLK_LUT_ATTR_NS21_Msk 0x200000UL 188 #define PROMC_MPC_BLK_LUT_ATTR_NS22_Pos 22UL 189 #define PROMC_MPC_BLK_LUT_ATTR_NS22_Msk 0x400000UL 190 #define PROMC_MPC_BLK_LUT_ATTR_NS23_Pos 23UL 191 #define PROMC_MPC_BLK_LUT_ATTR_NS23_Msk 0x800000UL 192 #define PROMC_MPC_BLK_LUT_ATTR_NS24_Pos 24UL 193 #define PROMC_MPC_BLK_LUT_ATTR_NS24_Msk 0x1000000UL 194 #define PROMC_MPC_BLK_LUT_ATTR_NS25_Pos 25UL 195 #define PROMC_MPC_BLK_LUT_ATTR_NS25_Msk 0x2000000UL 196 #define PROMC_MPC_BLK_LUT_ATTR_NS26_Pos 26UL 197 #define PROMC_MPC_BLK_LUT_ATTR_NS26_Msk 0x4000000UL 198 #define PROMC_MPC_BLK_LUT_ATTR_NS27_Pos 27UL 199 #define PROMC_MPC_BLK_LUT_ATTR_NS27_Msk 0x8000000UL 200 #define PROMC_MPC_BLK_LUT_ATTR_NS28_Pos 28UL 201 #define PROMC_MPC_BLK_LUT_ATTR_NS28_Msk 0x10000000UL 202 #define PROMC_MPC_BLK_LUT_ATTR_NS29_Pos 29UL 203 #define PROMC_MPC_BLK_LUT_ATTR_NS29_Msk 0x20000000UL 204 #define PROMC_MPC_BLK_LUT_ATTR_NS30_Pos 30UL 205 #define PROMC_MPC_BLK_LUT_ATTR_NS30_Msk 0x40000000UL 206 #define PROMC_MPC_BLK_LUT_ATTR_NS31_Pos 31UL 207 #define PROMC_MPC_BLK_LUT_ATTR_NS31_Msk 0x80000000UL 208 /* PROMC_MPC.ROT_CTRL */ 209 #define PROMC_MPC_ROT_CTRL_AUTO_INC_Pos 8UL 210 #define PROMC_MPC_ROT_CTRL_AUTO_INC_Msk 0x100UL 211 #define PROMC_MPC_ROT_CTRL_LOCK_Pos 31UL 212 #define PROMC_MPC_ROT_CTRL_LOCK_Msk 0x80000000UL 213 /* PROMC_MPC.ROT_CFG */ 214 #define PROMC_MPC_ROT_CFG_BLOCK_SIZE_Pos 0UL 215 #define PROMC_MPC_ROT_CFG_BLOCK_SIZE_Msk 0xFUL 216 /* PROMC_MPC.ROT_BLK_MAX */ 217 #define PROMC_MPC_ROT_BLK_MAX_VALUE_Pos 0UL 218 #define PROMC_MPC_ROT_BLK_MAX_VALUE_Msk 0xFFFFFFFFUL 219 /* PROMC_MPC.ROT_BLK_CFG */ 220 #define PROMC_MPC_ROT_BLK_CFG_BLOCK_SIZE_Pos 0UL 221 #define PROMC_MPC_ROT_BLK_CFG_BLOCK_SIZE_Msk 0xFUL 222 #define PROMC_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Pos 31UL 223 #define PROMC_MPC_ROT_BLK_CFG_INIT_IN_PROGRESS_Msk 0x80000000UL 224 /* PROMC_MPC.ROT_BLK_IDX */ 225 #define PROMC_MPC_ROT_BLK_IDX_VALUE_Pos 0UL 226 #define PROMC_MPC_ROT_BLK_IDX_VALUE_Msk 0xFFFFFFFFUL 227 /* PROMC_MPC.ROT_BLK_PC */ 228 #define PROMC_MPC_ROT_BLK_PC_PC_Pos 0UL 229 #define PROMC_MPC_ROT_BLK_PC_PC_Msk 0xFUL 230 /* PROMC_MPC.ROT_BLK_LUT */ 231 #define PROMC_MPC_ROT_BLK_LUT_ATTR0_Pos 0UL 232 #define PROMC_MPC_ROT_BLK_LUT_ATTR0_Msk 0x7UL 233 #define PROMC_MPC_ROT_BLK_LUT_ATTR1_Pos 4UL 234 #define PROMC_MPC_ROT_BLK_LUT_ATTR1_Msk 0x70UL 235 #define PROMC_MPC_ROT_BLK_LUT_ATTR2_Pos 8UL 236 #define PROMC_MPC_ROT_BLK_LUT_ATTR2_Msk 0x700UL 237 #define PROMC_MPC_ROT_BLK_LUT_ATTR3_Pos 12UL 238 #define PROMC_MPC_ROT_BLK_LUT_ATTR3_Msk 0x7000UL 239 #define PROMC_MPC_ROT_BLK_LUT_ATTR4_Pos 16UL 240 #define PROMC_MPC_ROT_BLK_LUT_ATTR4_Msk 0x70000UL 241 #define PROMC_MPC_ROT_BLK_LUT_ATTR5_Pos 20UL 242 #define PROMC_MPC_ROT_BLK_LUT_ATTR5_Msk 0x700000UL 243 #define PROMC_MPC_ROT_BLK_LUT_ATTR6_Pos 24UL 244 #define PROMC_MPC_ROT_BLK_LUT_ATTR6_Msk 0x7000000UL 245 #define PROMC_MPC_ROT_BLK_LUT_ATTR7_Pos 28UL 246 #define PROMC_MPC_ROT_BLK_LUT_ATTR7_Msk 0x70000000UL 247 248 249 /* PROMC.CTL */ 250 #define PROMC_CTL_ROM_WS_Pos 0UL 251 #define PROMC_CTL_ROM_WS_Msk 0x3UL 252 /* PROMC.PATCH_CTL */ 253 #define PROMC_PATCH_CTL_ENABLED_Pos 31UL 254 #define PROMC_PATCH_CTL_ENABLED_Msk 0x80000000UL 255 /* PROMC.PATCH_STATUS */ 256 #define PROMC_PATCH_STATUS_PATCH_IDX_Pos 0UL 257 #define PROMC_PATCH_STATUS_PATCH_IDX_Msk 0x1FFUL 258 #define PROMC_PATCH_STATUS_PATCH_VALID_Pos 31UL 259 #define PROMC_PATCH_STATUS_PATCH_VALID_Msk 0x80000000UL 260 /* PROMC.PATCH_CFG */ 261 #define PROMC_PATCH_CFG_PATCH_NR_Pos 0UL 262 #define PROMC_PATCH_CFG_PATCH_NR_Msk 0x3FFUL 263 #define PROMC_PATCH_CFG_PATCH_SIZE_Pos 16UL 264 #define PROMC_PATCH_CFG_PATCH_SIZE_Msk 0x30000UL 265 /* PROMC.PATCH_SROM */ 266 #define PROMC_PATCH_SROM_BOUNDARY_Pos 0UL 267 #define PROMC_PATCH_SROM_BOUNDARY_Msk 0xFFFFFFFFUL 268 /* PROMC.PATCH_STRUCT_CTL */ 269 #define PROMC_PATCH_STRUCT_CTL_VALID_Pos 0UL 270 #define PROMC_PATCH_STRUCT_CTL_VALID_Msk 0x1UL 271 #define PROMC_PATCH_STRUCT_CTL_MATCH_ADDR_Pos 4UL 272 #define PROMC_PATCH_STRUCT_CTL_MATCH_ADDR_Msk 0xFFFFFFF0UL 273 /* PROMC.PATCH_DATA */ 274 #define PROMC_PATCH_DATA_DATA_Pos 0UL 275 #define PROMC_PATCH_DATA_DATA_Msk 0xFFFFFFFFUL 276 277 278 #endif /* _CYIP_PROMC_H_ */ 279 280 281 /* [] END OF FILE */ 282
