1 /***************************************************************************//** 2 * \file gpio_tviic2d6m_327_bga.h 3 * 4 * \brief 5 * TVIIC2D6M device GPIO header for 327-BGA package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_TVIIC2D6M_327_BGA_H_ 28 #define _GPIO_TVIIC2D6M_327_BGA_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 327u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ECT, 50 AMUXBUS_FPDLINK0, 51 AMUXBUS_FPDLINK1, 52 AMUXBUS_MAIN, 53 AMUXBUS_MIPI, 54 AMUXBUS_TEST, 55 AMUXBUS_TESTSRSS, 56 }; 57 58 /* AMUX Splitter Controls */ 59 typedef enum 60 { 61 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_TEST; Right = AMUXBUS_TESTSRSS */ 62 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_ECT; Right = AMUXBUS_TEST */ 63 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_MIPI; Right = AMUXBUS_TEST */ 64 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_FPDLINK0; Right = AMUXBUS_TEST */ 65 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_FPDLINK1; Right = AMUXBUS_TEST */ 66 AMUX_SPLIT_CTL_5 = 0x0005u /* Left = AMUXBUS_MAIN; Right = AMUXBUS_TEST */ 67 } cy_en_amux_split_t; 68 69 /* Port List */ 70 /* PORT 0 (GPIO) */ 71 #define P0_0_PORT GPIO_PRT0 72 #define P0_0_PIN 0u 73 #define P0_0_NUM 0u 74 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 75 #define P0_1_PORT GPIO_PRT0 76 #define P0_1_PIN 1u 77 #define P0_1_NUM 1u 78 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 79 #define P0_2_PORT GPIO_PRT0 80 #define P0_2_PIN 2u 81 #define P0_2_NUM 2u 82 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 83 #define P0_3_PORT GPIO_PRT0 84 #define P0_3_PIN 3u 85 #define P0_3_NUM 3u 86 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 87 #define P0_4_PORT GPIO_PRT0 88 #define P0_4_PIN 4u 89 #define P0_4_NUM 4u 90 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 91 #define P0_5_PORT GPIO_PRT0 92 #define P0_5_PIN 5u 93 #define P0_5_NUM 5u 94 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 95 96 /* PORT 1 (GPIO) */ 97 #define P1_0_PORT GPIO_PRT1 98 #define P1_0_PIN 0u 99 #define P1_0_NUM 0u 100 #define P1_0_AMUXSEGMENT AMUXBUS_MAIN 101 #define P1_1_PORT GPIO_PRT1 102 #define P1_1_PIN 1u 103 #define P1_1_NUM 1u 104 #define P1_1_AMUXSEGMENT AMUXBUS_MAIN 105 #define P1_4_PORT GPIO_PRT1 106 #define P1_4_PIN 4u 107 #define P1_4_NUM 4u 108 #define P1_4_AMUXSEGMENT AMUXBUS_MAIN 109 #define P1_5_PORT GPIO_PRT1 110 #define P1_5_PIN 5u 111 #define P1_5_NUM 5u 112 #define P1_5_AMUXSEGMENT AMUXBUS_MAIN 113 114 /* PORT 2 (GPIO) */ 115 #define P2_3_PORT GPIO_PRT2 116 #define P2_3_PIN 3u 117 #define P2_3_NUM 3u 118 #define P2_3_AMUXSEGMENT AMUXBUS_MAIN 119 #define P2_4_PORT GPIO_PRT2 120 #define P2_4_PIN 4u 121 #define P2_4_NUM 4u 122 #define P2_4_AMUXSEGMENT AMUXBUS_MAIN 123 #define P2_5_PORT GPIO_PRT2 124 #define P2_5_PIN 5u 125 #define P2_5_NUM 5u 126 #define P2_5_AMUXSEGMENT AMUXBUS_TEST 127 #define P2_6_PORT GPIO_PRT2 128 #define P2_6_PIN 6u 129 #define P2_6_NUM 6u 130 #define P2_6_AMUXSEGMENT AMUXBUS_TEST 131 132 /* PORT 3 (GPIO) */ 133 #define P3_0_PORT GPIO_PRT3 134 #define P3_0_PIN 0u 135 #define P3_0_NUM 0u 136 #define P3_0_AMUXSEGMENT AMUXBUS_MAIN 137 #define P3_1_PORT GPIO_PRT3 138 #define P3_1_PIN 1u 139 #define P3_1_NUM 1u 140 #define P3_1_AMUXSEGMENT AMUXBUS_MAIN 141 #define P3_2_PORT GPIO_PRT3 142 #define P3_2_PIN 2u 143 #define P3_2_NUM 2u 144 #define P3_2_AMUXSEGMENT AMUXBUS_MAIN 145 #define P3_3_PORT GPIO_PRT3 146 #define P3_3_PIN 3u 147 #define P3_3_NUM 3u 148 #define P3_3_AMUXSEGMENT AMUXBUS_MAIN 149 #define P3_4_PORT GPIO_PRT3 150 #define P3_4_PIN 4u 151 #define P3_4_NUM 4u 152 #define P3_4_AMUXSEGMENT AMUXBUS_MAIN 153 154 /* PORT 4 (GPIO) */ 155 #define P4_0_PORT GPIO_PRT4 156 #define P4_0_PIN 0u 157 #define P4_0_NUM 0u 158 #define P4_0_AMUXSEGMENT AMUXBUS_MAIN 159 #define P4_1_PORT GPIO_PRT4 160 #define P4_1_PIN 1u 161 #define P4_1_NUM 1u 162 #define P4_1_AMUXSEGMENT AMUXBUS_MAIN 163 #define P4_2_PORT GPIO_PRT4 164 #define P4_2_PIN 2u 165 #define P4_2_NUM 2u 166 #define P4_2_AMUXSEGMENT AMUXBUS_MAIN 167 #define P4_3_PORT GPIO_PRT4 168 #define P4_3_PIN 3u 169 #define P4_3_NUM 3u 170 #define P4_3_AMUXSEGMENT AMUXBUS_MAIN 171 #define P4_4_PORT GPIO_PRT4 172 #define P4_4_PIN 4u 173 #define P4_4_NUM 4u 174 #define P4_4_AMUXSEGMENT AMUXBUS_MAIN 175 #define P4_5_PORT GPIO_PRT4 176 #define P4_5_PIN 5u 177 #define P4_5_NUM 5u 178 #define P4_5_AMUXSEGMENT AMUXBUS_MAIN 179 #define P4_6_PORT GPIO_PRT4 180 #define P4_6_PIN 6u 181 #define P4_6_NUM 6u 182 #define P4_6_AMUXSEGMENT AMUXBUS_MAIN 183 #define P4_7_PORT GPIO_PRT4 184 #define P4_7_PIN 7u 185 #define P4_7_NUM 7u 186 #define P4_7_AMUXSEGMENT AMUXBUS_MAIN 187 188 /* PORT 5 (GPIO) */ 189 #define P5_0_PORT GPIO_PRT5 190 #define P5_0_PIN 0u 191 #define P5_0_NUM 0u 192 #define P5_0_AMUXSEGMENT AMUXBUS_MAIN 193 #define P5_1_PORT GPIO_PRT5 194 #define P5_1_PIN 1u 195 #define P5_1_NUM 1u 196 #define P5_1_AMUXSEGMENT AMUXBUS_MAIN 197 #define P5_2_PORT GPIO_PRT5 198 #define P5_2_PIN 2u 199 #define P5_2_NUM 2u 200 #define P5_2_AMUXSEGMENT AMUXBUS_MAIN 201 #define P5_3_PORT GPIO_PRT5 202 #define P5_3_PIN 3u 203 #define P5_3_NUM 3u 204 #define P5_3_AMUXSEGMENT AMUXBUS_MAIN 205 #define P5_4_PORT GPIO_PRT5 206 #define P5_4_PIN 4u 207 #define P5_4_NUM 4u 208 #define P5_4_AMUXSEGMENT AMUXBUS_MAIN 209 #define P5_5_PORT GPIO_PRT5 210 #define P5_5_PIN 5u 211 #define P5_5_NUM 5u 212 #define P5_5_AMUXSEGMENT AMUXBUS_MAIN 213 #define P5_6_PORT GPIO_PRT5 214 #define P5_6_PIN 6u 215 #define P5_6_NUM 6u 216 #define P5_6_AMUXSEGMENT AMUXBUS_MAIN 217 #define P5_7_PORT GPIO_PRT5 218 #define P5_7_PIN 7u 219 #define P5_7_NUM 7u 220 #define P5_7_AMUXSEGMENT AMUXBUS_MAIN 221 222 /* PORT 6 (GPIO) */ 223 #define P6_0_PORT GPIO_PRT6 224 #define P6_0_PIN 0u 225 #define P6_0_NUM 0u 226 #define P6_0_AMUXSEGMENT AMUXBUS_MAIN 227 #define P6_1_PORT GPIO_PRT6 228 #define P6_1_PIN 1u 229 #define P6_1_NUM 1u 230 #define P6_1_AMUXSEGMENT AMUXBUS_MAIN 231 #define P6_2_PORT GPIO_PRT6 232 #define P6_2_PIN 2u 233 #define P6_2_NUM 2u 234 #define P6_2_AMUXSEGMENT AMUXBUS_MAIN 235 #define P6_3_PORT GPIO_PRT6 236 #define P6_3_PIN 3u 237 #define P6_3_NUM 3u 238 #define P6_3_AMUXSEGMENT AMUXBUS_MAIN 239 #define P6_4_PORT GPIO_PRT6 240 #define P6_4_PIN 4u 241 #define P6_4_NUM 4u 242 #define P6_4_AMUXSEGMENT AMUXBUS_MAIN 243 #define P6_5_PORT GPIO_PRT6 244 #define P6_5_PIN 5u 245 #define P6_5_NUM 5u 246 #define P6_5_AMUXSEGMENT AMUXBUS_MAIN 247 #define P6_6_PORT GPIO_PRT6 248 #define P6_6_PIN 6u 249 #define P6_6_NUM 6u 250 #define P6_6_AMUXSEGMENT AMUXBUS_MAIN 251 #define P6_7_PORT GPIO_PRT6 252 #define P6_7_PIN 7u 253 #define P6_7_NUM 7u 254 #define P6_7_AMUXSEGMENT AMUXBUS_MAIN 255 256 /* PORT 7 (GPIO) */ 257 #define P7_0_PORT GPIO_PRT7 258 #define P7_0_PIN 0u 259 #define P7_0_NUM 0u 260 #define P7_0_AMUXSEGMENT AMUXBUS_MAIN 261 #define P7_1_PORT GPIO_PRT7 262 #define P7_1_PIN 1u 263 #define P7_1_NUM 1u 264 #define P7_1_AMUXSEGMENT AMUXBUS_MAIN 265 #define P7_2_PORT GPIO_PRT7 266 #define P7_2_PIN 2u 267 #define P7_2_NUM 2u 268 #define P7_2_AMUXSEGMENT AMUXBUS_MAIN 269 #define P7_3_PORT GPIO_PRT7 270 #define P7_3_PIN 3u 271 #define P7_3_NUM 3u 272 #define P7_3_AMUXSEGMENT AMUXBUS_MAIN 273 #define P7_4_PORT GPIO_PRT7 274 #define P7_4_PIN 4u 275 #define P7_4_NUM 4u 276 #define P7_4_AMUXSEGMENT AMUXBUS_MAIN 277 #define P7_5_PORT GPIO_PRT7 278 #define P7_5_PIN 5u 279 #define P7_5_NUM 5u 280 #define P7_5_AMUXSEGMENT AMUXBUS_MAIN 281 #define P7_6_PORT GPIO_PRT7 282 #define P7_6_PIN 6u 283 #define P7_6_NUM 6u 284 #define P7_6_AMUXSEGMENT AMUXBUS_MAIN 285 #define P7_7_PORT GPIO_PRT7 286 #define P7_7_PIN 7u 287 #define P7_7_NUM 7u 288 #define P7_7_AMUXSEGMENT AMUXBUS_MAIN 289 290 /* PORT 8 (GPIO) */ 291 #define P8_0_PORT GPIO_PRT8 292 #define P8_0_PIN 0u 293 #define P8_0_NUM 0u 294 #define P8_0_AMUXSEGMENT AMUXBUS_MAIN 295 #define P8_1_PORT GPIO_PRT8 296 #define P8_1_PIN 1u 297 #define P8_1_NUM 1u 298 #define P8_1_AMUXSEGMENT AMUXBUS_MAIN 299 #define P8_2_PORT GPIO_PRT8 300 #define P8_2_PIN 2u 301 #define P8_2_NUM 2u 302 #define P8_2_AMUXSEGMENT AMUXBUS_MAIN 303 #define P8_3_PORT GPIO_PRT8 304 #define P8_3_PIN 3u 305 #define P8_3_NUM 3u 306 #define P8_3_AMUXSEGMENT AMUXBUS_MAIN 307 308 /* PORT 9 (GPIO) */ 309 #define P9_0_PORT GPIO_PRT9 310 #define P9_0_PIN 0u 311 #define P9_0_NUM 0u 312 #define P9_0_AMUXSEGMENT AMUXBUS_MAIN 313 #define P9_1_PORT GPIO_PRT9 314 #define P9_1_PIN 1u 315 #define P9_1_NUM 1u 316 #define P9_1_AMUXSEGMENT AMUXBUS_MAIN 317 #define P9_2_PORT GPIO_PRT9 318 #define P9_2_PIN 2u 319 #define P9_2_NUM 2u 320 #define P9_2_AMUXSEGMENT AMUXBUS_MAIN 321 #define P9_3_PORT GPIO_PRT9 322 #define P9_3_PIN 3u 323 #define P9_3_NUM 3u 324 #define P9_3_AMUXSEGMENT AMUXBUS_MAIN 325 #define P9_4_PORT GPIO_PRT9 326 #define P9_4_PIN 4u 327 #define P9_4_NUM 4u 328 #define P9_4_AMUXSEGMENT AMUXBUS_MAIN 329 #define P9_5_PORT GPIO_PRT9 330 #define P9_5_PIN 5u 331 #define P9_5_NUM 5u 332 #define P9_5_AMUXSEGMENT AMUXBUS_MAIN 333 #define P9_6_PORT GPIO_PRT9 334 #define P9_6_PIN 6u 335 #define P9_6_NUM 6u 336 #define P9_6_AMUXSEGMENT AMUXBUS_MAIN 337 #define P9_7_PORT GPIO_PRT9 338 #define P9_7_PIN 7u 339 #define P9_7_NUM 7u 340 #define P9_7_AMUXSEGMENT AMUXBUS_MAIN 341 342 /* PORT 11 (GPIO) */ 343 #define P11_0_PORT GPIO_PRT11 344 #define P11_0_PIN 0u 345 #define P11_0_NUM 0u 346 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 347 #define P11_1_PORT GPIO_PRT11 348 #define P11_1_PIN 1u 349 #define P11_1_NUM 1u 350 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 351 #define P11_2_PORT GPIO_PRT11 352 #define P11_2_PIN 2u 353 #define P11_2_NUM 2u 354 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 355 #define P11_3_PORT GPIO_PRT11 356 #define P11_3_PIN 3u 357 #define P11_3_NUM 3u 358 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 359 #define P11_4_PORT GPIO_PRT11 360 #define P11_4_PIN 4u 361 #define P11_4_NUM 4u 362 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 363 #define P11_5_PORT GPIO_PRT11 364 #define P11_5_PIN 5u 365 #define P11_5_NUM 5u 366 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 367 #define P11_6_PORT GPIO_PRT11 368 #define P11_6_PIN 6u 369 #define P11_6_NUM 6u 370 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 371 #define P11_7_PORT GPIO_PRT11 372 #define P11_7_PIN 7u 373 #define P11_7_NUM 7u 374 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 375 376 /* PORT 12 (GPIO) */ 377 #define P12_0_PORT GPIO_PRT12 378 #define P12_0_PIN 0u 379 #define P12_0_NUM 0u 380 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 381 #define P12_1_PORT GPIO_PRT12 382 #define P12_1_PIN 1u 383 #define P12_1_NUM 1u 384 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 385 #define P12_2_PORT GPIO_PRT12 386 #define P12_2_PIN 2u 387 #define P12_2_NUM 2u 388 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 389 #define P12_3_PORT GPIO_PRT12 390 #define P12_3_PIN 3u 391 #define P12_3_NUM 3u 392 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 393 #define P12_4_PORT GPIO_PRT12 394 #define P12_4_PIN 4u 395 #define P12_4_NUM 4u 396 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 397 #define P12_5_PORT GPIO_PRT12 398 #define P12_5_PIN 5u 399 #define P12_5_NUM 5u 400 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 401 #define P12_6_PORT GPIO_PRT12 402 #define P12_6_PIN 6u 403 #define P12_6_NUM 6u 404 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 405 #define P12_7_PORT GPIO_PRT12 406 #define P12_7_PIN 7u 407 #define P12_7_NUM 7u 408 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 409 410 /* PORT 13 (GPIO) */ 411 #define P13_0_PORT GPIO_PRT13 412 #define P13_0_PIN 0u 413 #define P13_0_NUM 0u 414 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 415 #define P13_1_PORT GPIO_PRT13 416 #define P13_1_PIN 1u 417 #define P13_1_NUM 1u 418 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 419 #define P13_2_PORT GPIO_PRT13 420 #define P13_2_PIN 2u 421 #define P13_2_NUM 2u 422 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 423 #define P13_3_PORT GPIO_PRT13 424 #define P13_3_PIN 3u 425 #define P13_3_NUM 3u 426 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 427 #define P13_4_PORT GPIO_PRT13 428 #define P13_4_PIN 4u 429 #define P13_4_NUM 4u 430 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 431 #define P13_5_PORT GPIO_PRT13 432 #define P13_5_PIN 5u 433 #define P13_5_NUM 5u 434 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 435 #define P13_6_PORT GPIO_PRT13 436 #define P13_6_PIN 6u 437 #define P13_6_NUM 6u 438 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 439 #define P13_7_PORT GPIO_PRT13 440 #define P13_7_PIN 7u 441 #define P13_7_NUM 7u 442 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 443 444 /* PORT 14 (GPIO) */ 445 #define P14_0_PORT GPIO_PRT14 446 #define P14_0_PIN 0u 447 #define P14_0_NUM 0u 448 #define P14_0_AMUXSEGMENT AMUXBUS_MAIN 449 #define P14_1_PORT GPIO_PRT14 450 #define P14_1_PIN 1u 451 #define P14_1_NUM 1u 452 #define P14_1_AMUXSEGMENT AMUXBUS_MAIN 453 #define P14_2_PORT GPIO_PRT14 454 #define P14_2_PIN 2u 455 #define P14_2_NUM 2u 456 #define P14_2_AMUXSEGMENT AMUXBUS_MAIN 457 #define P14_3_PORT GPIO_PRT14 458 #define P14_3_PIN 3u 459 #define P14_3_NUM 3u 460 #define P14_3_AMUXSEGMENT AMUXBUS_MAIN 461 #define P14_4_PORT GPIO_PRT14 462 #define P14_4_PIN 4u 463 #define P14_4_NUM 4u 464 #define P14_4_AMUXSEGMENT AMUXBUS_MAIN 465 #define P14_5_PORT GPIO_PRT14 466 #define P14_5_PIN 5u 467 #define P14_5_NUM 5u 468 #define P14_5_AMUXSEGMENT AMUXBUS_MAIN 469 #define P14_6_PORT GPIO_PRT14 470 #define P14_6_PIN 6u 471 #define P14_6_NUM 6u 472 #define P14_6_AMUXSEGMENT AMUXBUS_MAIN 473 #define P14_7_PORT GPIO_PRT14 474 #define P14_7_PIN 7u 475 #define P14_7_NUM 7u 476 #define P14_7_AMUXSEGMENT AMUXBUS_MAIN 477 478 /* PORT 15 (GPIO) */ 479 #define P15_2_PORT GPIO_PRT15 480 #define P15_2_PIN 2u 481 #define P15_2_NUM 2u 482 #define P15_2_AMUXSEGMENT AMUXBUS_MAIN 483 #define P15_3_PORT GPIO_PRT15 484 #define P15_3_PIN 3u 485 #define P15_3_NUM 3u 486 #define P15_3_AMUXSEGMENT AMUXBUS_MAIN 487 #define P15_4_PORT GPIO_PRT15 488 #define P15_4_PIN 4u 489 #define P15_4_NUM 4u 490 #define P15_4_AMUXSEGMENT AMUXBUS_MAIN 491 #define P15_5_PORT GPIO_PRT15 492 #define P15_5_PIN 5u 493 #define P15_5_NUM 5u 494 #define P15_5_AMUXSEGMENT AMUXBUS_MAIN 495 #define P15_6_PORT GPIO_PRT15 496 #define P15_6_PIN 6u 497 #define P15_6_NUM 6u 498 #define P15_6_AMUXSEGMENT AMUXBUS_MAIN 499 #define P15_7_PORT GPIO_PRT15 500 #define P15_7_PIN 7u 501 #define P15_7_NUM 7u 502 #define P15_7_AMUXSEGMENT AMUXBUS_MAIN 503 504 /* PORT 16 (GPIO) */ 505 #define P16_0_PORT GPIO_PRT16 506 #define P16_0_PIN 0u 507 #define P16_0_NUM 0u 508 #define P16_0_AMUXSEGMENT AMUXBUS_MAIN 509 #define P16_1_PORT GPIO_PRT16 510 #define P16_1_PIN 1u 511 #define P16_1_NUM 1u 512 #define P16_1_AMUXSEGMENT AMUXBUS_MAIN 513 #define P16_2_PORT GPIO_PRT16 514 #define P16_2_PIN 2u 515 #define P16_2_NUM 2u 516 #define P16_2_AMUXSEGMENT AMUXBUS_MAIN 517 #define P16_3_PORT GPIO_PRT16 518 #define P16_3_PIN 3u 519 #define P16_3_NUM 3u 520 #define P16_3_AMUXSEGMENT AMUXBUS_MAIN 521 #define P16_4_PORT GPIO_PRT16 522 #define P16_4_PIN 4u 523 #define P16_4_NUM 4u 524 #define P16_4_AMUXSEGMENT AMUXBUS_MAIN 525 #define P16_5_PORT GPIO_PRT16 526 #define P16_5_PIN 5u 527 #define P16_5_NUM 5u 528 #define P16_5_AMUXSEGMENT AMUXBUS_MAIN 529 #define P16_6_PORT GPIO_PRT16 530 #define P16_6_PIN 6u 531 #define P16_6_NUM 6u 532 #define P16_6_AMUXSEGMENT AMUXBUS_MAIN 533 #define P16_7_PORT GPIO_PRT16 534 #define P16_7_PIN 7u 535 #define P16_7_NUM 7u 536 #define P16_7_AMUXSEGMENT AMUXBUS_MAIN 537 538 /* PORT 17 (GPIO) */ 539 #define P17_0_PORT GPIO_PRT17 540 #define P17_0_PIN 0u 541 #define P17_0_NUM 0u 542 #define P17_0_AMUXSEGMENT AMUXBUS_MAIN 543 544 /* PORT 18 (GPIO) */ 545 #define P18_0_PORT GPIO_PRT18 546 #define P18_0_PIN 0u 547 #define P18_0_NUM 0u 548 #define P18_0_AMUXSEGMENT AMUXBUS_MAIN 549 #define P18_1_PORT GPIO_PRT18 550 #define P18_1_PIN 1u 551 #define P18_1_NUM 1u 552 #define P18_1_AMUXSEGMENT AMUXBUS_MAIN 553 #define P18_2_PORT GPIO_PRT18 554 #define P18_2_PIN 2u 555 #define P18_2_NUM 2u 556 #define P18_2_AMUXSEGMENT AMUXBUS_MAIN 557 #define P18_3_PORT GPIO_PRT18 558 #define P18_3_PIN 3u 559 #define P18_3_NUM 3u 560 #define P18_3_AMUXSEGMENT AMUXBUS_MAIN 561 #define P18_4_PORT GPIO_PRT18 562 #define P18_4_PIN 4u 563 #define P18_4_NUM 4u 564 #define P18_4_AMUXSEGMENT AMUXBUS_MAIN 565 #define P18_5_PORT GPIO_PRT18 566 #define P18_5_PIN 5u 567 #define P18_5_NUM 5u 568 #define P18_5_AMUXSEGMENT AMUXBUS_MAIN 569 #define P18_6_PORT GPIO_PRT18 570 #define P18_6_PIN 6u 571 #define P18_6_NUM 6u 572 #define P18_6_AMUXSEGMENT AMUXBUS_MAIN 573 #define P18_7_PORT GPIO_PRT18 574 #define P18_7_PIN 7u 575 #define P18_7_NUM 7u 576 #define P18_7_AMUXSEGMENT AMUXBUS_MAIN 577 578 /* PORT 19 (GPIO) */ 579 #define P19_0_PORT GPIO_PRT19 580 #define P19_0_PIN 0u 581 #define P19_0_NUM 0u 582 #define P19_0_AMUXSEGMENT AMUXBUS_MAIN 583 #define P19_1_PORT GPIO_PRT19 584 #define P19_1_PIN 1u 585 #define P19_1_NUM 1u 586 #define P19_1_AMUXSEGMENT AMUXBUS_MAIN 587 #define P19_2_PORT GPIO_PRT19 588 #define P19_2_PIN 2u 589 #define P19_2_NUM 2u 590 #define P19_2_AMUXSEGMENT AMUXBUS_MAIN 591 #define P19_3_PORT GPIO_PRT19 592 #define P19_3_PIN 3u 593 #define P19_3_NUM 3u 594 #define P19_3_AMUXSEGMENT AMUXBUS_MAIN 595 #define P19_4_PORT GPIO_PRT19 596 #define P19_4_PIN 4u 597 #define P19_4_NUM 4u 598 #define P19_4_AMUXSEGMENT AMUXBUS_MAIN 599 #define P19_5_PORT GPIO_PRT19 600 #define P19_5_PIN 5u 601 #define P19_5_NUM 5u 602 #define P19_5_AMUXSEGMENT AMUXBUS_MAIN 603 #define P19_6_PORT GPIO_PRT19 604 #define P19_6_PIN 6u 605 #define P19_6_NUM 6u 606 #define P19_6_AMUXSEGMENT AMUXBUS_MAIN 607 #define P19_7_PORT GPIO_PRT19 608 #define P19_7_PIN 7u 609 #define P19_7_NUM 7u 610 #define P19_7_AMUXSEGMENT AMUXBUS_MAIN 611 612 /* PORT 20 (GPIO) */ 613 #define P20_0_PORT GPIO_PRT20 614 #define P20_0_PIN 0u 615 #define P20_0_NUM 0u 616 #define P20_0_AMUXSEGMENT AMUXBUS_MAIN 617 #define P20_1_PORT GPIO_PRT20 618 #define P20_1_PIN 1u 619 #define P20_1_NUM 1u 620 #define P20_1_AMUXSEGMENT AMUXBUS_MAIN 621 #define P20_2_PORT GPIO_PRT20 622 #define P20_2_PIN 2u 623 #define P20_2_NUM 2u 624 #define P20_2_AMUXSEGMENT AMUXBUS_MAIN 625 #define P20_3_PORT GPIO_PRT20 626 #define P20_3_PIN 3u 627 #define P20_3_NUM 3u 628 #define P20_3_AMUXSEGMENT AMUXBUS_MAIN 629 #define P20_4_PORT GPIO_PRT20 630 #define P20_4_PIN 4u 631 #define P20_4_NUM 4u 632 #define P20_4_AMUXSEGMENT AMUXBUS_MAIN 633 #define P20_5_PORT GPIO_PRT20 634 #define P20_5_PIN 5u 635 #define P20_5_NUM 5u 636 #define P20_5_AMUXSEGMENT AMUXBUS_MAIN 637 #define P20_6_PORT GPIO_PRT20 638 #define P20_6_PIN 6u 639 #define P20_6_NUM 6u 640 #define P20_6_AMUXSEGMENT AMUXBUS_MAIN 641 #define P20_7_PORT GPIO_PRT20 642 #define P20_7_PIN 7u 643 #define P20_7_NUM 7u 644 #define P20_7_AMUXSEGMENT AMUXBUS_MAIN 645 646 /* PORT 21 (GPIO) */ 647 #define P21_0_PORT GPIO_PRT21 648 #define P21_0_PIN 0u 649 #define P21_0_NUM 0u 650 #define P21_0_AMUXSEGMENT AMUXBUS_MAIN 651 #define P21_1_PORT GPIO_PRT21 652 #define P21_1_PIN 1u 653 #define P21_1_NUM 1u 654 #define P21_1_AMUXSEGMENT AMUXBUS_MAIN 655 #define P21_2_PORT GPIO_PRT21 656 #define P21_2_PIN 2u 657 #define P21_2_NUM 2u 658 #define P21_2_AMUXSEGMENT AMUXBUS_MAIN 659 #define P21_3_PORT GPIO_PRT21 660 #define P21_3_PIN 3u 661 #define P21_3_NUM 3u 662 #define P21_3_AMUXSEGMENT AMUXBUS_MAIN 663 664 /* PORT 23 (GPIO) */ 665 #define P23_0_PORT GPIO_PRT23 666 #define P23_0_PIN 0u 667 #define P23_0_NUM 0u 668 #define P23_0_AMUXSEGMENT AMUXBUS_MAIN 669 #define P23_1_PORT GPIO_PRT23 670 #define P23_1_PIN 1u 671 #define P23_1_NUM 1u 672 #define P23_1_AMUXSEGMENT AMUXBUS_MAIN 673 #define P23_2_PORT GPIO_PRT23 674 #define P23_2_PIN 2u 675 #define P23_2_NUM 2u 676 #define P23_2_AMUXSEGMENT AMUXBUS_MAIN 677 #define P23_3_PORT GPIO_PRT23 678 #define P23_3_PIN 3u 679 #define P23_3_NUM 3u 680 #define P23_3_AMUXSEGMENT AMUXBUS_MAIN 681 #define P23_4_PORT GPIO_PRT23 682 #define P23_4_PIN 4u 683 #define P23_4_NUM 4u 684 #define P23_4_AMUXSEGMENT AMUXBUS_MAIN 685 686 /* PORT 24 (GPIO) */ 687 #define P24_0_PORT GPIO_PRT24 688 #define P24_0_PIN 0u 689 #define P24_0_NUM 0u 690 #define P24_0_AMUXSEGMENT AMUXBUS_MAIN 691 #define P24_1_PORT GPIO_PRT24 692 #define P24_1_PIN 1u 693 #define P24_1_NUM 1u 694 #define P24_1_AMUXSEGMENT AMUXBUS_MAIN 695 696 /* PORT 25 (GPIO) */ 697 #define P25_0_PORT GPIO_PRT25 698 #define P25_0_PIN 0u 699 #define P25_0_NUM 0u 700 #define P25_0_AMUXSEGMENT AMUXBUS_MAIN 701 #define P25_1_PORT GPIO_PRT25 702 #define P25_1_PIN 1u 703 #define P25_1_NUM 1u 704 #define P25_1_AMUXSEGMENT AMUXBUS_MAIN 705 #define P25_2_PORT GPIO_PRT25 706 #define P25_2_PIN 2u 707 #define P25_2_NUM 2u 708 #define P25_2_AMUXSEGMENT AMUXBUS_MAIN 709 #define P25_3_PORT GPIO_PRT25 710 #define P25_3_PIN 3u 711 #define P25_3_NUM 3u 712 #define P25_3_AMUXSEGMENT AMUXBUS_MAIN 713 #define P25_4_PORT GPIO_PRT25 714 #define P25_4_PIN 4u 715 #define P25_4_NUM 4u 716 #define P25_4_AMUXSEGMENT AMUXBUS_MAIN 717 #define P25_5_PORT GPIO_PRT25 718 #define P25_5_PIN 5u 719 #define P25_5_NUM 5u 720 #define P25_5_AMUXSEGMENT AMUXBUS_MAIN 721 722 /* PORT 26 (GPIO) */ 723 #define P26_0_PORT GPIO_PRT26 724 #define P26_0_PIN 0u 725 #define P26_0_NUM 0u 726 #define P26_0_AMUXSEGMENT AMUXBUS_MAIN 727 #define P26_1_PORT GPIO_PRT26 728 #define P26_1_PIN 1u 729 #define P26_1_NUM 1u 730 #define P26_1_AMUXSEGMENT AMUXBUS_MAIN 731 #define P26_2_PORT GPIO_PRT26 732 #define P26_2_PIN 2u 733 #define P26_2_NUM 2u 734 #define P26_2_AMUXSEGMENT AMUXBUS_MAIN 735 #define P26_3_PORT GPIO_PRT26 736 #define P26_3_PIN 3u 737 #define P26_3_NUM 3u 738 #define P26_3_AMUXSEGMENT AMUXBUS_MAIN 739 #define P26_4_PORT GPIO_PRT26 740 #define P26_4_PIN 4u 741 #define P26_4_NUM 4u 742 #define P26_4_AMUXSEGMENT AMUXBUS_MAIN 743 744 /* PORT 27 (GPIO) */ 745 #define P27_0_PORT GPIO_PRT27 746 #define P27_0_PIN 0u 747 #define P27_0_NUM 0u 748 #define P27_0_AMUXSEGMENT AMUXBUS_MAIN 749 #define P27_1_PORT GPIO_PRT27 750 #define P27_1_PIN 1u 751 #define P27_1_NUM 1u 752 #define P27_1_AMUXSEGMENT AMUXBUS_MAIN 753 754 /* PORT 28 (GPIO) */ 755 #define P28_0_PORT GPIO_PRT28 756 #define P28_0_PIN 0u 757 #define P28_0_NUM 0u 758 #define P28_0_AMUXSEGMENT AMUXBUS_MAIN 759 #define P28_1_PORT GPIO_PRT28 760 #define P28_1_PIN 1u 761 #define P28_1_NUM 1u 762 #define P28_1_AMUXSEGMENT AMUXBUS_MAIN 763 #define P28_2_PORT GPIO_PRT28 764 #define P28_2_PIN 2u 765 #define P28_2_NUM 2u 766 #define P28_2_AMUXSEGMENT AMUXBUS_MAIN 767 #define P28_3_PORT GPIO_PRT28 768 #define P28_3_PIN 3u 769 #define P28_3_NUM 3u 770 #define P28_3_AMUXSEGMENT AMUXBUS_MAIN 771 #define P28_4_PORT GPIO_PRT28 772 #define P28_4_PIN 4u 773 #define P28_4_NUM 4u 774 #define P28_4_AMUXSEGMENT AMUXBUS_MAIN 775 #define P28_5_PORT GPIO_PRT28 776 #define P28_5_PIN 5u 777 #define P28_5_NUM 5u 778 #define P28_5_AMUXSEGMENT AMUXBUS_MAIN 779 780 /* PORT 29 (GPIO) */ 781 #define P29_0_PORT GPIO_PRT29 782 #define P29_0_PIN 0u 783 #define P29_0_NUM 0u 784 #define P29_0_AMUXSEGMENT AMUXBUS_MAIN 785 #define P29_1_PORT GPIO_PRT29 786 #define P29_1_PIN 1u 787 #define P29_1_NUM 1u 788 #define P29_1_AMUXSEGMENT AMUXBUS_MAIN 789 790 /* PORT 30 (GPIO) */ 791 #define P30_0_PORT GPIO_PRT30 792 #define P30_0_PIN 0u 793 #define P30_0_NUM 0u 794 #define P30_0_AMUXSEGMENT AMUXBUS_MAIN 795 #define P30_1_PORT GPIO_PRT30 796 #define P30_1_PIN 1u 797 #define P30_1_NUM 1u 798 #define P30_1_AMUXSEGMENT AMUXBUS_MAIN 799 800 /* Analog Connections */ 801 #define PASS0_I_TEMP_KELVIN_PORT 1u 802 #define PASS0_I_TEMP_KELVIN_PIN 0u 803 #define PASS0_SARMUX_PADS0_PORT 5u 804 #define PASS0_SARMUX_PADS0_PIN 6u 805 #define PASS0_SARMUX_PADS1_PORT 5u 806 #define PASS0_SARMUX_PADS1_PIN 7u 807 #define PASS0_SARMUX_PADS10_PORT 7u 808 #define PASS0_SARMUX_PADS10_PIN 0u 809 #define PASS0_SARMUX_PADS11_PORT 7u 810 #define PASS0_SARMUX_PADS11_PIN 1u 811 #define PASS0_SARMUX_PADS12_PORT 7u 812 #define PASS0_SARMUX_PADS12_PIN 2u 813 #define PASS0_SARMUX_PADS13_PORT 7u 814 #define PASS0_SARMUX_PADS13_PIN 3u 815 #define PASS0_SARMUX_PADS14_PORT 7u 816 #define PASS0_SARMUX_PADS14_PIN 4u 817 #define PASS0_SARMUX_PADS15_PORT 7u 818 #define PASS0_SARMUX_PADS15_PIN 5u 819 #define PASS0_SARMUX_PADS16_PORT 7u 820 #define PASS0_SARMUX_PADS16_PIN 6u 821 #define PASS0_SARMUX_PADS17_PORT 7u 822 #define PASS0_SARMUX_PADS17_PIN 7u 823 #define PASS0_SARMUX_PADS18_PORT 29u 824 #define PASS0_SARMUX_PADS18_PIN 0u 825 #define PASS0_SARMUX_PADS19_PORT 29u 826 #define PASS0_SARMUX_PADS19_PIN 1u 827 #define PASS0_SARMUX_PADS2_PORT 6u 828 #define PASS0_SARMUX_PADS2_PIN 0u 829 #define PASS0_SARMUX_PADS20_PORT 8u 830 #define PASS0_SARMUX_PADS20_PIN 0u 831 #define PASS0_SARMUX_PADS21_PORT 8u 832 #define PASS0_SARMUX_PADS21_PIN 1u 833 #define PASS0_SARMUX_PADS22_PORT 8u 834 #define PASS0_SARMUX_PADS22_PIN 2u 835 #define PASS0_SARMUX_PADS23_PORT 8u 836 #define PASS0_SARMUX_PADS23_PIN 3u 837 #define PASS0_SARMUX_PADS3_PORT 6u 838 #define PASS0_SARMUX_PADS3_PIN 1u 839 #define PASS0_SARMUX_PADS32_PORT 9u 840 #define PASS0_SARMUX_PADS32_PIN 0u 841 #define PASS0_SARMUX_PADS33_PORT 9u 842 #define PASS0_SARMUX_PADS33_PIN 1u 843 #define PASS0_SARMUX_PADS34_PORT 9u 844 #define PASS0_SARMUX_PADS34_PIN 2u 845 #define PASS0_SARMUX_PADS35_PORT 9u 846 #define PASS0_SARMUX_PADS35_PIN 3u 847 #define PASS0_SARMUX_PADS36_PORT 9u 848 #define PASS0_SARMUX_PADS36_PIN 4u 849 #define PASS0_SARMUX_PADS37_PORT 9u 850 #define PASS0_SARMUX_PADS37_PIN 5u 851 #define PASS0_SARMUX_PADS38_PORT 9u 852 #define PASS0_SARMUX_PADS38_PIN 6u 853 #define PASS0_SARMUX_PADS39_PORT 9u 854 #define PASS0_SARMUX_PADS39_PIN 7u 855 #define PASS0_SARMUX_PADS4_PORT 6u 856 #define PASS0_SARMUX_PADS4_PIN 2u 857 #define PASS0_SARMUX_PADS40_PORT 11u 858 #define PASS0_SARMUX_PADS40_PIN 0u 859 #define PASS0_SARMUX_PADS41_PORT 11u 860 #define PASS0_SARMUX_PADS41_PIN 1u 861 #define PASS0_SARMUX_PADS42_PORT 11u 862 #define PASS0_SARMUX_PADS42_PIN 2u 863 #define PASS0_SARMUX_PADS43_PORT 11u 864 #define PASS0_SARMUX_PADS43_PIN 3u 865 #define PASS0_SARMUX_PADS44_PORT 11u 866 #define PASS0_SARMUX_PADS44_PIN 4u 867 #define PASS0_SARMUX_PADS45_PORT 11u 868 #define PASS0_SARMUX_PADS45_PIN 5u 869 #define PASS0_SARMUX_PADS46_PORT 11u 870 #define PASS0_SARMUX_PADS46_PIN 6u 871 #define PASS0_SARMUX_PADS47_PORT 11u 872 #define PASS0_SARMUX_PADS47_PIN 7u 873 #define PASS0_SARMUX_PADS48_PORT 12u 874 #define PASS0_SARMUX_PADS48_PIN 0u 875 #define PASS0_SARMUX_PADS49_PORT 12u 876 #define PASS0_SARMUX_PADS49_PIN 1u 877 #define PASS0_SARMUX_PADS5_PORT 6u 878 #define PASS0_SARMUX_PADS5_PIN 3u 879 #define PASS0_SARMUX_PADS50_PORT 12u 880 #define PASS0_SARMUX_PADS50_PIN 2u 881 #define PASS0_SARMUX_PADS51_PORT 12u 882 #define PASS0_SARMUX_PADS51_PIN 3u 883 #define PASS0_SARMUX_PADS52_PORT 12u 884 #define PASS0_SARMUX_PADS52_PIN 4u 885 #define PASS0_SARMUX_PADS53_PORT 12u 886 #define PASS0_SARMUX_PADS53_PIN 5u 887 #define PASS0_SARMUX_PADS54_PORT 12u 888 #define PASS0_SARMUX_PADS54_PIN 6u 889 #define PASS0_SARMUX_PADS55_PORT 12u 890 #define PASS0_SARMUX_PADS55_PIN 7u 891 #define PASS0_SARMUX_PADS6_PORT 6u 892 #define PASS0_SARMUX_PADS6_PIN 4u 893 #define PASS0_SARMUX_PADS7_PORT 6u 894 #define PASS0_SARMUX_PADS7_PIN 5u 895 #define PASS0_SARMUX_PADS8_PORT 6u 896 #define PASS0_SARMUX_PADS8_PIN 6u 897 #define PASS0_SARMUX_PADS9_PORT 6u 898 #define PASS0_SARMUX_PADS9_PIN 7u 899 #define PASS0_VB_TEMP_KELVIN_PORT 2u 900 #define PASS0_VB_TEMP_KELVIN_PIN 6u 901 #define PASS0_VE_TEMP_KELVIN_PORT 29u 902 #define PASS0_VE_TEMP_KELVIN_PIN 1u 903 #define SRSS_ADFT_PIN0_PORT 2u 904 #define SRSS_ADFT_PIN0_PIN 5u 905 #define SRSS_ADFT_PIN1_PORT 2u 906 #define SRSS_ADFT_PIN1_PIN 6u 907 #define SRSS_ADFT_POR_PAD_HV_PORT 3u 908 #define SRSS_ADFT_POR_PAD_HV_PIN 1u 909 #define SRSS_ECO_IN_PORT 1u 910 #define SRSS_ECO_IN_PIN 0u 911 #define SRSS_ECO_OUT_PORT 1u 912 #define SRSS_ECO_OUT_PIN 1u 913 #define SRSS_LPECO_IN_PORT 1u 914 #define SRSS_LPECO_IN_PIN 4u 915 #define SRSS_LPECO_OUT_PORT 1u 916 #define SRSS_LPECO_OUT_PIN 5u 917 #define SRSS_VEXT_REF_REG_PORT 1u 918 #define SRSS_VEXT_REF_REG_PIN 1u 919 #define SRSS_WCO_IN_PORT 1u 920 #define SRSS_WCO_IN_PIN 4u 921 #define SRSS_WCO_OUT_PORT 1u 922 #define SRSS_WCO_OUT_PIN 5u 923 924 /* HSIOM Connections */ 925 typedef enum 926 { 927 /* Generic HSIOM connections */ 928 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 929 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 930 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 931 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 932 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 933 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 934 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 935 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 936 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 937 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 938 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 939 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 940 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 941 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 942 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 943 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 944 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 945 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 946 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 947 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 948 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 949 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 950 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 951 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 952 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 953 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 954 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 955 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 956 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 957 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 958 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 959 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 960 961 /* P0.0 */ 962 P0_0_GPIO = 0, /* GPIO controls 'out' */ 963 P0_0_AMUXA = 4, /* Analog mux bus A */ 964 P0_0_AMUXB = 5, /* Analog mux bus B */ 965 P0_0_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:0 */ 966 P0_0_TDM0_TDM_TX_MCK2 = 16, /* Digital Active - tdm[0].tdm_tx_mck[2]:0 */ 967 P0_0_TDM0_TDM_RX_MCK2 = 17, /* Digital Active - tdm[0].tdm_rx_mck[2]:0 */ 968 P0_0_LIN0_LIN_TX1 = 23, /* Digital Active - lin[0].lin_tx[1]:0 */ 969 P0_0_SCB10_SPI_CLK = 25, /* Digital Active - scb[10].spi_clk:0 */ 970 P0_0_SCB10_UART_RX = 26, /* Digital Active - scb[10].uart_rx:0 */ 971 P0_0_SCB10_I2C_SDA = 27, /* Digital Active - scb[10].i2c_sda:0 */ 972 973 /* P0.1 */ 974 P0_1_GPIO = 0, /* GPIO controls 'out' */ 975 P0_1_AMUXA = 4, /* Analog mux bus A */ 976 P0_1_AMUXB = 5, /* Analog mux bus B */ 977 P0_1_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:0 */ 978 P0_1_TCPWM0_TR_ONE_CNT_IN20 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[20]:0 */ 979 P0_1_TDM0_TDM_TX_SCK2 = 16, /* Digital Active - tdm[0].tdm_tx_sck[2]:0 */ 980 P0_1_TDM0_TDM_RX_SCK2 = 17, /* Digital Active - tdm[0].tdm_rx_sck[2]:0 */ 981 P0_1_LIN0_LIN_RX1 = 23, /* Digital Active - lin[0].lin_rx[1]:0 */ 982 P0_1_SCB10_SPI_MOSI = 25, /* Digital Active - scb[10].spi_mosi:0 */ 983 P0_1_SCB10_UART_TX = 26, /* Digital Active - scb[10].uart_tx:0 */ 984 P0_1_SCB10_I2C_SCL = 27, /* Digital Active - scb[10].i2c_scl:0 */ 985 986 /* P0.2 */ 987 P0_2_GPIO = 0, /* GPIO controls 'out' */ 988 P0_2_AMUXA = 4, /* Analog mux bus A */ 989 P0_2_AMUXB = 5, /* Analog mux bus B */ 990 P0_2_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:0 */ 991 P0_2_TDM0_TDM_TX_FSYNC2 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[2]:0 */ 992 P0_2_TDM0_TDM_RX_FSYNC2 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[2]:0 */ 993 P0_2_CXPI0_CXPI_TX1 = 24, /* Digital Active - cxpi[0].cxpi_tx[1]:0 */ 994 P0_2_SCB10_SPI_MISO = 25, /* Digital Active - scb[10].spi_miso:0 */ 995 P0_2_SCB10_UART_RTS = 26, /* Digital Active - scb[10].uart_rts:0 */ 996 P0_2_SCB0_I2C_SDA = 30, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 997 998 /* P0.3 */ 999 P0_3_GPIO = 0, /* GPIO controls 'out' */ 1000 P0_3_AMUXA = 4, /* Analog mux bus A */ 1001 P0_3_AMUXB = 5, /* Analog mux bus B */ 1002 P0_3_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:0 */ 1003 P0_3_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:0 */ 1004 P0_3_TDM0_TDM_TX_SD2 = 16, /* Digital Active - tdm[0].tdm_tx_sd[2]:0 */ 1005 P0_3_TDM0_TDM_RX_SD2 = 17, /* Digital Active - tdm[0].tdm_rx_sd[2]:0 */ 1006 P0_3_CXPI0_CXPI_RX1 = 24, /* Digital Active - cxpi[0].cxpi_rx[1]:0 */ 1007 P0_3_SCB10_SPI_SELECT0 = 25, /* Digital Active - scb[10].spi_select0:0 */ 1008 P0_3_SCB10_UART_CTS = 26, /* Digital Active - scb[10].uart_cts:0 */ 1009 P0_3_SCB0_I2C_SCL = 30, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 1010 1011 /* P0.4 */ 1012 P0_4_GPIO = 0, /* GPIO controls 'out' */ 1013 P0_4_AMUXA = 4, /* Analog mux bus A */ 1014 P0_4_AMUXB = 5, /* Analog mux bus B */ 1015 P0_4_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:0 */ 1016 P0_4_SCB11_SPI_CLK = 25, /* Digital Active - scb[11].spi_clk:0 */ 1017 P0_4_SCB11_UART_RX = 26, /* Digital Active - scb[11].uart_rx:0 */ 1018 P0_4_SCB11_I2C_SDA = 27, /* Digital Active - scb[11].i2c_sda:0 */ 1019 1020 /* P0.5 */ 1021 P0_5_GPIO = 0, /* GPIO controls 'out' */ 1022 P0_5_AMUXA = 4, /* Analog mux bus A */ 1023 P0_5_AMUXB = 5, /* Analog mux bus B */ 1024 P0_5_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:0 */ 1025 P0_5_TCPWM0_TR_ONE_CNT_IN22 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:0 */ 1026 P0_5_SCB11_SPI_MOSI = 25, /* Digital Active - scb[11].spi_mosi:0 */ 1027 P0_5_SCB11_UART_TX = 26, /* Digital Active - scb[11].uart_tx:0 */ 1028 P0_5_SCB11_I2C_SCL = 27, /* Digital Active - scb[11].i2c_scl:0 */ 1029 1030 /* P1.0 */ 1031 P1_0_GPIO = 0, /* GPIO controls 'out' */ 1032 P1_0_AMUXA = 4, /* Analog mux bus A */ 1033 P1_0_AMUXB = 5, /* Analog mux bus B */ 1034 P1_0_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:0 */ 1035 P1_0_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1036 1037 /* P1.1 */ 1038 P1_1_GPIO = 0, /* GPIO controls 'out' */ 1039 P1_1_AMUXA = 4, /* Analog mux bus A */ 1040 P1_1_AMUXB = 5, /* Analog mux bus B */ 1041 1042 /* P1.4 */ 1043 P1_4_GPIO = 0, /* GPIO controls 'out' */ 1044 P1_4_AMUXA = 4, /* Analog mux bus A */ 1045 P1_4_AMUXB = 5, /* Analog mux bus B */ 1046 1047 /* P1.5 */ 1048 P1_5_GPIO = 0, /* GPIO controls 'out' */ 1049 P1_5_AMUXA = 4, /* Analog mux bus A */ 1050 P1_5_AMUXB = 5, /* Analog mux bus B */ 1051 1052 /* P2.3 */ 1053 P2_3_GPIO = 0, /* GPIO controls 'out' */ 1054 P2_3_AMUXA = 4, /* Analog mux bus A */ 1055 P2_3_AMUXB = 5, /* Analog mux bus B */ 1056 P2_3_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:0 */ 1057 P2_3_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:0 */ 1058 P2_3_CXPI0_CXPI_EN0 = 21, /* Digital Active - cxpi[0].cxpi_en[0]:0 */ 1059 P2_3_LIN0_LIN_EN0 = 23, /* Digital Active - lin[0].lin_en[0]:0 */ 1060 P2_3_CANFD1_TTCAN_TX0 = 25, /* Digital Active - canfd[1].ttcan_tx[0]:1 */ 1061 P2_3_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:1 */ 1062 P2_3_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:1 */ 1063 1064 /* P2.4 */ 1065 P2_4_GPIO = 0, /* GPIO controls 'out' */ 1066 P2_4_AMUXA = 4, /* Analog mux bus A */ 1067 P2_4_AMUXB = 5, /* Analog mux bus B */ 1068 P2_4_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:0 */ 1069 P2_4_CXPI0_CXPI_RX0 = 21, /* Digital Active - cxpi[0].cxpi_rx[0]:0 */ 1070 P2_4_LIN0_LIN_RX0 = 23, /* Digital Active - lin[0].lin_rx[0]:0 */ 1071 P2_4_CANFD1_TTCAN_RX0 = 25, /* Digital Active - canfd[1].ttcan_rx[0]:1 */ 1072 P2_4_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn:0 */ 1073 1074 /* P2.5 */ 1075 P2_5_GPIO = 0, /* GPIO controls 'out' */ 1076 P2_5_AMUXA = 4, /* Analog mux bus A */ 1077 P2_5_AMUXB = 5, /* Analog mux bus B */ 1078 P2_5_DAC0_DAC_MCK = 24, /* Digital Active - dac[0].dac_mck:0 */ 1079 P2_5_PERI_TR_IO_INPUT0 = 27, /* Digital Active - peri.tr_io_input[0]:1 */ 1080 P2_5_SRSS_CAL_WAVE = 29, /* Digital Deep Sleep - srss.cal_wave:0 */ 1081 P2_5_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1082 1083 /* P2.6 */ 1084 P2_6_GPIO = 0, /* GPIO controls 'out' */ 1085 P2_6_AMUXA = 4, /* Analog mux bus A */ 1086 P2_6_AMUXB = 5, /* Analog mux bus B */ 1087 P2_6_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo:0 */ 1088 P2_6_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1089 1090 /* P3.0 */ 1091 P3_0_GPIO = 0, /* GPIO controls 'out' */ 1092 P3_0_AMUXA = 4, /* Analog mux bus A */ 1093 P3_0_AMUXB = 5, /* Analog mux bus B */ 1094 P3_0_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:0 */ 1095 P3_0_TCPWM0_TR_ONE_CNT_IN25 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:0 */ 1096 P3_0_CXPI0_CXPI_TX0 = 21, /* Digital Active - cxpi[0].cxpi_tx[0]:0 */ 1097 P3_0_LIN0_LIN_TX0 = 23, /* Digital Active - lin[0].lin_tx[0]:0 */ 1098 P3_0_CANFD0_TTCAN_TX0 = 25, /* Digital Active - canfd[0].ttcan_tx[0]:0 */ 1099 P3_0_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk:0 */ 1100 1101 /* P3.1 */ 1102 P3_1_GPIO = 0, /* GPIO controls 'out' */ 1103 P3_1_AMUXA = 4, /* Analog mux bus A */ 1104 P3_1_AMUXB = 5, /* Analog mux bus B */ 1105 P3_1_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:0 */ 1106 P3_1_CANFD0_TTCAN_RX0 = 25, /* Digital Active - canfd[0].ttcan_rx[0]:0 */ 1107 1108 /* P3.2 */ 1109 P3_2_GPIO = 0, /* GPIO controls 'out' */ 1110 P3_2_AMUXA = 4, /* Analog mux bus A */ 1111 P3_2_AMUXB = 5, /* Analog mux bus B */ 1112 P3_2_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:0 */ 1113 P3_2_TCPWM0_TR_ONE_CNT_IN26 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[26]:0 */ 1114 P3_2_CANFD0_TTCAN_TX1 = 25, /* Digital Active - canfd[0].ttcan_tx[1]:0 */ 1115 P3_2_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms:0 */ 1116 1117 /* P3.3 */ 1118 P3_3_GPIO = 0, /* GPIO controls 'out' */ 1119 P3_3_AMUXA = 4, /* Analog mux bus A */ 1120 P3_3_AMUXB = 5, /* Analog mux bus B */ 1121 P3_3_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:0 */ 1122 P3_3_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:1 */ 1123 P3_3_CANFD0_TTCAN_RX1 = 25, /* Digital Active - canfd[0].ttcan_rx[1]:0 */ 1124 P3_3_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi:0 */ 1125 P3_3_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1126 1127 /* P3.4 */ 1128 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1129 P3_4_AMUXA = 4, /* Analog mux bus A */ 1130 P3_4_AMUXB = 5, /* Analog mux bus B */ 1131 P3_4_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:0 */ 1132 P3_4_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:0 */ 1133 P3_4_LIN0_LIN_EN1 = 23, /* Digital Active - lin[0].lin_en[1]:0 */ 1134 P3_4_CXPI0_CXPI_EN1 = 24, /* Digital Active - cxpi[0].cxpi_en[1]:0 */ 1135 P3_4_SCB10_SPI_SELECT1 = 25, /* Digital Active - scb[10].spi_select1:0 */ 1136 P3_4_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:0 */ 1137 1138 /* P4.0 */ 1139 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1140 P4_0_AMUXA = 4, /* Analog mux bus A */ 1141 P4_0_AMUXB = 5, /* Analog mux bus B */ 1142 P4_0_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:0 */ 1143 P4_0_SG0_SG_AMPL0 = 22, /* Digital Active - sg[0].sg_ampl[0]:1 */ 1144 P4_0_PWM0_PWM_LINE1_P0 = 24, /* Digital Active - pwm[0].pwm_line1_p[0]:0 */ 1145 P4_0_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:0 */ 1146 1147 /* P4.1 */ 1148 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1149 P4_1_AMUXA = 4, /* Analog mux bus A */ 1150 P4_1_AMUXB = 5, /* Analog mux bus B */ 1151 P4_1_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:0 */ 1152 P4_1_TCPWM0_TR_ONE_CNT_IN28 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:0 */ 1153 P4_1_SG0_SG_TONE0 = 22, /* Digital Active - sg[0].sg_tone[0]:1 */ 1154 P4_1_PWM0_PWM_LINE1_N0 = 24, /* Digital Active - pwm[0].pwm_line1_n[0]:0 */ 1155 P4_1_CPUSS_FAULT_OUT2 = 27, /* Digital Active - cpuss.fault_out[2]:0 */ 1156 1157 /* P4.2 */ 1158 P4_2_GPIO = 0, /* GPIO controls 'out' */ 1159 P4_2_AMUXA = 4, /* Analog mux bus A */ 1160 P4_2_AMUXB = 5, /* Analog mux bus B */ 1161 P4_2_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:0 */ 1162 P4_2_SG0_SG_AMPL1 = 22, /* Digital Active - sg[0].sg_ampl[1]:1 */ 1163 P4_2_PWM0_PWM_LINE2_P0 = 24, /* Digital Active - pwm[0].pwm_line2_p[0]:0 */ 1164 P4_2_CPUSS_FAULT_OUT3 = 27, /* Digital Active - cpuss.fault_out[3]:0 */ 1165 1166 /* P4.3 */ 1167 P4_3_GPIO = 0, /* GPIO controls 'out' */ 1168 P4_3_AMUXA = 4, /* Analog mux bus A */ 1169 P4_3_AMUXB = 5, /* Analog mux bus B */ 1170 P4_3_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:0 */ 1171 P4_3_TCPWM0_TR_ONE_CNT_IN29 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[29]:0 */ 1172 P4_3_SG0_SG_TONE1 = 22, /* Digital Active - sg[0].sg_tone[1]:1 */ 1173 P4_3_PWM0_PWM_LINE2_N0 = 24, /* Digital Active - pwm[0].pwm_line2_n[0]:0 */ 1174 1175 /* P4.4 */ 1176 P4_4_GPIO = 0, /* GPIO controls 'out' */ 1177 P4_4_AMUXA = 4, /* Analog mux bus A */ 1178 P4_4_AMUXB = 5, /* Analog mux bus B */ 1179 P4_4_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:0 */ 1180 P4_4_TDM0_TDM_TX_MCK3 = 16, /* Digital Active - tdm[0].tdm_tx_mck[3]:0 */ 1181 P4_4_TDM0_TDM_RX_MCK3 = 17, /* Digital Active - tdm[0].tdm_rx_mck[3]:0 */ 1182 P4_4_CXPI0_CXPI_EN0 = 21, /* Digital Active - cxpi[0].cxpi_en[0]:1 */ 1183 P4_4_SG0_SG_AMPL2 = 22, /* Digital Active - sg[0].sg_ampl[2]:1 */ 1184 P4_4_LIN0_LIN_EN0 = 23, /* Digital Active - lin[0].lin_en[0]:1 */ 1185 P4_4_PWM0_PWM_LINE1_P1 = 24, /* Digital Active - pwm[0].pwm_line1_p[1]:0 */ 1186 1187 /* P4.5 */ 1188 P4_5_GPIO = 0, /* GPIO controls 'out' */ 1189 P4_5_AMUXA = 4, /* Analog mux bus A */ 1190 P4_5_AMUXB = 5, /* Analog mux bus B */ 1191 P4_5_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:0 */ 1192 P4_5_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:0 */ 1193 P4_5_TDM0_TDM_TX_SCK3 = 16, /* Digital Active - tdm[0].tdm_tx_sck[3]:0 */ 1194 P4_5_TDM0_TDM_RX_SCK3 = 17, /* Digital Active - tdm[0].tdm_rx_sck[3]:0 */ 1195 P4_5_CXPI0_CXPI_RX0 = 21, /* Digital Active - cxpi[0].cxpi_rx[0]:1 */ 1196 P4_5_SG0_SG_TONE2 = 22, /* Digital Active - sg[0].sg_tone[2]:1 */ 1197 P4_5_LIN0_LIN_RX0 = 23, /* Digital Active - lin[0].lin_rx[0]:1 */ 1198 P4_5_PWM0_PWM_LINE1_N1 = 24, /* Digital Active - pwm[0].pwm_line1_n[1]:0 */ 1199 1200 /* P4.6 */ 1201 P4_6_GPIO = 0, /* GPIO controls 'out' */ 1202 P4_6_AMUXA = 4, /* Analog mux bus A */ 1203 P4_6_AMUXB = 5, /* Analog mux bus B */ 1204 P4_6_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:0 */ 1205 P4_6_TDM0_TDM_TX_FSYNC3 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[3]:0 */ 1206 P4_6_TDM0_TDM_RX_FSYNC3 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[3]:0 */ 1207 P4_6_CXPI0_CXPI_TX0 = 21, /* Digital Active - cxpi[0].cxpi_tx[0]:1 */ 1208 P4_6_SG0_SG_AMPL3 = 22, /* Digital Active - sg[0].sg_ampl[3]:1 */ 1209 P4_6_LIN0_LIN_TX0 = 23, /* Digital Active - lin[0].lin_tx[0]:1 */ 1210 P4_6_PWM0_PWM_LINE2_P1 = 24, /* Digital Active - pwm[0].pwm_line2_p[1]:0 */ 1211 1212 /* P4.7 */ 1213 P4_7_GPIO = 0, /* GPIO controls 'out' */ 1214 P4_7_AMUXA = 4, /* Analog mux bus A */ 1215 P4_7_AMUXB = 5, /* Analog mux bus B */ 1216 P4_7_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:0 */ 1217 P4_7_TCPWM0_TR_ONE_CNT_IN31 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:0 */ 1218 P4_7_TDM0_TDM_TX_SD3 = 16, /* Digital Active - tdm[0].tdm_tx_sd[3]:0 */ 1219 P4_7_TDM0_TDM_RX_SD3 = 17, /* Digital Active - tdm[0].tdm_rx_sd[3]:0 */ 1220 P4_7_SG0_SG_TONE3 = 22, /* Digital Active - sg[0].sg_tone[3]:1 */ 1221 P4_7_PWM0_PWM_LINE2_N1 = 24, /* Digital Active - pwm[0].pwm_line2_n[1]:0 */ 1222 1223 /* P5.0 */ 1224 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1225 P5_0_AMUXA = 4, /* Analog mux bus A */ 1226 P5_0_AMUXB = 5, /* Analog mux bus B */ 1227 P5_0_TCPWM0_LINE524 = 8, /* Digital Active - tcpwm[0].line[524]:0 */ 1228 P5_0_TCPWM0_LINE_COMPL529 = 9, /* Digital Active - tcpwm[0].line_compl[529]:0 */ 1229 P5_0_TCPWM0_TR_ONE_CNT_IN528 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[528]:0 */ 1230 P5_0_TDM0_TDM_TX_MCK2 = 16, /* Digital Active - tdm[0].tdm_tx_mck[2]:1 */ 1231 P5_0_TDM0_TDM_RX_MCK2 = 17, /* Digital Active - tdm[0].tdm_rx_mck[2]:1 */ 1232 P5_0_VIDEOSS0_TTL_DSP0_DATA_A03 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[3]:0 */ 1233 P5_0_CANFD0_TTCAN_TX0 = 25, /* Digital Active - canfd[0].ttcan_tx[0]:1 */ 1234 1235 /* P5.1 */ 1236 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1237 P5_1_AMUXA = 4, /* Analog mux bus A */ 1238 P5_1_AMUXB = 5, /* Analog mux bus B */ 1239 P5_1_TCPWM0_LINE525 = 8, /* Digital Active - tcpwm[0].line[525]:0 */ 1240 P5_1_TCPWM0_LINE_COMPL524 = 9, /* Digital Active - tcpwm[0].line_compl[524]:0 */ 1241 P5_1_TCPWM0_TR_ONE_CNT_IN529 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[529]:0 */ 1242 P5_1_TDM0_TDM_TX_SCK2 = 16, /* Digital Active - tdm[0].tdm_tx_sck[2]:1 */ 1243 P5_1_TDM0_TDM_RX_SCK2 = 17, /* Digital Active - tdm[0].tdm_rx_sck[2]:1 */ 1244 P5_1_VIDEOSS0_TTL_DSP0_DATA_A13 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[3]:0 */ 1245 P5_1_CANFD0_TTCAN_RX0 = 25, /* Digital Active - canfd[0].ttcan_rx[0]:1 */ 1246 1247 /* P5.2 */ 1248 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1249 P5_2_AMUXA = 4, /* Analog mux bus A */ 1250 P5_2_AMUXB = 5, /* Analog mux bus B */ 1251 P5_2_TCPWM0_LINE526 = 8, /* Digital Active - tcpwm[0].line[526]:0 */ 1252 P5_2_TCPWM0_LINE_COMPL525 = 9, /* Digital Active - tcpwm[0].line_compl[525]:0 */ 1253 P5_2_TCPWM0_TR_ONE_CNT_IN524 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[524]:0 */ 1254 P5_2_TDM0_TDM_TX_FSYNC2 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[2]:1 */ 1255 P5_2_TDM0_TDM_RX_FSYNC2 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[2]:1 */ 1256 P5_2_SG0_SG_AMPL0 = 22, /* Digital Active - sg[0].sg_ampl[0]:0 */ 1257 P5_2_VIDEOSS0_TTL_DSP0_DATA_A04 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[4]:0 */ 1258 P5_2_CANFD0_TTCAN_TX1 = 25, /* Digital Active - canfd[0].ttcan_tx[1]:1 */ 1259 1260 /* P5.3 */ 1261 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1262 P5_3_AMUXA = 4, /* Analog mux bus A */ 1263 P5_3_AMUXB = 5, /* Analog mux bus B */ 1264 P5_3_TCPWM0_LINE527 = 8, /* Digital Active - tcpwm[0].line[527]:0 */ 1265 P5_3_TCPWM0_LINE_COMPL526 = 9, /* Digital Active - tcpwm[0].line_compl[526]:0 */ 1266 P5_3_TCPWM0_TR_ONE_CNT_IN525 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[525]:0 */ 1267 P5_3_TDM0_TDM_TX_SD2 = 16, /* Digital Active - tdm[0].tdm_tx_sd[2]:1 */ 1268 P5_3_TDM0_TDM_RX_SD2 = 17, /* Digital Active - tdm[0].tdm_rx_sd[2]:1 */ 1269 P5_3_SG0_SG_TONE0 = 22, /* Digital Active - sg[0].sg_tone[0]:0 */ 1270 P5_3_VIDEOSS0_TTL_DSP0_DATA_A14 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[4]:0 */ 1271 P5_3_CANFD0_TTCAN_RX1 = 25, /* Digital Active - canfd[0].ttcan_rx[1]:1 */ 1272 1273 /* P5.4 */ 1274 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1275 P5_4_AMUXA = 4, /* Analog mux bus A */ 1276 P5_4_AMUXB = 5, /* Analog mux bus B */ 1277 P5_4_TCPWM0_LINE528 = 8, /* Digital Active - tcpwm[0].line[528]:0 */ 1278 P5_4_TCPWM0_LINE_COMPL527 = 9, /* Digital Active - tcpwm[0].line_compl[527]:0 */ 1279 P5_4_TCPWM0_TR_ONE_CNT_IN526 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[526]:0 */ 1280 P5_4_VIDEOSS0_TTL_DSP0_DATA_A05 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[5]:0 */ 1281 P5_4_CANFD1_TTCAN_TX1 = 25, /* Digital Active - canfd[1].ttcan_tx[1]:1 */ 1282 1283 /* P5.5 */ 1284 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1285 P5_5_AMUXA = 4, /* Analog mux bus A */ 1286 P5_5_AMUXB = 5, /* Analog mux bus B */ 1287 P5_5_TCPWM0_LINE529 = 8, /* Digital Active - tcpwm[0].line[529]:0 */ 1288 P5_5_TCPWM0_LINE_COMPL528 = 9, /* Digital Active - tcpwm[0].line_compl[528]:0 */ 1289 P5_5_TCPWM0_TR_ONE_CNT_IN527 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[527]:0 */ 1290 P5_5_VIDEOSS0_TTL_DSP0_DATA_A15 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[5]:0 */ 1291 P5_5_CANFD1_TTCAN_RX1 = 25, /* Digital Active - canfd[1].ttcan_rx[1]:1 */ 1292 1293 /* P5.6 */ 1294 P5_6_GPIO = 0, /* GPIO controls 'out' */ 1295 P5_6_AMUXA = 4, /* Analog mux bus A */ 1296 P5_6_AMUXB = 5, /* Analog mux bus B */ 1297 P5_6_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:1 */ 1298 P5_6_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:1 */ 1299 P5_6_TCPWM0_TR_ONE_CNT_IN28 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:1 */ 1300 P5_6_TDM0_TDM_TX_MCK3 = 16, /* Digital Active - tdm[0].tdm_tx_mck[3]:1 */ 1301 P5_6_TDM0_TDM_RX_MCK3 = 17, /* Digital Active - tdm[0].tdm_rx_mck[3]:1 */ 1302 P5_6_VIDEOSS0_TTL_DSP0_DATA_A06 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[6]:0 */ 1303 P5_6_SCB8_SPI_CLK = 25, /* Digital Active - scb[8].spi_clk:0 */ 1304 P5_6_SCB8_UART_RX = 26, /* Digital Active - scb[8].uart_rx:0 */ 1305 P5_6_SCB8_I2C_SDA = 27, /* Digital Active - scb[8].i2c_sda:0 */ 1306 1307 /* P5.7 */ 1308 P5_7_GPIO = 0, /* GPIO controls 'out' */ 1309 P5_7_AMUXA = 4, /* Analog mux bus A */ 1310 P5_7_AMUXB = 5, /* Analog mux bus B */ 1311 P5_7_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:1 */ 1312 P5_7_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:1 */ 1313 P5_7_TCPWM0_TR_ONE_CNT_IN29 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[29]:1 */ 1314 P5_7_TDM0_TDM_TX_SCK3 = 16, /* Digital Active - tdm[0].tdm_tx_sck[3]:1 */ 1315 P5_7_TDM0_TDM_RX_SCK3 = 17, /* Digital Active - tdm[0].tdm_rx_sck[3]:1 */ 1316 P5_7_VIDEOSS0_TTL_DSP0_DATA_A16 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[6]:0 */ 1317 P5_7_SCB8_SPI_MOSI = 25, /* Digital Active - scb[8].spi_mosi:0 */ 1318 P5_7_SCB8_UART_TX = 26, /* Digital Active - scb[8].uart_tx:0 */ 1319 P5_7_SCB8_I2C_SCL = 27, /* Digital Active - scb[8].i2c_scl:0 */ 1320 1321 /* P6.0 */ 1322 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1323 P6_0_AMUXA = 4, /* Analog mux bus A */ 1324 P6_0_AMUXB = 5, /* Analog mux bus B */ 1325 P6_0_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:1 */ 1326 P6_0_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:1 */ 1327 P6_0_TCPWM0_TR_ONE_CNT_IN20 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[20]:1 */ 1328 P6_0_TDM0_TDM_TX_FSYNC3 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[3]:1 */ 1329 P6_0_TDM0_TDM_RX_FSYNC3 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[3]:1 */ 1330 P6_0_VIDEOSS0_TTL_DSP0_DATA_A07 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[7]:0 */ 1331 P6_0_SCB8_SPI_MISO = 25, /* Digital Active - scb[8].spi_miso:0 */ 1332 P6_0_SCB8_UART_RTS = 26, /* Digital Active - scb[8].uart_rts:0 */ 1333 1334 /* P6.1 */ 1335 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1336 P6_1_AMUXA = 4, /* Analog mux bus A */ 1337 P6_1_AMUXB = 5, /* Analog mux bus B */ 1338 P6_1_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:1 */ 1339 P6_1_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:1 */ 1340 P6_1_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:1 */ 1341 P6_1_TDM0_TDM_TX_SD3 = 16, /* Digital Active - tdm[0].tdm_tx_sd[3]:1 */ 1342 P6_1_TDM0_TDM_RX_SD3 = 17, /* Digital Active - tdm[0].tdm_rx_sd[3]:1 */ 1343 P6_1_VIDEOSS0_TTL_DSP0_DATA_A17 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[7]:0 */ 1344 P6_1_SCB8_SPI_SELECT0 = 25, /* Digital Active - scb[8].spi_select0:0 */ 1345 P6_1_SCB8_UART_CTS = 26, /* Digital Active - scb[8].uart_cts:0 */ 1346 1347 /* P6.2 */ 1348 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1349 P6_2_AMUXA = 4, /* Analog mux bus A */ 1350 P6_2_AMUXB = 5, /* Analog mux bus B */ 1351 P6_2_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:1 */ 1352 P6_2_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:1 */ 1353 P6_2_TCPWM0_TR_ONE_CNT_IN22 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:1 */ 1354 P6_2_VIDEOSS0_TTL_DSP0_DATA_A08 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[8]:0 */ 1355 P6_2_SCB8_SPI_SELECT1 = 25, /* Digital Active - scb[8].spi_select1:0 */ 1356 P6_2_PERI_TR_IO_INPUT0 = 27, /* Digital Active - peri.tr_io_input[0]:0 */ 1357 1358 /* P6.3 */ 1359 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1360 P6_3_AMUXA = 4, /* Analog mux bus A */ 1361 P6_3_AMUXB = 5, /* Analog mux bus B */ 1362 P6_3_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:1 */ 1363 P6_3_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:1 */ 1364 P6_3_TCPWM0_TR_ONE_CNT_IN23 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[23]:1 */ 1365 P6_3_VIDEOSS0_TTL_DSP0_DATA_A18 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[8]:0 */ 1366 P6_3_PERI_TR_IO_INPUT29 = 27, /* Digital Active - peri.tr_io_input[29]:0 */ 1367 1368 /* P6.4 */ 1369 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1370 P6_4_AMUXA = 4, /* Analog mux bus A */ 1371 P6_4_AMUXB = 5, /* Analog mux bus B */ 1372 P6_4_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:1 */ 1373 P6_4_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:1 */ 1374 P6_4_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:1 */ 1375 P6_4_VIDEOSS0_TTL_DSP0_DATA_A09 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[9]:0 */ 1376 P6_4_PERI_TR_IO_INPUT30 = 27, /* Digital Active - peri.tr_io_input[30]:0 */ 1377 1378 /* P6.5 */ 1379 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1380 P6_5_AMUXA = 4, /* Analog mux bus A */ 1381 P6_5_AMUXB = 5, /* Analog mux bus B */ 1382 P6_5_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:1 */ 1383 P6_5_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:1 */ 1384 P6_5_TCPWM0_TR_ONE_CNT_IN25 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:1 */ 1385 P6_5_VIDEOSS0_TTL_DSP0_DATA_A19 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[9]:0 */ 1386 P6_5_PERI_TR_IO_INPUT31 = 27, /* Digital Active - peri.tr_io_input[31]:0 */ 1387 1388 /* P6.6 */ 1389 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1390 P6_6_AMUXA = 4, /* Analog mux bus A */ 1391 P6_6_AMUXB = 5, /* Analog mux bus B */ 1392 P6_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:1 */ 1393 P6_6_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:1 */ 1394 P6_6_TCPWM0_TR_ONE_CNT_IN26 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[26]:1 */ 1395 P6_6_VIDEOSS0_TTL_DSP0_DATA_A010 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[10]:0 */ 1396 P6_6_PERI_TR_IO_INPUT32 = 27, /* Digital Active - peri.tr_io_input[32]:0 */ 1397 1398 /* P6.7 */ 1399 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1400 P6_7_AMUXA = 4, /* Analog mux bus A */ 1401 P6_7_AMUXB = 5, /* Analog mux bus B */ 1402 P6_7_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:1 */ 1403 P6_7_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:1 */ 1404 P6_7_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:1 */ 1405 P6_7_VIDEOSS0_TTL_DSP0_DATA_A110 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[10]:0 */ 1406 P6_7_PERI_TR_IO_INPUT33 = 27, /* Digital Active - peri.tr_io_input[33]:0 */ 1407 1408 /* P7.0 */ 1409 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1410 P7_0_AMUXA = 4, /* Analog mux bus A */ 1411 P7_0_AMUXB = 5, /* Analog mux bus B */ 1412 P7_0_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:2 */ 1413 P7_0_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:1 */ 1414 P7_0_TCPWM0_TR_ONE_CNT_IN32 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[32]:1 */ 1415 P7_0_VIDEOSS0_TTL_DSP0_DATA_A011 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[11]:0 */ 1416 P7_0_PERI_TR_IO_INPUT10 = 27, /* Digital Active - peri.tr_io_input[10]:0 */ 1417 1418 /* P7.1 */ 1419 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1420 P7_1_AMUXA = 4, /* Analog mux bus A */ 1421 P7_1_AMUXB = 5, /* Analog mux bus B */ 1422 P7_1_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:2 */ 1423 P7_1_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:2 */ 1424 P7_1_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:1 */ 1425 P7_1_PWM0_PWM_LINE1_P0 = 24, /* Digital Active - pwm[0].pwm_line1_p[0]:1 */ 1426 P7_1_PERI_TR_IO_INPUT11 = 27, /* Digital Active - peri.tr_io_input[11]:0 */ 1427 1428 /* P7.2 */ 1429 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1430 P7_2_AMUXA = 4, /* Analog mux bus A */ 1431 P7_2_AMUXB = 5, /* Analog mux bus B */ 1432 P7_2_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:2 */ 1433 P7_2_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:2 */ 1434 P7_2_TCPWM0_TR_ONE_CNT_IN20 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[20]:2 */ 1435 P7_2_PWM0_PWM_LINE1_N0 = 24, /* Digital Active - pwm[0].pwm_line1_n[0]:1 */ 1436 P7_2_PERI_TR_IO_INPUT12 = 27, /* Digital Active - peri.tr_io_input[12]:0 */ 1437 1438 /* P7.3 */ 1439 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1440 P7_3_AMUXA = 4, /* Analog mux bus A */ 1441 P7_3_AMUXB = 5, /* Analog mux bus B */ 1442 P7_3_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:2 */ 1443 P7_3_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:2 */ 1444 P7_3_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:2 */ 1445 P7_3_PWM0_PWM_LINE2_P0 = 24, /* Digital Active - pwm[0].pwm_line2_p[0]:1 */ 1446 P7_3_PERI_TR_IO_INPUT13 = 27, /* Digital Active - peri.tr_io_input[13]:0 */ 1447 1448 /* P7.4 */ 1449 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1450 P7_4_AMUXA = 4, /* Analog mux bus A */ 1451 P7_4_AMUXB = 5, /* Analog mux bus B */ 1452 P7_4_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:2 */ 1453 P7_4_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:2 */ 1454 P7_4_TCPWM0_TR_ONE_CNT_IN22 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:2 */ 1455 P7_4_PWM0_PWM_LINE2_N0 = 24, /* Digital Active - pwm[0].pwm_line2_n[0]:1 */ 1456 P7_4_PERI_TR_IO_INPUT14 = 27, /* Digital Active - peri.tr_io_input[14]:0 */ 1457 1458 /* P7.5 */ 1459 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1460 P7_5_AMUXA = 4, /* Analog mux bus A */ 1461 P7_5_AMUXB = 5, /* Analog mux bus B */ 1462 P7_5_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:2 */ 1463 P7_5_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:2 */ 1464 P7_5_TCPWM0_TR_ONE_CNT_IN23 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[23]:2 */ 1465 P7_5_PWM0_PWM_LINE1_P1 = 24, /* Digital Active - pwm[0].pwm_line1_p[1]:1 */ 1466 P7_5_PERI_TR_IO_INPUT15 = 27, /* Digital Active - peri.tr_io_input[15]:0 */ 1467 1468 /* P7.6 */ 1469 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1470 P7_6_AMUXA = 4, /* Analog mux bus A */ 1471 P7_6_AMUXB = 5, /* Analog mux bus B */ 1472 P7_6_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:2 */ 1473 P7_6_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:2 */ 1474 P7_6_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:2 */ 1475 P7_6_PASS0_SAR_EXT_MUX_SEL0 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[0] */ 1476 P7_6_PWM0_PWM_LINE1_N1 = 24, /* Digital Active - pwm[0].pwm_line1_n[1]:1 */ 1477 P7_6_PERI_TR_IO_INPUT16 = 27, /* Digital Active - peri.tr_io_input[16]:0 */ 1478 1479 /* P7.7 */ 1480 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1481 P7_7_AMUXA = 4, /* Analog mux bus A */ 1482 P7_7_AMUXB = 5, /* Analog mux bus B */ 1483 P7_7_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:2 */ 1484 P7_7_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:2 */ 1485 P7_7_TCPWM0_TR_ONE_CNT_IN25 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:2 */ 1486 P7_7_PASS0_SAR_EXT_MUX_SEL1 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[1] */ 1487 P7_7_PWM0_PWM_LINE2_P1 = 24, /* Digital Active - pwm[0].pwm_line2_p[1]:1 */ 1488 P7_7_PERI_TR_IO_INPUT17 = 27, /* Digital Active - peri.tr_io_input[17]:0 */ 1489 1490 /* P8.0 */ 1491 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1492 P8_0_AMUXA = 4, /* Analog mux bus A */ 1493 P8_0_AMUXB = 5, /* Analog mux bus B */ 1494 P8_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:1 */ 1495 P8_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:2 */ 1496 P8_0_TCPWM0_TR_ONE_CNT_IN28 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:2 */ 1497 P8_0_PASS0_SAR_EXT_MUX_SEL3 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[3] */ 1498 P8_0_VIDEOSS0_TTL_DSP0_CONTROL0 = 24, /* Digital Active - videoss[0].ttl_dsp0_control[0]:0 */ 1499 P8_0_SCB9_SPI_MISO = 25, /* Digital Active - scb[9].spi_miso:0 */ 1500 P8_0_SCB9_UART_RTS = 26, /* Digital Active - scb[9].uart_rts:0 */ 1501 1502 /* P8.1 */ 1503 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1504 P8_1_AMUXA = 4, /* Analog mux bus A */ 1505 P8_1_AMUXB = 5, /* Analog mux bus B */ 1506 P8_1_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:1 */ 1507 P8_1_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:1 */ 1508 P8_1_TCPWM0_TR_ONE_CNT_IN29 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[29]:2 */ 1509 P8_1_PASS0_SAR_EXT_MUX_SEL4 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[4] */ 1510 P8_1_VIDEOSS0_TTL_DSP0_CONTROL1 = 24, /* Digital Active - videoss[0].ttl_dsp0_control[1]:0 */ 1511 P8_1_SCB9_SPI_SELECT0 = 25, /* Digital Active - scb[9].spi_select0:0 */ 1512 P8_1_SCB9_UART_CTS = 26, /* Digital Active - scb[9].uart_cts:0 */ 1513 1514 /* P8.2 */ 1515 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1516 P8_2_AMUXA = 4, /* Analog mux bus A */ 1517 P8_2_AMUXB = 5, /* Analog mux bus B */ 1518 P8_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:1 */ 1519 P8_2_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:1 */ 1520 P8_2_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:1 */ 1521 P8_2_PASS0_SAR_EXT_MUX_SEL5 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[5] */ 1522 P8_2_VIDEOSS0_TTL_DSP0_CONTROL2 = 24, /* Digital Active - videoss[0].ttl_dsp0_control[2]:0 */ 1523 P8_2_SCB9_SPI_SELECT1 = 25, /* Digital Active - scb[9].spi_select1:0 */ 1524 1525 /* P8.3 */ 1526 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1527 P8_3_AMUXA = 4, /* Analog mux bus A */ 1528 P8_3_AMUXB = 5, /* Analog mux bus B */ 1529 P8_3_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:1 */ 1530 P8_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:1 */ 1531 P8_3_TCPWM0_TR_ONE_CNT_IN31 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:1 */ 1532 P8_3_PASS0_SAR_EXT_MUX_EN1 = 16, /* Digital Active - pass[0].sar_ext_mux_en[1] */ 1533 P8_3_VIDEOSS0_TTL_DSP0_CLOCK = 24, /* Digital Active - videoss[0].ttl_dsp0_clock:0 */ 1534 1535 /* P9.0 */ 1536 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1537 P9_0_AMUXA = 4, /* Analog mux bus A */ 1538 P9_0_AMUXB = 5, /* Analog mux bus B */ 1539 P9_0_TCPWM0_LINE256 = 8, /* Digital Active - tcpwm[0].line[256]:0 */ 1540 P9_0_TCPWM0_TR_ONE_CNT_IN530 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[530] */ 1541 P9_0_TDM0_TDM_TX_MCK2 = 16, /* Digital Active - tdm[0].tdm_tx_mck[2]:2 */ 1542 P9_0_TDM0_TDM_RX_MCK2 = 17, /* Digital Active - tdm[0].tdm_rx_mck[2]:2 */ 1543 P9_0_VIDEOSS0_TTL_CAP0_DATA8 = 21, /* Digital Active - videoss[0].ttl_cap0_data[8]:1 */ 1544 P9_0_SG0_SG_AMPL1 = 22, /* Digital Active - sg[0].sg_ampl[1]:0 */ 1545 P9_0_SCB7_SPI_CLK = 25, /* Digital Active - scb[7].spi_clk:0 */ 1546 P9_0_SCB7_UART_RX = 26, /* Digital Active - scb[7].uart_rx:0 */ 1547 P9_0_SCB7_I2C_SDA = 27, /* Digital Active - scb[7].i2c_sda:0 */ 1548 1549 /* P9.1 */ 1550 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1551 P9_1_AMUXA = 4, /* Analog mux bus A */ 1552 P9_1_AMUXB = 5, /* Analog mux bus B */ 1553 P9_1_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:0 */ 1554 P9_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 1555 P9_1_TCPWM0_TR_ONE_CNT_IN35 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[35]:0 */ 1556 P9_1_TDM0_TDM_TX_SCK2 = 16, /* Digital Active - tdm[0].tdm_tx_sck[2]:2 */ 1557 P9_1_TDM0_TDM_RX_SCK2 = 17, /* Digital Active - tdm[0].tdm_rx_sck[2]:2 */ 1558 P9_1_SG0_SG_TONE1 = 22, /* Digital Active - sg[0].sg_tone[1]:0 */ 1559 P9_1_VIDEOSS0_TTL_CAP0_DATA9 = 23, /* Digital Active - videoss[0].ttl_cap0_data[9]:1 */ 1560 P9_1_SCB7_SPI_MOSI = 25, /* Digital Active - scb[7].spi_mosi:0 */ 1561 P9_1_SCB7_UART_TX = 26, /* Digital Active - scb[7].uart_tx:0 */ 1562 P9_1_SCB7_I2C_SCL = 27, /* Digital Active - scb[7].i2c_scl:0 */ 1563 1564 /* P9.2 */ 1565 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1566 P9_2_AMUXA = 4, /* Analog mux bus A */ 1567 P9_2_AMUXB = 5, /* Analog mux bus B */ 1568 P9_2_TCPWM0_LINE257 = 8, /* Digital Active - tcpwm[0].line[257]:0 */ 1569 P9_2_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:0 */ 1570 P9_2_TCPWM0_TR_ONE_CNT_IN531 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[531] */ 1571 P9_2_TDM0_TDM_TX_FSYNC2 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[2]:2 */ 1572 P9_2_TDM0_TDM_RX_FSYNC2 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[2]:2 */ 1573 P9_2_VIDEOSS0_TTL_CAP0_DATA10 = 21, /* Digital Active - videoss[0].ttl_cap0_data[10]:1 */ 1574 P9_2_SG0_SG_AMPL2 = 22, /* Digital Active - sg[0].sg_ampl[2]:0 */ 1575 P9_2_SCB7_SPI_MISO = 25, /* Digital Active - scb[7].spi_miso:0 */ 1576 P9_2_SCB7_UART_RTS = 26, /* Digital Active - scb[7].uart_rts:0 */ 1577 1578 /* P9.3 */ 1579 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1580 P9_3_AMUXA = 4, /* Analog mux bus A */ 1581 P9_3_AMUXB = 5, /* Analog mux bus B */ 1582 P9_3_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:0 */ 1583 P9_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 1584 P9_3_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:0 */ 1585 P9_3_TDM0_TDM_TX_SD2 = 16, /* Digital Active - tdm[0].tdm_tx_sd[2]:2 */ 1586 P9_3_TDM0_TDM_RX_SD2 = 17, /* Digital Active - tdm[0].tdm_rx_sd[2]:2 */ 1587 P9_3_SG0_SG_TONE2 = 22, /* Digital Active - sg[0].sg_tone[2]:0 */ 1588 P9_3_VIDEOSS0_TTL_CAP0_DATA11 = 23, /* Digital Active - videoss[0].ttl_cap0_data[11]:1 */ 1589 P9_3_SCB7_SPI_SELECT0 = 25, /* Digital Active - scb[7].spi_select0:0 */ 1590 P9_3_SCB7_UART_CTS = 26, /* Digital Active - scb[7].uart_cts:0 */ 1591 1592 /* P9.4 */ 1593 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1594 P9_4_AMUXA = 4, /* Analog mux bus A */ 1595 P9_4_AMUXB = 5, /* Analog mux bus B */ 1596 P9_4_TCPWM0_LINE258 = 8, /* Digital Active - tcpwm[0].line[258]:0 */ 1597 P9_4_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:0 */ 1598 P9_4_TCPWM0_TR_ONE_CNT_IN532 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[532] */ 1599 P9_4_TDM0_TDM_RX_MCK3 = 17, /* Digital Active - tdm[0].tdm_rx_mck[3]:2 */ 1600 P9_4_VIDEOSS0_TTL_CAP0_DATA12 = 21, /* Digital Active - videoss[0].ttl_cap0_data[12]:1 */ 1601 P9_4_SG0_SG_AMPL3 = 22, /* Digital Active - sg[0].sg_ampl[3]:0 */ 1602 P9_4_SCB7_SPI_SELECT1 = 25, /* Digital Active - scb[7].spi_select1:0 */ 1603 P9_4_SCB0_UART_RX = 26, /* Digital Active - scb[0].uart_rx:1 */ 1604 P9_4_SCB0_I2C_SDA = 30, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 1605 1606 /* P9.5 */ 1607 P9_5_GPIO = 0, /* GPIO controls 'out' */ 1608 P9_5_AMUXA = 4, /* Analog mux bus A */ 1609 P9_5_AMUXB = 5, /* Analog mux bus B */ 1610 P9_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:0 */ 1611 P9_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 1612 P9_5_TCPWM0_TR_ONE_CNT_IN37 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:0 */ 1613 P9_5_TDM0_TDM_RX_SCK3 = 17, /* Digital Active - tdm[0].tdm_rx_sck[3]:2 */ 1614 P9_5_SG0_SG_TONE3 = 22, /* Digital Active - sg[0].sg_tone[3]:0 */ 1615 P9_5_VIDEOSS0_TTL_CAP0_DATA13 = 23, /* Digital Active - videoss[0].ttl_cap0_data[13]:1 */ 1616 P9_5_SCB0_UART_TX = 26, /* Digital Active - scb[0].uart_tx:1 */ 1617 P9_5_SCB0_I2C_SCL = 30, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 1618 1619 /* P9.6 */ 1620 P9_6_GPIO = 0, /* GPIO controls 'out' */ 1621 P9_6_AMUXA = 4, /* Analog mux bus A */ 1622 P9_6_AMUXB = 5, /* Analog mux bus B */ 1623 P9_6_TCPWM0_LINE259 = 8, /* Digital Active - tcpwm[0].line[259]:0 */ 1624 P9_6_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:0 */ 1625 P9_6_TCPWM0_TR_ONE_CNT_IN533 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[533] */ 1626 P9_6_TDM0_TDM_RX_FSYNC3 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[3]:2 */ 1627 P9_6_VIDEOSS0_TTL_CAP0_DATA14 = 21, /* Digital Active - videoss[0].ttl_cap0_data[14]:1 */ 1628 P9_6_SG0_SG_AMPL4 = 22, /* Digital Active - sg[0].sg_ampl[4]:0 */ 1629 P9_6_CPUSS_FAULT_OUT0 = 27, /* Digital Active - cpuss.fault_out[0]:1 */ 1630 1631 /* P9.7 */ 1632 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1633 P9_7_AMUXA = 4, /* Analog mux bus A */ 1634 P9_7_AMUXB = 5, /* Analog mux bus B */ 1635 P9_7_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 1636 P9_7_TCPWM0_TR_ONE_CNT_IN534 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[534] */ 1637 P9_7_TDM0_TDM_RX_SD3 = 17, /* Digital Active - tdm[0].tdm_rx_sd[3]:2 */ 1638 P9_7_SG0_SG_TONE4 = 22, /* Digital Active - sg[0].sg_tone[4]:0 */ 1639 P9_7_VIDEOSS0_TTL_CAP0_DATA15 = 23, /* Digital Active - videoss[0].ttl_cap0_data[15]:1 */ 1640 P9_7_CPUSS_FAULT_OUT1 = 27, /* Digital Active - cpuss.fault_out[1]:1 */ 1641 1642 /* P11.0 */ 1643 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1644 P11_0_AMUXA = 4, /* Analog mux bus A */ 1645 P11_0_AMUXB = 5, /* Analog mux bus B */ 1646 P11_0_TCPWM0_LINE260 = 8, /* Digital Active - tcpwm[0].line[260]:0 */ 1647 P11_0_TCPWM0_TR_ONE_CNT_IN514 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[514] */ 1648 P11_0_VIDEOSS0_TTL_CAP0_DATA18 = 21, /* Digital Active - videoss[0].ttl_cap0_data[18]:1 */ 1649 P11_0_SCB0_UART_RTS = 26, /* Digital Active - scb[0].uart_rts:0 */ 1650 P11_0_PERI_TR_IO_INPUT34 = 27, /* Digital Active - peri.tr_io_input[34]:0 */ 1651 P11_0_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 1652 1653 /* P11.1 */ 1654 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1655 P11_1_AMUXA = 4, /* Analog mux bus A */ 1656 P11_1_AMUXB = 5, /* Analog mux bus B */ 1657 P11_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 1658 P11_1_TCPWM0_TR_ONE_CNT_IN535 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[535] */ 1659 P11_1_VIDEOSS0_TTL_CAP0_DATA19 = 23, /* Digital Active - videoss[0].ttl_cap0_data[19]:1 */ 1660 P11_1_SCB0_UART_CTS = 26, /* Digital Active - scb[0].uart_cts:0 */ 1661 P11_1_PERI_TR_IO_INPUT35 = 27, /* Digital Active - peri.tr_io_input[35]:0 */ 1662 P11_1_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 1663 1664 /* P11.2 */ 1665 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1666 P11_2_AMUXA = 4, /* Analog mux bus A */ 1667 P11_2_AMUXB = 5, /* Analog mux bus B */ 1668 P11_2_TCPWM0_LINE261 = 8, /* Digital Active - tcpwm[0].line[261]:0 */ 1669 P11_2_TCPWM0_TR_ONE_CNT_IN515 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[515] */ 1670 P11_2_VIDEOSS0_TTL_CAP0_DATA20 = 21, /* Digital Active - videoss[0].ttl_cap0_data[20]:1 */ 1671 P11_2_PERI_TR_IO_INPUT36 = 27, /* Digital Active - peri.tr_io_input[36]:0 */ 1672 P11_2_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:1 */ 1673 1674 /* P11.3 */ 1675 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1676 P11_3_AMUXA = 4, /* Analog mux bus A */ 1677 P11_3_AMUXB = 5, /* Analog mux bus B */ 1678 P11_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 1679 P11_3_TCPWM0_TR_ONE_CNT_IN536 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[536] */ 1680 P11_3_VIDEOSS0_TTL_CAP0_DATA21 = 23, /* Digital Active - videoss[0].ttl_cap0_data[21]:1 */ 1681 P11_3_PERI_TR_IO_INPUT37 = 27, /* Digital Active - peri.tr_io_input[37]:0 */ 1682 P11_3_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:1 */ 1683 1684 /* P11.4 */ 1685 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1686 P11_4_AMUXA = 4, /* Analog mux bus A */ 1687 P11_4_AMUXB = 5, /* Analog mux bus B */ 1688 P11_4_TCPWM0_LINE262 = 8, /* Digital Active - tcpwm[0].line[262]:0 */ 1689 P11_4_TCPWM0_TR_ONE_CNT_IN516 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[516] */ 1690 P11_4_TDM0_TDM_TX_MCK3 = 16, /* Digital Active - tdm[0].tdm_tx_mck[3]:2 */ 1691 P11_4_TDM0_TDM_RX_MCK3 = 17, /* Digital Active - tdm[0].tdm_rx_mck[3]:3 */ 1692 P11_4_VIDEOSS0_TTL_CAP0_DATA22 = 21, /* Digital Active - videoss[0].ttl_cap0_data[22]:1 */ 1693 P11_4_PERI_TR_IO_INPUT38 = 27, /* Digital Active - peri.tr_io_input[38]:0 */ 1694 P11_4_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:1 */ 1695 1696 /* P11.5 */ 1697 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1698 P11_5_AMUXA = 4, /* Analog mux bus A */ 1699 P11_5_AMUXB = 5, /* Analog mux bus B */ 1700 P11_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 1701 P11_5_TCPWM0_TR_ONE_CNT_IN537 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[537] */ 1702 P11_5_TDM0_TDM_TX_SCK3 = 16, /* Digital Active - tdm[0].tdm_tx_sck[3]:2 */ 1703 P11_5_TDM0_TDM_RX_SCK3 = 17, /* Digital Active - tdm[0].tdm_rx_sck[3]:3 */ 1704 P11_5_VIDEOSS0_TTL_CAP0_DATA23 = 23, /* Digital Active - videoss[0].ttl_cap0_data[23]:1 */ 1705 P11_5_PERI_TR_IO_INPUT39 = 27, /* Digital Active - peri.tr_io_input[39]:0 */ 1706 P11_5_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:1 */ 1707 1708 /* P11.6 */ 1709 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1710 P11_6_AMUXA = 4, /* Analog mux bus A */ 1711 P11_6_AMUXB = 5, /* Analog mux bus B */ 1712 P11_6_TCPWM0_LINE263 = 8, /* Digital Active - tcpwm[0].line[263]:0 */ 1713 P11_6_TCPWM0_TR_ONE_CNT_IN517 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[517] */ 1714 P11_6_TDM0_TDM_TX_FSYNC3 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[3]:2 */ 1715 P11_6_TDM0_TDM_RX_FSYNC3 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[3]:3 */ 1716 P11_6_VIDEOSS0_TTL_CAP0_DATA24 = 21, /* Digital Active - videoss[0].ttl_cap0_data[24]:1 */ 1717 P11_6_PERI_TR_IO_INPUT40 = 27, /* Digital Active - peri.tr_io_input[40]:0 */ 1718 P11_6_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 1719 1720 /* P11.7 */ 1721 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1722 P11_7_AMUXA = 4, /* Analog mux bus A */ 1723 P11_7_AMUXB = 5, /* Analog mux bus B */ 1724 P11_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ 1725 P11_7_TCPWM0_TR_ONE_CNT_IN538 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[538] */ 1726 P11_7_TDM0_TDM_TX_SD3 = 16, /* Digital Active - tdm[0].tdm_tx_sd[3]:2 */ 1727 P11_7_TDM0_TDM_RX_SD3 = 17, /* Digital Active - tdm[0].tdm_rx_sd[3]:3 */ 1728 P11_7_VIDEOSS0_TTL_CAP0_DATA25 = 23, /* Digital Active - videoss[0].ttl_cap0_data[25]:1 */ 1729 P11_7_PERI_TR_IO_INPUT41 = 27, /* Digital Active - peri.tr_io_input[41]:0 */ 1730 P11_7_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 1731 1732 /* P12.0 */ 1733 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1734 P12_0_AMUXA = 4, /* Analog mux bus A */ 1735 P12_0_AMUXB = 5, /* Analog mux bus B */ 1736 P12_0_TCPWM0_LINE264 = 8, /* Digital Active - tcpwm[0].line[264]:0 */ 1737 P12_0_TCPWM0_TR_ONE_CNT_IN518 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[518] */ 1738 P12_0_VIDEOSS0_TTL_CAP0_DATA26 = 21, /* Digital Active - videoss[0].ttl_cap0_data[26]:1 */ 1739 P12_0_PERI_TR_IO_INPUT42 = 27, /* Digital Active - peri.tr_io_input[42]:0 */ 1740 P12_0_SCB0_SPI_SELECT3 = 30, /* Digital Deep Sleep - scb[0].spi_select3:0 */ 1741 1742 /* P12.1 */ 1743 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1744 P12_1_AMUXA = 4, /* Analog mux bus A */ 1745 P12_1_AMUXB = 5, /* Analog mux bus B */ 1746 P12_1_TCPWM0_LINE_COMPL264 = 9, /* Digital Active - tcpwm[0].line_compl[264]:0 */ 1747 P12_1_TCPWM0_TR_ONE_CNT_IN539 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[539] */ 1748 P12_1_PERI_TR_IO_INPUT43 = 27, /* Digital Active - peri.tr_io_input[43]:0 */ 1749 1750 /* P12.2 */ 1751 P12_2_GPIO = 0, /* GPIO controls 'out' */ 1752 P12_2_AMUXA = 4, /* Analog mux bus A */ 1753 P12_2_AMUXB = 5, /* Analog mux bus B */ 1754 P12_2_TCPWM0_LINE265 = 8, /* Digital Active - tcpwm[0].line[265]:0 */ 1755 P12_2_TCPWM0_TR_ONE_CNT_IN519 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[519] */ 1756 P12_2_VIDEOSS0_TTL_DSP0_DATA_A00 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[0]:0 */ 1757 P12_2_PERI_TR_IO_INPUT44 = 27, /* Digital Active - peri.tr_io_input[44]:0 */ 1758 1759 /* P12.3 */ 1760 P12_3_GPIO = 0, /* GPIO controls 'out' */ 1761 P12_3_AMUXA = 4, /* Analog mux bus A */ 1762 P12_3_AMUXB = 5, /* Analog mux bus B */ 1763 P12_3_TCPWM0_LINE_COMPL265 = 9, /* Digital Active - tcpwm[0].line_compl[265]:0 */ 1764 P12_3_TCPWM0_TR_ONE_CNT_IN540 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[540] */ 1765 P12_3_VIDEOSS0_TTL_DSP0_DATA_A10 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[0]:0 */ 1766 P12_3_PERI_TR_IO_INPUT45 = 27, /* Digital Active - peri.tr_io_input[45]:0 */ 1767 1768 /* P12.4 */ 1769 P12_4_GPIO = 0, /* GPIO controls 'out' */ 1770 P12_4_AMUXA = 4, /* Analog mux bus A */ 1771 P12_4_AMUXB = 5, /* Analog mux bus B */ 1772 P12_4_TCPWM0_LINE266 = 8, /* Digital Active - tcpwm[0].line[266]:0 */ 1773 P12_4_TCPWM0_TR_ONE_CNT_IN520 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[520] */ 1774 P12_4_SG0_SG_AMPL4 = 22, /* Digital Active - sg[0].sg_ampl[4]:1 */ 1775 P12_4_VIDEOSS0_TTL_DSP0_DATA_A01 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[1]:0 */ 1776 P12_4_PERI_TR_IO_INPUT46 = 27, /* Digital Active - peri.tr_io_input[46]:0 */ 1777 1778 /* P12.5 */ 1779 P12_5_GPIO = 0, /* GPIO controls 'out' */ 1780 P12_5_AMUXA = 4, /* Analog mux bus A */ 1781 P12_5_AMUXB = 5, /* Analog mux bus B */ 1782 P12_5_TCPWM0_LINE_COMPL266 = 9, /* Digital Active - tcpwm[0].line_compl[266]:0 */ 1783 P12_5_TCPWM0_TR_ONE_CNT_IN541 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[541] */ 1784 P12_5_SG0_SG_TONE4 = 22, /* Digital Active - sg[0].sg_tone[4]:1 */ 1785 P12_5_VIDEOSS0_TTL_DSP0_DATA_A11 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[1]:0 */ 1786 P12_5_PERI_TR_IO_INPUT47 = 27, /* Digital Active - peri.tr_io_input[47]:0 */ 1787 1788 /* P12.6 */ 1789 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1790 P12_6_AMUXA = 4, /* Analog mux bus A */ 1791 P12_6_AMUXB = 5, /* Analog mux bus B */ 1792 P12_6_TCPWM0_LINE267 = 8, /* Digital Active - tcpwm[0].line[267]:0 */ 1793 P12_6_TCPWM0_TR_ONE_CNT_IN542 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[542] */ 1794 P12_6_VIDEOSS0_TTL_DSP0_DATA_A02 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a0[2]:0 */ 1795 1796 /* P12.7 */ 1797 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1798 P12_7_AMUXA = 4, /* Analog mux bus A */ 1799 P12_7_AMUXB = 5, /* Analog mux bus B */ 1800 P12_7_TCPWM0_LINE_COMPL267 = 9, /* Digital Active - tcpwm[0].line_compl[267]:0 */ 1801 P12_7_TCPWM0_TR_ONE_CNT_IN543 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[543] */ 1802 P12_7_VIDEOSS0_TTL_DSP0_DATA_A12 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[2]:0 */ 1803 1804 /* P13.0 */ 1805 P13_0_GPIO = 0, /* GPIO controls 'out' */ 1806 P13_0_AMUXA = 4, /* Analog mux bus A */ 1807 P13_0_AMUXB = 5, /* Analog mux bus B */ 1808 P13_0_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:0 */ 1809 P13_0_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:0 */ 1810 P13_0_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:0 */ 1811 P13_0_ETH0_MDC = 24, /* Digital Active - eth[0].mdc */ 1812 1813 /* P13.1 */ 1814 P13_1_GPIO = 0, /* GPIO controls 'out' */ 1815 P13_1_AMUXA = 4, /* Analog mux bus A */ 1816 P13_1_AMUXB = 5, /* Analog mux bus B */ 1817 P13_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:0 */ 1818 P13_1_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:0 */ 1819 P13_1_TCPWM0_TR_ONE_CNT_IN34 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:0 */ 1820 P13_1_ETH0_MDIO = 24, /* Digital Active - eth[0].mdio */ 1821 1822 /* P13.2 */ 1823 P13_2_GPIO = 0, /* GPIO controls 'out' */ 1824 P13_2_AMUXA = 4, /* Analog mux bus A */ 1825 P13_2_AMUXB = 5, /* Analog mux bus B */ 1826 P13_2_ETH0_TXD0 = 24, /* Digital Active - eth[0].txd[0] */ 1827 1828 /* P13.3 */ 1829 P13_3_GPIO = 0, /* GPIO controls 'out' */ 1830 P13_3_AMUXA = 4, /* Analog mux bus A */ 1831 P13_3_AMUXB = 5, /* Analog mux bus B */ 1832 P13_3_VIDEOSS0_TTL_DSP1_CONTROL3 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[3]:0 */ 1833 P13_3_VIDEOSS0_TTL_DSP0_CONTROL3 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[3]:0 */ 1834 P13_3_ETH0_TXD1 = 24, /* Digital Active - eth[0].txd[1] */ 1835 1836 /* P13.4 */ 1837 P13_4_GPIO = 0, /* GPIO controls 'out' */ 1838 P13_4_AMUXA = 4, /* Analog mux bus A */ 1839 P13_4_AMUXB = 5, /* Analog mux bus B */ 1840 P13_4_VIDEOSS0_TTL_DSP1_CONTROL4 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[4]:0 */ 1841 P13_4_VIDEOSS0_TTL_DSP0_CONTROL4 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[4]:0 */ 1842 P13_4_ETH0_TX_CLK = 24, /* Digital Active - eth[0].tx_clk */ 1843 1844 /* P13.5 */ 1845 P13_5_GPIO = 0, /* GPIO controls 'out' */ 1846 P13_5_AMUXA = 4, /* Analog mux bus A */ 1847 P13_5_AMUXB = 5, /* Analog mux bus B */ 1848 P13_5_ETH0_REF_CLK = 24, /* Digital Active - eth[0].ref_clk */ 1849 1850 /* P13.6 */ 1851 P13_6_GPIO = 0, /* GPIO controls 'out' */ 1852 P13_6_AMUXA = 4, /* Analog mux bus A */ 1853 P13_6_AMUXB = 5, /* Analog mux bus B */ 1854 P13_6_ETH0_TXD2 = 24, /* Digital Active - eth[0].txd[2] */ 1855 1856 /* P13.7 */ 1857 P13_7_GPIO = 0, /* GPIO controls 'out' */ 1858 P13_7_AMUXA = 4, /* Analog mux bus A */ 1859 P13_7_AMUXB = 5, /* Analog mux bus B */ 1860 P13_7_ETH0_TXD3 = 24, /* Digital Active - eth[0].txd[3] */ 1861 1862 /* P14.0 */ 1863 P14_0_GPIO = 0, /* GPIO controls 'out' */ 1864 P14_0_AMUXA = 4, /* Analog mux bus A */ 1865 P14_0_AMUXB = 5, /* Analog mux bus B */ 1866 P14_0_VIDEOSS0_TTL_DSP1_CONTROL5 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[5]:0 */ 1867 P14_0_VIDEOSS0_TTL_DSP0_CONTROL5 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[5]:0 */ 1868 P14_0_ETH0_TX_CTL = 24, /* Digital Active - eth[0].tx_ctl */ 1869 1870 /* P14.1 */ 1871 P14_1_GPIO = 0, /* GPIO controls 'out' */ 1872 P14_1_AMUXA = 4, /* Analog mux bus A */ 1873 P14_1_AMUXB = 5, /* Analog mux bus B */ 1874 P14_1_VIDEOSS0_TTL_DSP1_CONTROL6 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[6]:0 */ 1875 P14_1_VIDEOSS0_TTL_DSP0_CONTROL6 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[6]:0 */ 1876 P14_1_ETH0_TX_ER = 24, /* Digital Active - eth[0].tx_er */ 1877 1878 /* P14.2 */ 1879 P14_2_GPIO = 0, /* GPIO controls 'out' */ 1880 P14_2_AMUXA = 4, /* Analog mux bus A */ 1881 P14_2_AMUXB = 5, /* Analog mux bus B */ 1882 P14_2_ETH0_RX_CLK = 24, /* Digital Active - eth[0].rx_clk */ 1883 1884 /* P14.3 */ 1885 P14_3_GPIO = 0, /* GPIO controls 'out' */ 1886 P14_3_AMUXA = 4, /* Analog mux bus A */ 1887 P14_3_AMUXB = 5, /* Analog mux bus B */ 1888 P14_3_ETH0_RXD0 = 24, /* Digital Active - eth[0].rxd[0] */ 1889 1890 /* P14.4 */ 1891 P14_4_GPIO = 0, /* GPIO controls 'out' */ 1892 P14_4_AMUXA = 4, /* Analog mux bus A */ 1893 P14_4_AMUXB = 5, /* Analog mux bus B */ 1894 P14_4_ETH0_RXD1 = 24, /* Digital Active - eth[0].rxd[1] */ 1895 1896 /* P14.5 */ 1897 P14_5_GPIO = 0, /* GPIO controls 'out' */ 1898 P14_5_AMUXA = 4, /* Analog mux bus A */ 1899 P14_5_AMUXB = 5, /* Analog mux bus B */ 1900 P14_5_VIDEOSS0_TTL_DSP1_CONTROL7 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[7]:0 */ 1901 P14_5_VIDEOSS0_TTL_DSP0_CONTROL7 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[7]:0 */ 1902 P14_5_ETH0_RXD2 = 24, /* Digital Active - eth[0].rxd[2] */ 1903 1904 /* P14.6 */ 1905 P14_6_GPIO = 0, /* GPIO controls 'out' */ 1906 P14_6_AMUXA = 4, /* Analog mux bus A */ 1907 P14_6_AMUXB = 5, /* Analog mux bus B */ 1908 P14_6_VIDEOSS0_TTL_DSP1_CONTROL8 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[8]:0 */ 1909 P14_6_VIDEOSS0_TTL_DSP0_CONTROL8 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[8]:0 */ 1910 P14_6_PERI_TR_IO_INPUT18 = 20, /* Digital Active - peri.tr_io_input[18]:0 */ 1911 P14_6_ETH0_RXD3 = 24, /* Digital Active - eth[0].rxd[3] */ 1912 1913 /* P14.7 */ 1914 P14_7_GPIO = 0, /* GPIO controls 'out' */ 1915 P14_7_AMUXA = 4, /* Analog mux bus A */ 1916 P14_7_AMUXB = 5, /* Analog mux bus B */ 1917 P14_7_VIDEOSS0_TTL_DSP1_CONTROL9 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[9]:0 */ 1918 P14_7_VIDEOSS0_TTL_DSP0_CONTROL9 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[9]:0 */ 1919 P14_7_PERI_TR_IO_INPUT19 = 20, /* Digital Active - peri.tr_io_input[19]:0 */ 1920 P14_7_ETH0_RX_CTL = 24, /* Digital Active - eth[0].rx_ctl */ 1921 1922 /* P15.2 */ 1923 P15_2_GPIO = 0, /* GPIO controls 'out' */ 1924 P15_2_AMUXA = 4, /* Analog mux bus A */ 1925 P15_2_AMUXB = 5, /* Analog mux bus B */ 1926 P15_2_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:0 */ 1927 P15_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:0 */ 1928 P15_2_TCPWM0_TR_ONE_CNT_IN32 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[32]:0 */ 1929 P15_2_VIDEOSS0_TTL_DSP1_CONTROL11 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[11]:0 */ 1930 P15_2_VIDEOSS0_TTL_DSP0_CONTROL11 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[11]:0 */ 1931 P15_2_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:2 */ 1932 P15_2_SCB1_SPI_CLK = 25, /* Digital Active - scb[1].spi_clk:1 */ 1933 P15_2_SCB1_UART_RX = 26, /* Digital Active - scb[1].uart_rx:1 */ 1934 P15_2_SCB1_I2C_SDA = 27, /* Digital Active - scb[1].i2c_sda:0 */ 1935 1936 /* P15.3 */ 1937 P15_3_GPIO = 0, /* GPIO controls 'out' */ 1938 P15_3_AMUXA = 4, /* Analog mux bus A */ 1939 P15_3_AMUXB = 5, /* Analog mux bus B */ 1940 P15_3_TCPWM0_LINE521 = 8, /* Digital Active - tcpwm[0].line[521]:0 */ 1941 P15_3_TCPWM0_LINE_COMPL523 = 9, /* Digital Active - tcpwm[0].line_compl[523]:0 */ 1942 P15_3_TCPWM0_TR_ONE_CNT_IN522 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[522]:0 */ 1943 P15_3_VIDEOSS0_TTL_CAP0_DATA26 = 21, /* Digital Active - videoss[0].ttl_cap0_data[26]:2 */ 1944 P15_3_SRSS_DDFT_CLK_DIRECT = 22, /* Digital Active - srss.ddft_clk_direct */ 1945 P15_3_SCB1_SPI_MOSI = 25, /* Digital Active - scb[1].spi_mosi:1 */ 1946 P15_3_SCB1_UART_TX = 26, /* Digital Active - scb[1].uart_tx:1 */ 1947 P15_3_SCB1_I2C_SCL = 27, /* Digital Active - scb[1].i2c_scl:0 */ 1948 1949 /* P15.4 */ 1950 P15_4_GPIO = 0, /* GPIO controls 'out' */ 1951 P15_4_AMUXA = 4, /* Analog mux bus A */ 1952 P15_4_AMUXB = 5, /* Analog mux bus B */ 1953 P15_4_TCPWM0_LINE522 = 8, /* Digital Active - tcpwm[0].line[522]:0 */ 1954 P15_4_TCPWM0_LINE_COMPL521 = 9, /* Digital Active - tcpwm[0].line_compl[521]:0 */ 1955 P15_4_TCPWM0_TR_ONE_CNT_IN523 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[523]:0 */ 1956 P15_4_SRSS_EXT_CLK = 22, /* Digital Active - srss.ext_clk:3 */ 1957 P15_4_VIDEOSS0_TTL_CAP0_DATA25 = 23, /* Digital Active - videoss[0].ttl_cap0_data[25]:2 */ 1958 P15_4_SCB1_SPI_MISO = 25, /* Digital Active - scb[1].spi_miso:1 */ 1959 P15_4_SCB1_UART_RTS = 26, /* Digital Active - scb[1].uart_rts:1 */ 1960 P15_4_CPUSS_CAL_SUP_NZ = 27, /* Digital Active - cpuss.cal_sup_nz:0 */ 1961 1962 /* P15.5 */ 1963 P15_5_GPIO = 0, /* GPIO controls 'out' */ 1964 P15_5_AMUXA = 4, /* Analog mux bus A */ 1965 P15_5_AMUXB = 5, /* Analog mux bus B */ 1966 P15_5_TCPWM0_LINE523 = 8, /* Digital Active - tcpwm[0].line[523]:0 */ 1967 P15_5_TCPWM0_LINE_COMPL522 = 9, /* Digital Active - tcpwm[0].line_compl[522]:0 */ 1968 P15_5_TCPWM0_TR_ONE_CNT_IN521 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[521]:0 */ 1969 P15_5_CPUSS_TRACE_CLOCK = 11, /* Digital Active - cpuss.trace_clock:0 */ 1970 P15_5_VIDEOSS0_TTL_CAP0_DATA24 = 21, /* Digital Active - videoss[0].ttl_cap0_data[24]:2 */ 1971 P15_5_PWM0_PWM_LINE1_P0 = 24, /* Digital Active - pwm[0].pwm_line1_p[0]:3 */ 1972 P15_5_SCB1_SPI_SELECT0 = 25, /* Digital Active - scb[1].spi_select0:1 */ 1973 P15_5_SCB1_UART_CTS = 26, /* Digital Active - scb[1].uart_cts:1 */ 1974 1975 /* P15.6 */ 1976 P15_6_GPIO = 0, /* GPIO controls 'out' */ 1977 P15_6_AMUXA = 4, /* Analog mux bus A */ 1978 P15_6_AMUXB = 5, /* Analog mux bus B */ 1979 P15_6_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:3 */ 1980 P15_6_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:4 */ 1981 P15_6_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:4 */ 1982 P15_6_TDM0_TDM_TX_MCK0 = 16, /* Digital Active - tdm[0].tdm_tx_mck[0]:1 */ 1983 P15_6_TDM0_TDM_RX_MCK0 = 17, /* Digital Active - tdm[0].tdm_rx_mck[0]:2 */ 1984 P15_6_TDM0_TDM_RX_MCK1 = 18, /* Digital Active - tdm[0].tdm_rx_mck[1]:2 */ 1985 P15_6_SG0_SG_MCK0 = 22, /* Digital Active - sg[0].sg_mck[0]:0 */ 1986 P15_6_VIDEOSS0_TTL_CAP0_CLK = 23, /* Digital Active - videoss[0].ttl_cap0_clk:0 */ 1987 P15_6_PWM0_PWM_LINE1_N0 = 24, /* Digital Active - pwm[0].pwm_line1_n[0]:3 */ 1988 P15_6_SCB1_SPI_SELECT1 = 25, /* Digital Active - scb[1].spi_select1:1 */ 1989 P15_6_PERI_TR_IO_INPUT22 = 27, /* Digital Active - peri.tr_io_input[22]:0 */ 1990 1991 /* P15.7 */ 1992 P15_7_GPIO = 0, /* GPIO controls 'out' */ 1993 P15_7_AMUXA = 4, /* Analog mux bus A */ 1994 P15_7_AMUXB = 5, /* Analog mux bus B */ 1995 P15_7_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:3 */ 1996 P15_7_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:3 */ 1997 P15_7_TCPWM0_TR_ONE_CNT_IN31 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:4 */ 1998 P15_7_CPUSS_TRACE_DATA0 = 11, /* Digital Active - cpuss.trace_data[0]:0 */ 1999 P15_7_TDM0_TDM_TX_SCK0 = 16, /* Digital Active - tdm[0].tdm_tx_sck[0]:1 */ 2000 P15_7_TDM0_TDM_RX_SCK0 = 17, /* Digital Active - tdm[0].tdm_rx_sck[0]:2 */ 2001 P15_7_TDM0_TDM_RX_SCK1 = 18, /* Digital Active - tdm[0].tdm_rx_sck[1]:2 */ 2002 P15_7_VIDEOSS0_TTL_DSP1_DATA_A00 = 20, /* Digital Active - videoss[0].ttl_dsp1_data_a0[0]:1 */ 2003 P15_7_VIDEOSS0_TTL_CAP0_DATA0 = 21, /* Digital Active - videoss[0].ttl_cap0_data[0]:0 */ 2004 P15_7_SG0_SG_MCK1 = 22, /* Digital Active - sg[0].sg_mck[1]:0 */ 2005 P15_7_VIDEOSS0_TTL_CAP0_DATA23 = 23, /* Digital Active - videoss[0].ttl_cap0_data[23]:2 */ 2006 P15_7_PWM0_PWM_LINE2_P0 = 24, /* Digital Active - pwm[0].pwm_line2_p[0]:3 */ 2007 P15_7_PERI_TR_IO_INPUT23 = 27, /* Digital Active - peri.tr_io_input[23]:0 */ 2008 2009 /* P16.0 */ 2010 P16_0_GPIO = 0, /* GPIO controls 'out' */ 2011 P16_0_AMUXA = 4, /* Analog mux bus A */ 2012 P16_0_AMUXB = 5, /* Analog mux bus B */ 2013 P16_0_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:3 */ 2014 P16_0_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:3 */ 2015 P16_0_TCPWM0_TR_ONE_CNT_IN20 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[20]:3 */ 2016 P16_0_CPUSS_TRACE_DATA1 = 11, /* Digital Active - cpuss.trace_data[1]:0 */ 2017 P16_0_TDM0_TDM_TX_FSYNC0 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[0]:1 */ 2018 P16_0_TDM0_TDM_RX_FSYNC0 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[0]:2 */ 2019 P16_0_TDM0_TDM_RX_FSYNC1 = 18, /* Digital Active - tdm[0].tdm_rx_fsync[1]:2 */ 2020 P16_0_VIDEOSS0_TTL_DSP1_DATA_A10 = 20, /* Digital Active - videoss[0].ttl_dsp1_data_a1[0]:1 */ 2021 P16_0_VIDEOSS0_TTL_CAP0_DATA22 = 21, /* Digital Active - videoss[0].ttl_cap0_data[22]:2 */ 2022 P16_0_SG0_SG_MCK2 = 22, /* Digital Active - sg[0].sg_mck[2]:0 */ 2023 P16_0_VIDEOSS0_TTL_CAP0_DATA1 = 23, /* Digital Active - videoss[0].ttl_cap0_data[1]:0 */ 2024 P16_0_PWM0_PWM_LINE2_N0 = 24, /* Digital Active - pwm[0].pwm_line2_n[0]:3 */ 2025 P16_0_PERI_TR_IO_INPUT24 = 27, /* Digital Active - peri.tr_io_input[24]:0 */ 2026 2027 /* P16.1 */ 2028 P16_1_GPIO = 0, /* GPIO controls 'out' */ 2029 P16_1_AMUXA = 4, /* Analog mux bus A */ 2030 P16_1_AMUXB = 5, /* Analog mux bus B */ 2031 P16_1_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:3 */ 2032 P16_1_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:3 */ 2033 P16_1_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:3 */ 2034 P16_1_CPUSS_TRACE_DATA2 = 11, /* Digital Active - cpuss.trace_data[2]:0 */ 2035 P16_1_TDM0_TDM_TX_SD0 = 16, /* Digital Active - tdm[0].tdm_tx_sd[0]:1 */ 2036 P16_1_TDM0_TDM_RX_SD0 = 17, /* Digital Active - tdm[0].tdm_rx_sd[0]:2 */ 2037 P16_1_TDM0_TDM_RX_SD1 = 18, /* Digital Active - tdm[0].tdm_rx_sd[1]:2 */ 2038 P16_1_VIDEOSS0_TTL_CAP0_DATA2 = 21, /* Digital Active - videoss[0].ttl_cap0_data[2]:0 */ 2039 P16_1_SG0_SG_MCK3 = 22, /* Digital Active - sg[0].sg_mck[3]:0 */ 2040 P16_1_VIDEOSS0_TTL_CAP0_DATA21 = 23, /* Digital Active - videoss[0].ttl_cap0_data[21]:2 */ 2041 P16_1_PWM0_PWM_LINE1_P1 = 24, /* Digital Active - pwm[0].pwm_line1_p[1]:3 */ 2042 P16_1_PERI_TR_IO_INPUT25 = 27, /* Digital Active - peri.tr_io_input[25]:0 */ 2043 2044 /* P16.2 */ 2045 P16_2_GPIO = 0, /* GPIO controls 'out' */ 2046 P16_2_AMUXA = 4, /* Analog mux bus A */ 2047 P16_2_AMUXB = 5, /* Analog mux bus B */ 2048 P16_2_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:3 */ 2049 P16_2_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:3 */ 2050 P16_2_TCPWM0_TR_ONE_CNT_IN22 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:3 */ 2051 P16_2_CPUSS_TRACE_DATA3 = 11, /* Digital Active - cpuss.trace_data[3]:0 */ 2052 P16_2_TDM0_TDM_TX_MCK1 = 16, /* Digital Active - tdm[0].tdm_tx_mck[1]:1 */ 2053 P16_2_TDM0_TDM_RX_MCK0 = 17, /* Digital Active - tdm[0].tdm_rx_mck[0]:3 */ 2054 P16_2_TDM0_TDM_RX_MCK1 = 18, /* Digital Active - tdm[0].tdm_rx_mck[1]:3 */ 2055 P16_2_VIDEOSS0_TTL_CAP0_DATA20 = 21, /* Digital Active - videoss[0].ttl_cap0_data[20]:2 */ 2056 P16_2_SG0_SG_MCK4 = 22, /* Digital Active - sg[0].sg_mck[4]:0 */ 2057 P16_2_VIDEOSS0_TTL_CAP0_DATA3 = 23, /* Digital Active - videoss[0].ttl_cap0_data[3]:0 */ 2058 P16_2_PWM0_PWM_LINE1_N1 = 24, /* Digital Active - pwm[0].pwm_line1_n[1]:3 */ 2059 P16_2_PERI_TR_IO_INPUT26 = 27, /* Digital Active - peri.tr_io_input[26]:0 */ 2060 2061 /* P16.3 */ 2062 P16_3_GPIO = 0, /* GPIO controls 'out' */ 2063 P16_3_AMUXA = 4, /* Analog mux bus A */ 2064 P16_3_AMUXB = 5, /* Analog mux bus B */ 2065 P16_3_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:3 */ 2066 P16_3_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:3 */ 2067 P16_3_TCPWM0_TR_ONE_CNT_IN23 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[23]:3 */ 2068 P16_3_CPUSS_TRACE_DATA4 = 11, /* Digital Active - cpuss.trace_data[4]:0 */ 2069 P16_3_TDM0_TDM_TX_SCK1 = 16, /* Digital Active - tdm[0].tdm_tx_sck[1]:1 */ 2070 P16_3_TDM0_TDM_RX_SCK0 = 17, /* Digital Active - tdm[0].tdm_rx_sck[0]:3 */ 2071 P16_3_TDM0_TDM_RX_SCK1 = 18, /* Digital Active - tdm[0].tdm_rx_sck[1]:3 */ 2072 P16_3_VIDEOSS0_TTL_CAP0_DATA4 = 21, /* Digital Active - videoss[0].ttl_cap0_data[4]:0 */ 2073 P16_3_PWM0_PWM_MCK0 = 22, /* Digital Active - pwm[0].pwm_mck[0]:0 */ 2074 P16_3_VIDEOSS0_TTL_CAP0_DATA19 = 23, /* Digital Active - videoss[0].ttl_cap0_data[19]:2 */ 2075 P16_3_PERI_TR_IO_INPUT27 = 27, /* Digital Active - peri.tr_io_input[27]:0 */ 2076 2077 /* P16.4 */ 2078 P16_4_GPIO = 0, /* GPIO controls 'out' */ 2079 P16_4_AMUXA = 4, /* Analog mux bus A */ 2080 P16_4_AMUXB = 5, /* Analog mux bus B */ 2081 P16_4_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:3 */ 2082 P16_4_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:3 */ 2083 P16_4_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:3 */ 2084 P16_4_CPUSS_TRACE_DATA5 = 11, /* Digital Active - cpuss.trace_data[5]:0 */ 2085 P16_4_TDM0_TDM_TX_FSYNC1 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[1]:1 */ 2086 P16_4_TDM0_TDM_RX_FSYNC0 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[0]:3 */ 2087 P16_4_TDM0_TDM_RX_FSYNC1 = 18, /* Digital Active - tdm[0].tdm_rx_fsync[1]:3 */ 2088 P16_4_VIDEOSS0_TTL_CAP0_DATA18 = 21, /* Digital Active - videoss[0].ttl_cap0_data[18]:2 */ 2089 P16_4_PWM0_PWM_MCK1 = 22, /* Digital Active - pwm[0].pwm_mck[1]:0 */ 2090 P16_4_VIDEOSS0_TTL_CAP0_DATA5 = 23, /* Digital Active - videoss[0].ttl_cap0_data[5]:0 */ 2091 2092 /* P16.5 */ 2093 P16_5_GPIO = 0, /* GPIO controls 'out' */ 2094 P16_5_AMUXA = 4, /* Analog mux bus A */ 2095 P16_5_AMUXB = 5, /* Analog mux bus B */ 2096 P16_5_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:3 */ 2097 P16_5_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:3 */ 2098 P16_5_TCPWM0_TR_ONE_CNT_IN25 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:3 */ 2099 P16_5_CPUSS_TRACE_DATA6 = 11, /* Digital Active - cpuss.trace_data[6]:0 */ 2100 P16_5_TDM0_TDM_TX_SD1 = 16, /* Digital Active - tdm[0].tdm_tx_sd[1]:1 */ 2101 P16_5_TDM0_TDM_RX_SD0 = 17, /* Digital Active - tdm[0].tdm_rx_sd[0]:3 */ 2102 P16_5_TDM0_TDM_RX_SD1 = 18, /* Digital Active - tdm[0].tdm_rx_sd[1]:3 */ 2103 P16_5_VIDEOSS0_TTL_CAP0_DATA6 = 21, /* Digital Active - videoss[0].ttl_cap0_data[6]:0 */ 2104 P16_5_VIDEOSS0_TTL_CAP0_DATA17 = 23, /* Digital Active - videoss[0].ttl_cap0_data[17]:2 */ 2105 P16_5_PWM0_PWM_LINE2_P1 = 24, /* Digital Active - pwm[0].pwm_line2_p[1]:3 */ 2106 P16_5_SCB1_SPI_SELECT1 = 25, /* Digital Active - scb[1].spi_select1:0 */ 2107 2108 /* P16.6 */ 2109 P16_6_GPIO = 0, /* GPIO controls 'out' */ 2110 P16_6_AMUXA = 4, /* Analog mux bus A */ 2111 P16_6_AMUXB = 5, /* Analog mux bus B */ 2112 P16_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:3 */ 2113 P16_6_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:3 */ 2114 P16_6_TCPWM0_TR_ONE_CNT_IN26 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[26]:3 */ 2115 P16_6_CPUSS_TRACE_DATA7 = 11, /* Digital Active - cpuss.trace_data[7]:0 */ 2116 P16_6_VIDEOSS0_TTL_CAP0_DATA16 = 21, /* Digital Active - videoss[0].ttl_cap0_data[16]:2 */ 2117 P16_6_VIDEOSS0_TTL_CAP0_DATA7 = 23, /* Digital Active - videoss[0].ttl_cap0_data[7]:0 */ 2118 P16_6_PWM0_PWM_LINE2_N1 = 24, /* Digital Active - pwm[0].pwm_line2_n[1]:3 */ 2119 P16_6_SCB1_SPI_SELECT0 = 25, /* Digital Active - scb[1].spi_select0:0 */ 2120 P16_6_SCB1_UART_CTS = 26, /* Digital Active - scb[1].uart_cts:0 */ 2121 2122 /* P16.7 */ 2123 P16_7_GPIO = 0, /* GPIO controls 'out' */ 2124 P16_7_AMUXA = 4, /* Analog mux bus A */ 2125 P16_7_AMUXB = 5, /* Analog mux bus B */ 2126 P16_7_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:3 */ 2127 P16_7_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:3 */ 2128 P16_7_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:3 */ 2129 P16_7_VIDEOSS0_TTL_DSP1_DATA_A00 = 20, /* Digital Active - videoss[0].ttl_dsp1_data_a0[0]:0 */ 2130 P16_7_VIDEOSS0_TTL_CAP0_DATA8 = 21, /* Digital Active - videoss[0].ttl_cap0_data[8]:0 */ 2131 P16_7_VIDEOSS0_TTL_CAP0_DATA15 = 23, /* Digital Active - videoss[0].ttl_cap0_data[15]:2 */ 2132 P16_7_SCB1_SPI_CLK = 25, /* Digital Active - scb[1].spi_clk:0 */ 2133 P16_7_SCB1_UART_RX = 26, /* Digital Active - scb[1].uart_rx:0 */ 2134 P16_7_PERI_TR_IO_OUTPUT0 = 27, /* Digital Active - peri.tr_io_output[0]:0 */ 2135 2136 /* P17.0 */ 2137 P17_0_GPIO = 0, /* GPIO controls 'out' */ 2138 P17_0_AMUXA = 4, /* Analog mux bus A */ 2139 P17_0_AMUXB = 5, /* Analog mux bus B */ 2140 P17_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:2 */ 2141 P17_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:3 */ 2142 P17_0_TCPWM0_TR_ONE_CNT_IN28 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:3 */ 2143 P17_0_VIDEOSS0_TTL_DSP1_DATA_A10 = 20, /* Digital Active - videoss[0].ttl_dsp1_data_a1[0]:0 */ 2144 P17_0_VIDEOSS0_TTL_CAP0_DATA14 = 21, /* Digital Active - videoss[0].ttl_cap0_data[14]:2 */ 2145 P17_0_VIDEOSS0_TTL_CAP0_DATA9 = 23, /* Digital Active - videoss[0].ttl_cap0_data[9]:0 */ 2146 P17_0_SCB1_SPI_MOSI = 25, /* Digital Active - scb[1].spi_mosi:0 */ 2147 P17_0_SCB1_UART_TX = 26, /* Digital Active - scb[1].uart_tx:0 */ 2148 P17_0_PERI_TR_IO_OUTPUT1 = 27, /* Digital Active - peri.tr_io_output[1]:0 */ 2149 2150 /* P18.0 */ 2151 P18_0_GPIO = 0, /* GPIO controls 'out' */ 2152 P18_0_AMUXA = 4, /* Analog mux bus A */ 2153 P18_0_AMUXB = 5, /* Analog mux bus B */ 2154 P18_0_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:2 */ 2155 P18_0_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:2 */ 2156 P18_0_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:2 */ 2157 P18_0_CPUSS_TRACE_CLOCK = 11, /* Digital Active - cpuss.trace_clock:1 */ 2158 P18_0_VIDEOSS0_TTL_CAP0_DATA10 = 21, /* Digital Active - videoss[0].ttl_cap0_data[10]:0 */ 2159 P18_0_VIDEOSS0_TTL_CAP0_DATA13 = 23, /* Digital Active - videoss[0].ttl_cap0_data[13]:2 */ 2160 P18_0_VIDEOSS0_TTL_DSP1_DATA_A01 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[1]:0 */ 2161 P18_0_SCB3_SPI_CLK = 25, /* Digital Active - scb[3].spi_clk:0 */ 2162 P18_0_SCB3_UART_RX = 26, /* Digital Active - scb[3].uart_rx:0 */ 2163 P18_0_SCB3_I2C_SDA = 27, /* Digital Active - scb[3].i2c_sda:0 */ 2164 2165 /* P18.1 */ 2166 P18_1_GPIO = 0, /* GPIO controls 'out' */ 2167 P18_1_AMUXA = 4, /* Analog mux bus A */ 2168 P18_1_AMUXB = 5, /* Analog mux bus B */ 2169 P18_1_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:2 */ 2170 P18_1_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:2 */ 2171 P18_1_TCPWM0_TR_ONE_CNT_IN31 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:2 */ 2172 P18_1_CPUSS_TRACE_DATA0 = 11, /* Digital Active - cpuss.trace_data[0]:1 */ 2173 P18_1_VIDEOSS0_TTL_CAP0_DATA12 = 21, /* Digital Active - videoss[0].ttl_cap0_data[12]:2 */ 2174 P18_1_VIDEOSS0_TTL_CAP0_DATA11 = 23, /* Digital Active - videoss[0].ttl_cap0_data[11]:0 */ 2175 P18_1_VIDEOSS0_TTL_DSP1_DATA_A11 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[1]:0 */ 2176 P18_1_SCB3_SPI_MOSI = 25, /* Digital Active - scb[3].spi_mosi:0 */ 2177 P18_1_SCB3_UART_TX = 26, /* Digital Active - scb[3].uart_tx:0 */ 2178 P18_1_SCB3_I2C_SCL = 27, /* Digital Active - scb[3].i2c_scl:0 */ 2179 2180 /* P18.2 */ 2181 P18_2_GPIO = 0, /* GPIO controls 'out' */ 2182 P18_2_AMUXA = 4, /* Analog mux bus A */ 2183 P18_2_AMUXB = 5, /* Analog mux bus B */ 2184 P18_2_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:1 */ 2185 P18_2_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:2 */ 2186 P18_2_TCPWM0_TR_ONE_CNT_IN32 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[32]:2 */ 2187 P18_2_CPUSS_TRACE_DATA1 = 11, /* Digital Active - cpuss.trace_data[1]:1 */ 2188 P18_2_VIDEOSS0_TTL_CAP0_DATA12 = 21, /* Digital Active - videoss[0].ttl_cap0_data[12]:0 */ 2189 P18_2_VIDEOSS0_TTL_CAP0_DATA11 = 23, /* Digital Active - videoss[0].ttl_cap0_data[11]:2 */ 2190 P18_2_VIDEOSS0_TTL_DSP1_DATA_A02 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[2]:0 */ 2191 P18_2_SCB3_SPI_MISO = 25, /* Digital Active - scb[3].spi_miso:0 */ 2192 P18_2_SCB3_UART_RTS = 26, /* Digital Active - scb[3].uart_rts:0 */ 2193 2194 /* P18.3 */ 2195 P18_3_GPIO = 0, /* GPIO controls 'out' */ 2196 P18_3_AMUXA = 4, /* Analog mux bus A */ 2197 P18_3_AMUXB = 5, /* Analog mux bus B */ 2198 P18_3_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:1 */ 2199 P18_3_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:1 */ 2200 P18_3_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:2 */ 2201 P18_3_CPUSS_TRACE_DATA2 = 11, /* Digital Active - cpuss.trace_data[2]:1 */ 2202 P18_3_VIDEOSS0_TTL_CAP0_DATA10 = 21, /* Digital Active - videoss[0].ttl_cap0_data[10]:2 */ 2203 P18_3_VIDEOSS0_TTL_CAP0_DATA13 = 23, /* Digital Active - videoss[0].ttl_cap0_data[13]:0 */ 2204 P18_3_VIDEOSS0_TTL_DSP1_DATA_A12 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[2]:0 */ 2205 P18_3_SCB3_SPI_SELECT0 = 25, /* Digital Active - scb[3].spi_select0:0 */ 2206 P18_3_SCB3_UART_CTS = 26, /* Digital Active - scb[3].uart_cts:0 */ 2207 2208 /* P18.4 */ 2209 P18_4_GPIO = 0, /* GPIO controls 'out' */ 2210 P18_4_AMUXA = 4, /* Analog mux bus A */ 2211 P18_4_AMUXB = 5, /* Analog mux bus B */ 2212 P18_4_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:1 */ 2213 P18_4_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:1 */ 2214 P18_4_TCPWM0_TR_ONE_CNT_IN34 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:1 */ 2215 P18_4_CPUSS_TRACE_DATA3 = 11, /* Digital Active - cpuss.trace_data[3]:1 */ 2216 P18_4_VIDEOSS0_TTL_CAP0_DATA14 = 21, /* Digital Active - videoss[0].ttl_cap0_data[14]:0 */ 2217 P18_4_VIDEOSS0_TTL_CAP0_DATA9 = 23, /* Digital Active - videoss[0].ttl_cap0_data[9]:2 */ 2218 P18_4_VIDEOSS0_TTL_DSP1_DATA_A03 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[3]:0 */ 2219 P18_4_SCB4_SPI_CLK = 25, /* Digital Active - scb[4].spi_clk:0 */ 2220 P18_4_SCB4_UART_RX = 26, /* Digital Active - scb[4].uart_rx:0 */ 2221 P18_4_SCB4_I2C_SDA = 27, /* Digital Active - scb[4].i2c_sda:0 */ 2222 2223 /* P18.5 */ 2224 P18_5_GPIO = 0, /* GPIO controls 'out' */ 2225 P18_5_AMUXA = 4, /* Analog mux bus A */ 2226 P18_5_AMUXB = 5, /* Analog mux bus B */ 2227 P18_5_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:1 */ 2228 P18_5_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:1 */ 2229 P18_5_TCPWM0_TR_ONE_CNT_IN35 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[35]:1 */ 2230 P18_5_VIDEOSS0_TTL_CAP0_DATA8 = 21, /* Digital Active - videoss[0].ttl_cap0_data[8]:2 */ 2231 P18_5_VIDEOSS0_TTL_CAP0_DATA15 = 23, /* Digital Active - videoss[0].ttl_cap0_data[15]:0 */ 2232 P18_5_VIDEOSS0_TTL_DSP1_DATA_A13 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[3]:0 */ 2233 P18_5_SCB4_SPI_MOSI = 25, /* Digital Active - scb[4].spi_mosi:0 */ 2234 P18_5_SCB4_UART_TX = 26, /* Digital Active - scb[4].uart_tx:0 */ 2235 P18_5_SCB4_I2C_SCL = 27, /* Digital Active - scb[4].i2c_scl:0 */ 2236 2237 /* P18.6 */ 2238 P18_6_GPIO = 0, /* GPIO controls 'out' */ 2239 P18_6_AMUXA = 4, /* Analog mux bus A */ 2240 P18_6_AMUXB = 5, /* Analog mux bus B */ 2241 P18_6_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:4 */ 2242 P18_6_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:1 */ 2243 P18_6_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:1 */ 2244 P18_6_VIDEOSS0_TTL_CAP0_DATA16 = 21, /* Digital Active - videoss[0].ttl_cap0_data[16]:0 */ 2245 P18_6_VIDEOSS0_TTL_CAP0_DATA7 = 23, /* Digital Active - videoss[0].ttl_cap0_data[7]:1 */ 2246 P18_6_VIDEOSS0_TTL_DSP1_DATA_A04 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[4]:0 */ 2247 P18_6_SCB4_SPI_MISO = 25, /* Digital Active - scb[4].spi_miso:0 */ 2248 P18_6_SCB4_UART_RTS = 26, /* Digital Active - scb[4].uart_rts:0 */ 2249 2250 /* P18.7 */ 2251 P18_7_GPIO = 0, /* GPIO controls 'out' */ 2252 P18_7_AMUXA = 4, /* Analog mux bus A */ 2253 P18_7_AMUXB = 5, /* Analog mux bus B */ 2254 P18_7_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:4 */ 2255 P18_7_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:4 */ 2256 P18_7_TCPWM0_TR_ONE_CNT_IN37 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:1 */ 2257 P18_7_VIDEOSS0_TTL_CAP0_DATA6 = 21, /* Digital Active - videoss[0].ttl_cap0_data[6]:1 */ 2258 P18_7_VIDEOSS0_TTL_CAP0_DATA17 = 23, /* Digital Active - videoss[0].ttl_cap0_data[17]:0 */ 2259 P18_7_VIDEOSS0_TTL_DSP1_DATA_A14 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[4]:0 */ 2260 P18_7_SCB4_SPI_SELECT0 = 25, /* Digital Active - scb[4].spi_select0:0 */ 2261 P18_7_SCB4_UART_CTS = 26, /* Digital Active - scb[4].uart_cts:0 */ 2262 2263 /* P19.0 */ 2264 P19_0_GPIO = 0, /* GPIO controls 'out' */ 2265 P19_0_AMUXA = 4, /* Analog mux bus A */ 2266 P19_0_AMUXB = 5, /* Analog mux bus B */ 2267 P19_0_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:4 */ 2268 P19_0_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:4 */ 2269 P19_0_TCPWM0_TR_ONE_CNT_IN20 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[20]:4 */ 2270 P19_0_VIDEOSS0_TTL_CAP0_DATA18 = 21, /* Digital Active - videoss[0].ttl_cap0_data[18]:0 */ 2271 P19_0_VIDEOSS0_TTL_CAP0_DATA5 = 23, /* Digital Active - videoss[0].ttl_cap0_data[5]:1 */ 2272 P19_0_VIDEOSS0_TTL_DSP1_DATA_A05 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[5]:0 */ 2273 P19_0_SCB3_SPI_SELECT1 = 25, /* Digital Active - scb[3].spi_select1:0 */ 2274 2275 /* P19.1 */ 2276 P19_1_GPIO = 0, /* GPIO controls 'out' */ 2277 P19_1_AMUXA = 4, /* Analog mux bus A */ 2278 P19_1_AMUXB = 5, /* Analog mux bus B */ 2279 P19_1_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:4 */ 2280 P19_1_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:4 */ 2281 P19_1_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:4 */ 2282 P19_1_VIDEOSS0_TTL_CAP0_DATA4 = 21, /* Digital Active - videoss[0].ttl_cap0_data[4]:1 */ 2283 P19_1_VIDEOSS0_TTL_CAP0_DATA19 = 23, /* Digital Active - videoss[0].ttl_cap0_data[19]:0 */ 2284 P19_1_VIDEOSS0_TTL_DSP1_DATA_A15 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[5]:0 */ 2285 P19_1_SCB4_SPI_SELECT1 = 25, /* Digital Active - scb[4].spi_select1:0 */ 2286 2287 /* P19.2 */ 2288 P19_2_GPIO = 0, /* GPIO controls 'out' */ 2289 P19_2_AMUXA = 4, /* Analog mux bus A */ 2290 P19_2_AMUXB = 5, /* Analog mux bus B */ 2291 P19_2_TCPWM0_LINE24 = 8, /* Digital Active - tcpwm[0].line[24]:4 */ 2292 P19_2_TCPWM0_LINE_COMPL23 = 9, /* Digital Active - tcpwm[0].line_compl[23]:4 */ 2293 P19_2_TCPWM0_TR_ONE_CNT_IN22 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[22]:4 */ 2294 P19_2_VIDEOSS0_TTL_CAP0_DATA20 = 21, /* Digital Active - videoss[0].ttl_cap0_data[20]:0 */ 2295 P19_2_VIDEOSS0_TTL_CAP0_DATA3 = 23, /* Digital Active - videoss[0].ttl_cap0_data[3]:1 */ 2296 P19_2_VIDEOSS0_TTL_DSP1_DATA_A06 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[6]:0 */ 2297 P19_2_SCB5_SPI_CLK = 25, /* Digital Active - scb[5].spi_clk:0 */ 2298 P19_2_SCB5_UART_RX = 26, /* Digital Active - scb[5].uart_rx:0 */ 2299 P19_2_SCB5_I2C_SDA = 27, /* Digital Active - scb[5].i2c_sda:0 */ 2300 2301 /* P19.3 */ 2302 P19_3_GPIO = 0, /* GPIO controls 'out' */ 2303 P19_3_AMUXA = 4, /* Analog mux bus A */ 2304 P19_3_AMUXB = 5, /* Analog mux bus B */ 2305 P19_3_TCPWM0_LINE25 = 8, /* Digital Active - tcpwm[0].line[25]:4 */ 2306 P19_3_TCPWM0_LINE_COMPL24 = 9, /* Digital Active - tcpwm[0].line_compl[24]:4 */ 2307 P19_3_TCPWM0_TR_ONE_CNT_IN23 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[23]:4 */ 2308 P19_3_VIDEOSS0_TTL_CAP0_DATA2 = 21, /* Digital Active - videoss[0].ttl_cap0_data[2]:1 */ 2309 P19_3_VIDEOSS0_TTL_CAP0_DATA21 = 23, /* Digital Active - videoss[0].ttl_cap0_data[21]:0 */ 2310 P19_3_VIDEOSS0_TTL_DSP1_DATA_A16 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[6]:0 */ 2311 P19_3_SCB5_SPI_MOSI = 25, /* Digital Active - scb[5].spi_mosi:0 */ 2312 P19_3_SCB5_UART_TX = 26, /* Digital Active - scb[5].uart_tx:0 */ 2313 P19_3_SCB5_I2C_SCL = 27, /* Digital Active - scb[5].i2c_scl:0 */ 2314 2315 /* P19.4 */ 2316 P19_4_GPIO = 0, /* GPIO controls 'out' */ 2317 P19_4_AMUXA = 4, /* Analog mux bus A */ 2318 P19_4_AMUXB = 5, /* Analog mux bus B */ 2319 P19_4_TCPWM0_LINE26 = 8, /* Digital Active - tcpwm[0].line[26]:4 */ 2320 P19_4_TCPWM0_LINE_COMPL25 = 9, /* Digital Active - tcpwm[0].line_compl[25]:4 */ 2321 P19_4_TCPWM0_TR_ONE_CNT_IN24 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[24]:4 */ 2322 P19_4_VIDEOSS0_TTL_CAP0_DATA22 = 21, /* Digital Active - videoss[0].ttl_cap0_data[22]:0 */ 2323 P19_4_VIDEOSS0_TTL_CAP0_DATA1 = 23, /* Digital Active - videoss[0].ttl_cap0_data[1]:1 */ 2324 P19_4_VIDEOSS0_TTL_DSP1_DATA_A07 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[7]:0 */ 2325 P19_4_SCB5_SPI_MISO = 25, /* Digital Active - scb[5].spi_miso:0 */ 2326 P19_4_SCB5_UART_RTS = 26, /* Digital Active - scb[5].uart_rts:0 */ 2327 2328 /* P19.5 */ 2329 P19_5_GPIO = 0, /* GPIO controls 'out' */ 2330 P19_5_AMUXA = 4, /* Analog mux bus A */ 2331 P19_5_AMUXB = 5, /* Analog mux bus B */ 2332 P19_5_TCPWM0_LINE27 = 8, /* Digital Active - tcpwm[0].line[27]:4 */ 2333 P19_5_TCPWM0_LINE_COMPL26 = 9, /* Digital Active - tcpwm[0].line_compl[26]:4 */ 2334 P19_5_TCPWM0_TR_ONE_CNT_IN25 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[25]:4 */ 2335 P19_5_VIDEOSS0_TTL_CAP0_DATA0 = 21, /* Digital Active - videoss[0].ttl_cap0_data[0]:1 */ 2336 P19_5_VIDEOSS0_TTL_CAP0_DATA23 = 23, /* Digital Active - videoss[0].ttl_cap0_data[23]:0 */ 2337 P19_5_VIDEOSS0_TTL_DSP1_DATA_A17 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[7]:0 */ 2338 P19_5_SCB5_SPI_SELECT0 = 25, /* Digital Active - scb[5].spi_select0:0 */ 2339 P19_5_SCB5_UART_CTS = 26, /* Digital Active - scb[5].uart_cts:0 */ 2340 2341 /* P19.6 */ 2342 P19_6_GPIO = 0, /* GPIO controls 'out' */ 2343 P19_6_AMUXA = 4, /* Analog mux bus A */ 2344 P19_6_AMUXB = 5, /* Analog mux bus B */ 2345 P19_6_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:4 */ 2346 P19_6_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:4 */ 2347 P19_6_TCPWM0_TR_ONE_CNT_IN26 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[26]:4 */ 2348 P19_6_VIDEOSS0_TTL_CAP0_DATA24 = 21, /* Digital Active - videoss[0].ttl_cap0_data[24]:0 */ 2349 P19_6_VIDEOSS0_TTL_DSP1_DATA_A08 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[8]:0 */ 2350 P19_6_SCB5_SPI_SELECT1 = 25, /* Digital Active - scb[5].spi_select1:0 */ 2351 2352 /* P19.7 */ 2353 P19_7_GPIO = 0, /* GPIO controls 'out' */ 2354 P19_7_AMUXA = 4, /* Analog mux bus A */ 2355 P19_7_AMUXB = 5, /* Analog mux bus B */ 2356 P19_7_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:4 */ 2357 P19_7_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:4 */ 2358 P19_7_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:4 */ 2359 P19_7_VIDEOSS0_TTL_CAP0_DATA25 = 23, /* Digital Active - videoss[0].ttl_cap0_data[25]:0 */ 2360 P19_7_VIDEOSS0_TTL_DSP1_DATA_A18 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[8]:0 */ 2361 P19_7_PERI_TR_IO_INPUT1 = 27, /* Digital Active - peri.tr_io_input[1]:0 */ 2362 2363 /* P20.0 */ 2364 P20_0_GPIO = 0, /* GPIO controls 'out' */ 2365 P20_0_AMUXA = 4, /* Analog mux bus A */ 2366 P20_0_AMUXB = 5, /* Analog mux bus B */ 2367 P20_0_TCPWM0_LINE30 = 8, /* Digital Active - tcpwm[0].line[30]:3 */ 2368 P20_0_TCPWM0_LINE_COMPL29 = 9, /* Digital Active - tcpwm[0].line_compl[29]:4 */ 2369 P20_0_TCPWM0_TR_ONE_CNT_IN28 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[28]:4 */ 2370 P20_0_VIDEOSS0_TTL_CAP0_DATA26 = 21, /* Digital Active - videoss[0].ttl_cap0_data[26]:0 */ 2371 P20_0_VIDEOSS0_TTL_DSP1_DATA_A09 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[9]:0 */ 2372 P20_0_PERI_TR_IO_INPUT2 = 27, /* Digital Active - peri.tr_io_input[2]:0 */ 2373 2374 /* P20.1 */ 2375 P20_1_GPIO = 0, /* GPIO controls 'out' */ 2376 P20_1_AMUXA = 4, /* Analog mux bus A */ 2377 P20_1_AMUXB = 5, /* Analog mux bus B */ 2378 P20_1_TCPWM0_LINE31 = 8, /* Digital Active - tcpwm[0].line[31]:3 */ 2379 P20_1_TCPWM0_LINE_COMPL30 = 9, /* Digital Active - tcpwm[0].line_compl[30]:3 */ 2380 P20_1_TCPWM0_TR_ONE_CNT_IN29 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[29]:4 */ 2381 P20_1_VIDEOSS0_TTL_CAP0_CLK = 23, /* Digital Active - videoss[0].ttl_cap0_clk:1 */ 2382 P20_1_VIDEOSS0_TTL_DSP1_DATA_A19 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[9]:0 */ 2383 P20_1_PERI_TR_IO_INPUT3 = 27, /* Digital Active - peri.tr_io_input[3]:0 */ 2384 2385 /* P20.2 */ 2386 P20_2_GPIO = 0, /* GPIO controls 'out' */ 2387 P20_2_AMUXA = 4, /* Analog mux bus A */ 2388 P20_2_AMUXB = 5, /* Analog mux bus B */ 2389 P20_2_TCPWM0_LINE32 = 8, /* Digital Active - tcpwm[0].line[32]:3 */ 2390 P20_2_TCPWM0_LINE_COMPL31 = 9, /* Digital Active - tcpwm[0].line_compl[31]:3 */ 2391 P20_2_TCPWM0_TR_ONE_CNT_IN30 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[30]:3 */ 2392 P20_2_TDM0_TDM_TX_MCK0 = 16, /* Digital Active - tdm[0].tdm_tx_mck[0]:0 */ 2393 P20_2_TDM0_TDM_RX_MCK0 = 17, /* Digital Active - tdm[0].tdm_rx_mck[0]:0 */ 2394 P20_2_TDM0_TDM_RX_MCK1 = 18, /* Digital Active - tdm[0].tdm_rx_mck[1]:0 */ 2395 P20_2_VIDEOSS0_TTL_DSP1_DATA_A010 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[10]:0 */ 2396 P20_2_PERI_TR_IO_INPUT4 = 27, /* Digital Active - peri.tr_io_input[4]:0 */ 2397 2398 /* P20.3 */ 2399 P20_3_GPIO = 0, /* GPIO controls 'out' */ 2400 P20_3_AMUXA = 4, /* Analog mux bus A */ 2401 P20_3_AMUXB = 5, /* Analog mux bus B */ 2402 P20_3_TCPWM0_LINE33 = 8, /* Digital Active - tcpwm[0].line[33]:3 */ 2403 P20_3_TCPWM0_LINE_COMPL32 = 9, /* Digital Active - tcpwm[0].line_compl[32]:3 */ 2404 P20_3_TCPWM0_TR_ONE_CNT_IN31 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[31]:3 */ 2405 P20_3_TDM0_TDM_TX_SCK0 = 16, /* Digital Active - tdm[0].tdm_tx_sck[0]:0 */ 2406 P20_3_TDM0_TDM_RX_SCK0 = 17, /* Digital Active - tdm[0].tdm_rx_sck[0]:0 */ 2407 P20_3_TDM0_TDM_RX_SCK1 = 18, /* Digital Active - tdm[0].tdm_rx_sck[1]:0 */ 2408 P20_3_VIDEOSS0_TTL_DSP1_DATA_A110 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[10]:0 */ 2409 P20_3_PERI_TR_IO_INPUT5 = 27, /* Digital Active - peri.tr_io_input[5]:0 */ 2410 2411 /* P20.4 */ 2412 P20_4_GPIO = 0, /* GPIO controls 'out' */ 2413 P20_4_AMUXA = 4, /* Analog mux bus A */ 2414 P20_4_AMUXB = 5, /* Analog mux bus B */ 2415 P20_4_TCPWM0_LINE34 = 8, /* Digital Active - tcpwm[0].line[34]:2 */ 2416 P20_4_TCPWM0_LINE_COMPL33 = 9, /* Digital Active - tcpwm[0].line_compl[33]:3 */ 2417 P20_4_TCPWM0_TR_ONE_CNT_IN32 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[32]:3 */ 2418 P20_4_TDM0_TDM_TX_FSYNC0 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[0]:0 */ 2419 P20_4_TDM0_TDM_RX_FSYNC0 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[0]:0 */ 2420 P20_4_TDM0_TDM_RX_FSYNC1 = 18, /* Digital Active - tdm[0].tdm_rx_fsync[1]:0 */ 2421 P20_4_VIDEOSS0_TTL_DSP1_DATA_A011 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a0[11]:0 */ 2422 P20_4_PERI_TR_IO_INPUT6 = 27, /* Digital Active - peri.tr_io_input[6]:0 */ 2423 2424 /* P20.5 */ 2425 P20_5_GPIO = 0, /* GPIO controls 'out' */ 2426 P20_5_AMUXA = 4, /* Analog mux bus A */ 2427 P20_5_AMUXB = 5, /* Analog mux bus B */ 2428 P20_5_TCPWM0_LINE35 = 8, /* Digital Active - tcpwm[0].line[35]:2 */ 2429 P20_5_TCPWM0_LINE_COMPL34 = 9, /* Digital Active - tcpwm[0].line_compl[34]:2 */ 2430 P20_5_TCPWM0_TR_ONE_CNT_IN33 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[33]:3 */ 2431 P20_5_TDM0_TDM_TX_SD0 = 16, /* Digital Active - tdm[0].tdm_tx_sd[0]:0 */ 2432 P20_5_TDM0_TDM_RX_SD0 = 17, /* Digital Active - tdm[0].tdm_rx_sd[0]:0 */ 2433 P20_5_TDM0_TDM_RX_SD1 = 18, /* Digital Active - tdm[0].tdm_rx_sd[1]:0 */ 2434 P20_5_VIDEOSS0_TTL_DSP1_DATA_A111 = 24, /* Digital Active - videoss[0].ttl_dsp1_data_a1[11]:0 */ 2435 P20_5_SCB2_SPI_SELECT1 = 25, /* Digital Active - scb[2].spi_select1:0 */ 2436 P20_5_PERI_TR_IO_INPUT7 = 27, /* Digital Active - peri.tr_io_input[7]:0 */ 2437 2438 /* P20.6 */ 2439 P20_6_GPIO = 0, /* GPIO controls 'out' */ 2440 P20_6_AMUXA = 4, /* Analog mux bus A */ 2441 P20_6_AMUXB = 5, /* Analog mux bus B */ 2442 P20_6_TCPWM0_LINE36 = 8, /* Digital Active - tcpwm[0].line[36]:2 */ 2443 P20_6_TCPWM0_LINE_COMPL35 = 9, /* Digital Active - tcpwm[0].line_compl[35]:2 */ 2444 P20_6_TCPWM0_TR_ONE_CNT_IN34 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[34]:2 */ 2445 P20_6_TDM0_TDM_TX_MCK1 = 16, /* Digital Active - tdm[0].tdm_tx_mck[1]:0 */ 2446 P20_6_TDM0_TDM_RX_MCK0 = 17, /* Digital Active - tdm[0].tdm_rx_mck[0]:1 */ 2447 P20_6_TDM0_TDM_RX_MCK1 = 18, /* Digital Active - tdm[0].tdm_rx_mck[1]:1 */ 2448 P20_6_VIDEOSS0_TTL_DSP1_CONTROL0 = 24, /* Digital Active - videoss[0].ttl_dsp1_control[0]:0 */ 2449 P20_6_SCB2_SPI_SELECT0 = 25, /* Digital Active - scb[2].spi_select0:0 */ 2450 P20_6_SCB2_UART_CTS = 26, /* Digital Active - scb[2].uart_cts:0 */ 2451 P20_6_PERI_TR_IO_INPUT8 = 27, /* Digital Active - peri.tr_io_input[8]:0 */ 2452 2453 /* P20.7 */ 2454 P20_7_GPIO = 0, /* GPIO controls 'out' */ 2455 P20_7_AMUXA = 4, /* Analog mux bus A */ 2456 P20_7_AMUXB = 5, /* Analog mux bus B */ 2457 P20_7_TCPWM0_LINE37 = 8, /* Digital Active - tcpwm[0].line[37]:2 */ 2458 P20_7_TCPWM0_LINE_COMPL36 = 9, /* Digital Active - tcpwm[0].line_compl[36]:2 */ 2459 P20_7_TCPWM0_TR_ONE_CNT_IN35 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[35]:2 */ 2460 P20_7_TDM0_TDM_TX_SCK1 = 16, /* Digital Active - tdm[0].tdm_tx_sck[1]:0 */ 2461 P20_7_TDM0_TDM_RX_SCK0 = 17, /* Digital Active - tdm[0].tdm_rx_sck[0]:1 */ 2462 P20_7_TDM0_TDM_RX_SCK1 = 18, /* Digital Active - tdm[0].tdm_rx_sck[1]:1 */ 2463 P20_7_VIDEOSS0_TTL_DSP1_CONTROL1 = 24, /* Digital Active - videoss[0].ttl_dsp1_control[1]:0 */ 2464 P20_7_SCB2_SPI_MISO = 25, /* Digital Active - scb[2].spi_miso:0 */ 2465 P20_7_SCB2_UART_RTS = 26, /* Digital Active - scb[2].uart_rts:0 */ 2466 P20_7_PERI_TR_IO_INPUT9 = 27, /* Digital Active - peri.tr_io_input[9]:0 */ 2467 2468 /* P21.0 */ 2469 P21_0_GPIO = 0, /* GPIO controls 'out' */ 2470 P21_0_AMUXA = 4, /* Analog mux bus A */ 2471 P21_0_AMUXB = 5, /* Analog mux bus B */ 2472 P21_0_TCPWM0_LINE20 = 8, /* Digital Active - tcpwm[0].line[20]:5 */ 2473 P21_0_TCPWM0_LINE_COMPL37 = 9, /* Digital Active - tcpwm[0].line_compl[37]:2 */ 2474 P21_0_TCPWM0_TR_ONE_CNT_IN36 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[36]:2 */ 2475 P21_0_TDM0_TDM_TX_FSYNC1 = 16, /* Digital Active - tdm[0].tdm_tx_fsync[1]:0 */ 2476 P21_0_TDM0_TDM_RX_FSYNC0 = 17, /* Digital Active - tdm[0].tdm_rx_fsync[0]:1 */ 2477 P21_0_TDM0_TDM_RX_FSYNC1 = 18, /* Digital Active - tdm[0].tdm_rx_fsync[1]:1 */ 2478 P21_0_VIDEOSS0_TTL_DSP1_CONTROL2 = 24, /* Digital Active - videoss[0].ttl_dsp1_control[2]:0 */ 2479 P21_0_SCB2_SPI_CLK = 25, /* Digital Active - scb[2].spi_clk:0 */ 2480 P21_0_SCB2_UART_RX = 26, /* Digital Active - scb[2].uart_rx:0 */ 2481 P21_0_SCB2_I2C_SDA = 27, /* Digital Active - scb[2].i2c_sda:0 */ 2482 2483 /* P21.1 */ 2484 P21_1_GPIO = 0, /* GPIO controls 'out' */ 2485 P21_1_AMUXA = 4, /* Analog mux bus A */ 2486 P21_1_AMUXB = 5, /* Analog mux bus B */ 2487 P21_1_TCPWM0_LINE21 = 8, /* Digital Active - tcpwm[0].line[21]:5 */ 2488 P21_1_TCPWM0_LINE_COMPL20 = 9, /* Digital Active - tcpwm[0].line_compl[20]:5 */ 2489 P21_1_TCPWM0_TR_ONE_CNT_IN37 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[37]:2 */ 2490 P21_1_TDM0_TDM_TX_SD1 = 16, /* Digital Active - tdm[0].tdm_tx_sd[1]:0 */ 2491 P21_1_TDM0_TDM_RX_SD0 = 17, /* Digital Active - tdm[0].tdm_rx_sd[0]:1 */ 2492 P21_1_TDM0_TDM_RX_SD1 = 18, /* Digital Active - tdm[0].tdm_rx_sd[1]:1 */ 2493 P21_1_VIDEOSS0_TTL_DSP1_CLOCK = 24, /* Digital Active - videoss[0].ttl_dsp1_clock:0 */ 2494 P21_1_SCB2_SPI_MOSI = 25, /* Digital Active - scb[2].spi_mosi:0 */ 2495 P21_1_SCB2_UART_TX = 26, /* Digital Active - scb[2].uart_tx:0 */ 2496 P21_1_SCB2_I2C_SCL = 27, /* Digital Active - scb[2].i2c_scl:0 */ 2497 2498 /* P21.2 */ 2499 P21_2_GPIO = 0, /* GPIO controls 'out' */ 2500 P21_2_AMUXA = 4, /* Analog mux bus A */ 2501 P21_2_AMUXB = 5, /* Analog mux bus B */ 2502 P21_2_TCPWM0_LINE22 = 8, /* Digital Active - tcpwm[0].line[22]:5 */ 2503 P21_2_TCPWM0_LINE_COMPL21 = 9, /* Digital Active - tcpwm[0].line_compl[21]:5 */ 2504 P21_2_TCPWM0_TR_ONE_CNT_IN20 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[20]:5 */ 2505 P21_2_PWM0_PWM_LINE1_P0 = 24, /* Digital Active - pwm[0].pwm_line1_p[0]:2 */ 2506 P21_2_CANFD1_TTCAN_TX0 = 25, /* Digital Active - canfd[1].ttcan_tx[0]:0 */ 2507 2508 /* P21.3 */ 2509 P21_3_GPIO = 0, /* GPIO controls 'out' */ 2510 P21_3_AMUXA = 4, /* Analog mux bus A */ 2511 P21_3_AMUXB = 5, /* Analog mux bus B */ 2512 P21_3_TCPWM0_LINE23 = 8, /* Digital Active - tcpwm[0].line[23]:5 */ 2513 P21_3_TCPWM0_LINE_COMPL22 = 9, /* Digital Active - tcpwm[0].line_compl[22]:5 */ 2514 P21_3_TCPWM0_TR_ONE_CNT_IN21 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[21]:5 */ 2515 P21_3_PWM0_PWM_LINE1_N0 = 24, /* Digital Active - pwm[0].pwm_line1_n[0]:2 */ 2516 P21_3_CANFD1_TTCAN_RX0 = 25, /* Digital Active - canfd[1].ttcan_rx[0]:0 */ 2517 2518 /* P23.0 */ 2519 P23_0_GPIO = 0, /* GPIO controls 'out' */ 2520 P23_0_AMUXA = 4, /* Analog mux bus A */ 2521 P23_0_AMUXB = 5, /* Analog mux bus B */ 2522 P23_0_SMIF0_SMIF0_SPIHB_DATA4 = 27, /* Digital Active - smif[0].smif0_spihb_data4 */ 2523 2524 /* P23.1 */ 2525 P23_1_GPIO = 0, /* GPIO controls 'out' */ 2526 P23_1_AMUXA = 4, /* Analog mux bus A */ 2527 P23_1_AMUXB = 5, /* Analog mux bus B */ 2528 P23_1_SMIF0_SMIF0_SPIHB_DATA2 = 27, /* Digital Active - smif[0].smif0_spihb_data2 */ 2529 2530 /* P23.2 */ 2531 P23_2_GPIO = 0, /* GPIO controls 'out' */ 2532 P23_2_AMUXA = 4, /* Analog mux bus A */ 2533 P23_2_AMUXB = 5, /* Analog mux bus B */ 2534 P23_2_SMIF0_SMIF0_SPIHB_DATA3 = 27, /* Digital Active - smif[0].smif0_spihb_data3 */ 2535 2536 /* P23.3 */ 2537 P23_3_GPIO = 0, /* GPIO controls 'out' */ 2538 P23_3_AMUXA = 4, /* Analog mux bus A */ 2539 P23_3_AMUXB = 5, /* Analog mux bus B */ 2540 P23_3_SMIF0_SMIF0_SPIHB_DATA5 = 27, /* Digital Active - smif[0].smif0_spihb_data5 */ 2541 2542 /* P23.4 */ 2543 P23_4_GPIO = 0, /* GPIO controls 'out' */ 2544 P23_4_AMUXA = 4, /* Analog mux bus A */ 2545 P23_4_AMUXB = 5, /* Analog mux bus B */ 2546 P23_4_SMIF0_SMIF0_SPIHB_RWDS = 27, /* Digital Active - smif[0].smif0_spihb_rwds */ 2547 2548 /* P24.0 */ 2549 P24_0_GPIO = 0, /* GPIO controls 'out' */ 2550 P24_0_AMUXA = 4, /* Analog mux bus A */ 2551 P24_0_AMUXB = 5, /* Analog mux bus B */ 2552 P24_0_SMIF0_SMIF0_SPIHB_CLK = 27, /* Digital Active - smif[0].smif0_spihb_clk:0 */ 2553 2554 /* P24.1 */ 2555 P24_1_GPIO = 0, /* GPIO controls 'out' */ 2556 P24_1_AMUXA = 4, /* Analog mux bus A */ 2557 P24_1_AMUXB = 5, /* Analog mux bus B */ 2558 P24_1_SMIF0_SMIF0_SPIHB_CLK = 27, /* Digital Active - smif[0].smif0_spihb_clk:1 */ 2559 2560 /* P25.0 */ 2561 P25_0_GPIO = 0, /* GPIO controls 'out' */ 2562 P25_0_AMUXA = 4, /* Analog mux bus A */ 2563 P25_0_AMUXB = 5, /* Analog mux bus B */ 2564 P25_0_SMIF0_SMIF0_SPIHB_DATA0 = 27, /* Digital Active - smif[0].smif0_spihb_data0 */ 2565 2566 /* P25.1 */ 2567 P25_1_GPIO = 0, /* GPIO controls 'out' */ 2568 P25_1_AMUXA = 4, /* Analog mux bus A */ 2569 P25_1_AMUXB = 5, /* Analog mux bus B */ 2570 P25_1_SMIF0_SMIF0_SPIHB_DATA6 = 27, /* Digital Active - smif[0].smif0_spihb_data6 */ 2571 2572 /* P25.2 */ 2573 P25_2_GPIO = 0, /* GPIO controls 'out' */ 2574 P25_2_AMUXA = 4, /* Analog mux bus A */ 2575 P25_2_AMUXB = 5, /* Analog mux bus B */ 2576 P25_2_SMIF0_SMIF0_SPIHB_SELECT0 = 27, /* Digital Active - smif[0].smif0_spihb_select0 */ 2577 2578 /* P25.3 */ 2579 P25_3_GPIO = 0, /* GPIO controls 'out' */ 2580 P25_3_AMUXA = 4, /* Analog mux bus A */ 2581 P25_3_AMUXB = 5, /* Analog mux bus B */ 2582 P25_3_SMIF0_SMIF0_SPIHB_DATA1 = 27, /* Digital Active - smif[0].smif0_spihb_data1 */ 2583 2584 /* P25.4 */ 2585 P25_4_GPIO = 0, /* GPIO controls 'out' */ 2586 P25_4_AMUXA = 4, /* Analog mux bus A */ 2587 P25_4_AMUXB = 5, /* Analog mux bus B */ 2588 P25_4_SMIF0_SMIF0_SPIHB_DATA7 = 27, /* Digital Active - smif[0].smif0_spihb_data7 */ 2589 2590 /* P25.5 */ 2591 P25_5_GPIO = 0, /* GPIO controls 'out' */ 2592 P25_5_AMUXA = 4, /* Analog mux bus A */ 2593 P25_5_AMUXB = 5, /* Analog mux bus B */ 2594 P25_5_SMIF0_SMIF0_SPIHB_SELECT1 = 27, /* Digital Active - smif[0].smif0_spihb_select1 */ 2595 2596 /* P26.0 */ 2597 P26_0_GPIO = 0, /* GPIO controls 'out' */ 2598 P26_0_AMUXA = 4, /* Analog mux bus A */ 2599 P26_0_AMUXB = 5, /* Analog mux bus B */ 2600 P26_0_SMIF0_SMIF1_SPIHB_DATA4 = 27, /* Digital Active - smif[0].smif1_spihb_data4 */ 2601 2602 /* P26.1 */ 2603 P26_1_GPIO = 0, /* GPIO controls 'out' */ 2604 P26_1_AMUXA = 4, /* Analog mux bus A */ 2605 P26_1_AMUXB = 5, /* Analog mux bus B */ 2606 P26_1_SMIF0_SMIF1_SPIHB_DATA2 = 27, /* Digital Active - smif[0].smif1_spihb_data2 */ 2607 2608 /* P26.2 */ 2609 P26_2_GPIO = 0, /* GPIO controls 'out' */ 2610 P26_2_AMUXA = 4, /* Analog mux bus A */ 2611 P26_2_AMUXB = 5, /* Analog mux bus B */ 2612 P26_2_SMIF0_SMIF1_SPIHB_DATA3 = 27, /* Digital Active - smif[0].smif1_spihb_data3 */ 2613 2614 /* P26.3 */ 2615 P26_3_GPIO = 0, /* GPIO controls 'out' */ 2616 P26_3_AMUXA = 4, /* Analog mux bus A */ 2617 P26_3_AMUXB = 5, /* Analog mux bus B */ 2618 P26_3_SMIF0_SMIF1_SPIHB_DATA5 = 27, /* Digital Active - smif[0].smif1_spihb_data5 */ 2619 2620 /* P26.4 */ 2621 P26_4_GPIO = 0, /* GPIO controls 'out' */ 2622 P26_4_AMUXA = 4, /* Analog mux bus A */ 2623 P26_4_AMUXB = 5, /* Analog mux bus B */ 2624 P26_4_SMIF0_SMIF1_SPIHB_RWDS = 27, /* Digital Active - smif[0].smif1_spihb_rwds */ 2625 2626 /* P27.0 */ 2627 P27_0_GPIO = 0, /* GPIO controls 'out' */ 2628 P27_0_AMUXA = 4, /* Analog mux bus A */ 2629 P27_0_AMUXB = 5, /* Analog mux bus B */ 2630 P27_0_SMIF0_SMIF1_SPIHB_CLK = 27, /* Digital Active - smif[0].smif1_spihb_clk:0 */ 2631 2632 /* P27.1 */ 2633 P27_1_GPIO = 0, /* GPIO controls 'out' */ 2634 P27_1_AMUXA = 4, /* Analog mux bus A */ 2635 P27_1_AMUXB = 5, /* Analog mux bus B */ 2636 P27_1_SMIF0_SMIF1_SPIHB_CLK = 27, /* Digital Active - smif[0].smif1_spihb_clk:1 */ 2637 2638 /* P28.0 */ 2639 P28_0_GPIO = 0, /* GPIO controls 'out' */ 2640 P28_0_AMUXA = 4, /* Analog mux bus A */ 2641 P28_0_AMUXB = 5, /* Analog mux bus B */ 2642 P28_0_SMIF0_SMIF1_SPIHB_DATA0 = 27, /* Digital Active - smif[0].smif1_spihb_data0 */ 2643 2644 /* P28.1 */ 2645 P28_1_GPIO = 0, /* GPIO controls 'out' */ 2646 P28_1_AMUXA = 4, /* Analog mux bus A */ 2647 P28_1_AMUXB = 5, /* Analog mux bus B */ 2648 P28_1_SMIF0_SMIF1_SPIHB_DATA6 = 27, /* Digital Active - smif[0].smif1_spihb_data6 */ 2649 2650 /* P28.2 */ 2651 P28_2_GPIO = 0, /* GPIO controls 'out' */ 2652 P28_2_AMUXA = 4, /* Analog mux bus A */ 2653 P28_2_AMUXB = 5, /* Analog mux bus B */ 2654 P28_2_SMIF0_SMIF1_SPIHB_SELECT0 = 27, /* Digital Active - smif[0].smif1_spihb_select0 */ 2655 2656 /* P28.3 */ 2657 P28_3_GPIO = 0, /* GPIO controls 'out' */ 2658 P28_3_AMUXA = 4, /* Analog mux bus A */ 2659 P28_3_AMUXB = 5, /* Analog mux bus B */ 2660 P28_3_SMIF0_SMIF1_SPIHB_DATA1 = 27, /* Digital Active - smif[0].smif1_spihb_data1 */ 2661 2662 /* P28.4 */ 2663 P28_4_GPIO = 0, /* GPIO controls 'out' */ 2664 P28_4_AMUXA = 4, /* Analog mux bus A */ 2665 P28_4_AMUXB = 5, /* Analog mux bus B */ 2666 P28_4_SMIF0_SMIF1_SPIHB_DATA7 = 27, /* Digital Active - smif[0].smif1_spihb_data7 */ 2667 2668 /* P28.5 */ 2669 P28_5_GPIO = 0, /* GPIO controls 'out' */ 2670 P28_5_AMUXA = 4, /* Analog mux bus A */ 2671 P28_5_AMUXB = 5, /* Analog mux bus B */ 2672 P28_5_SMIF0_SMIF1_SPIHB_SELECT1 = 27, /* Digital Active - smif[0].smif1_spihb_select1 */ 2673 2674 /* P29.0 */ 2675 P29_0_GPIO = 0, /* GPIO controls 'out' */ 2676 P29_0_AMUXA = 4, /* Analog mux bus A */ 2677 P29_0_AMUXB = 5, /* Analog mux bus B */ 2678 P29_0_TCPWM0_LINE28 = 8, /* Digital Active - tcpwm[0].line[28]:2 */ 2679 P29_0_TCPWM0_LINE_COMPL27 = 9, /* Digital Active - tcpwm[0].line_compl[27]:2 */ 2680 P29_0_TCPWM0_TR_ONE_CNT_IN26 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[26]:2 */ 2681 P29_0_PASS0_SAR_EXT_MUX_SEL2 = 16, /* Digital Active - pass[0].sar_ext_mux_sel[2] */ 2682 P29_0_CPUSS_CLK_FM_PUMP = 22, /* Digital Active - cpuss.clk_fm_pump */ 2683 P29_0_PWM0_PWM_LINE2_N1 = 24, /* Digital Active - pwm[0].pwm_line2_n[1]:1 */ 2684 P29_0_SCB9_SPI_CLK = 25, /* Digital Active - scb[9].spi_clk:0 */ 2685 P29_0_SCB9_UART_RX = 26, /* Digital Active - scb[9].uart_rx:0 */ 2686 P29_0_SCB9_I2C_SDA = 27, /* Digital Active - scb[9].i2c_sda:0 */ 2687 2688 /* P29.1 */ 2689 P29_1_GPIO = 0, /* GPIO controls 'out' */ 2690 P29_1_AMUXA = 4, /* Analog mux bus A */ 2691 P29_1_AMUXB = 5, /* Analog mux bus B */ 2692 P29_1_TCPWM0_LINE29 = 8, /* Digital Active - tcpwm[0].line[29]:2 */ 2693 P29_1_TCPWM0_LINE_COMPL28 = 9, /* Digital Active - tcpwm[0].line_compl[28]:2 */ 2694 P29_1_TCPWM0_TR_ONE_CNT_IN27 = 10, /* Digital Active - tcpwm[0].tr_one_cnt_in[27]:2 */ 2695 P29_1_PASS0_SAR_EXT_MUX_EN0 = 16, /* Digital Active - pass[0].sar_ext_mux_en[0] */ 2696 P29_1_VIDEOSS0_TTL_DSP0_DATA_A111 = 24, /* Digital Active - videoss[0].ttl_dsp0_data_a1[11]:0 */ 2697 P29_1_SCB9_SPI_MOSI = 25, /* Digital Active - scb[9].spi_mosi:0 */ 2698 P29_1_SCB9_UART_TX = 26, /* Digital Active - scb[9].uart_tx:0 */ 2699 P29_1_SCB9_I2C_SCL = 27, /* Digital Active - scb[9].i2c_scl:0 */ 2700 2701 /* P30.0 */ 2702 P30_0_GPIO = 0, /* GPIO controls 'out' */ 2703 P30_0_AMUXA = 4, /* Analog mux bus A */ 2704 P30_0_AMUXB = 5, /* Analog mux bus B */ 2705 P30_0_PERI_TR_IO_INPUT20 = 20, /* Digital Active - peri.tr_io_input[20]:0 */ 2706 P30_0_ETH0_RX_ER = 24, /* Digital Active - eth[0].rx_er */ 2707 2708 /* P30.1 */ 2709 P30_1_GPIO = 0, /* GPIO controls 'out' */ 2710 P30_1_AMUXA = 4, /* Analog mux bus A */ 2711 P30_1_AMUXB = 5, /* Analog mux bus B */ 2712 P30_1_VIDEOSS0_TTL_DSP1_CONTROL10 = 18, /* Digital Active - videoss[0].ttl_dsp1_control[10]:0 */ 2713 P30_1_VIDEOSS0_TTL_DSP0_CONTROL10 = 19, /* Digital Active - videoss[0].ttl_dsp0_control[10]:0 */ 2714 P30_1_PERI_TR_IO_INPUT21 = 20, /* Digital Active - peri.tr_io_input[21]:0 */ 2715 P30_1_SRSS_IO_CLK_HF5 = 22, /* Digital Active - srss.io_clk_hf[5]:0 */ 2716 P30_1_ETH0_ETH_TSU_TIMER_CMP_VAL = 24 /* Digital Active - eth[0].eth_tsu_timer_cmp_val */ 2717 } en_hsiom_sel_t; 2718 2719 #endif /* _GPIO_TVIIC2D6M_327_BGA_H_ */ 2720 2721 2722 /* [] END OF FILE */ 2723
