1 /***************************************************************************//** 2 * \file gpio_cyw20829_52_qfn.h 3 * 4 * \brief 5 * CYW20829 device GPIO header for 52-QFN package 6 * 7 * \note 8 * Generator version: 1.6.0.381 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2020 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _GPIO_CYW20829_52_QFN_H_ 29 #define _GPIO_CYW20829_52_QFN_H_ 30 31 /* Package type */ 32 enum 33 { 34 CY_GPIO_PACKAGE_QFN, 35 CY_GPIO_PACKAGE_BGA, 36 CY_GPIO_PACKAGE_CSP, 37 CY_GPIO_PACKAGE_WLCSP, 38 CY_GPIO_PACKAGE_LQFP, 39 CY_GPIO_PACKAGE_TQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN 44 #define CY_GPIO_PIN_COUNT 52u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDA, 50 AMUXBUS_SAR, 51 AMUXBUS_AMUXBUSA_SRSS_VDDD, 52 AMUXBUS_AMUXBUSB_SRSS_VDDD, 53 }; 54 55 /* AMUX Splitter Controls */ 56 typedef enum 57 { 58 AMUX_SPLIT_CTL_0 = 0x0000u /* Left = AMUXBUS__SRSS_VDDD; Right = AMUXBUS_SRSS._ADFT_VDDD */ 59 } cy_en_amux_split_t; 60 61 /* Port List */ 62 /* PORT 0 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 63 #define P0_0_PORT GPIO_PRT0 64 #define P0_0_PIN 0u 65 #define P0_0_NUM 0u 66 #define P0_1_PORT GPIO_PRT0 67 #define P0_1_PIN 1u 68 #define P0_1_NUM 1u 69 #define P0_2_PORT GPIO_PRT0 70 #define P0_2_PIN 2u 71 #define P0_2_NUM 2u 72 #define P0_3_PORT GPIO_PRT0 73 #define P0_3_PIN 3u 74 #define P0_3_NUM 3u 75 #define P0_4_PORT GPIO_PRT0 76 #define P0_4_PIN 4u 77 #define P0_4_NUM 4u 78 #define P0_5_PORT GPIO_PRT0 79 #define P0_5_PIN 5u 80 #define P0_5_NUM 5u 81 82 /* PORT 1 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 83 #define P1_0_PORT GPIO_PRT1 84 #define P1_0_PIN 0u 85 #define P1_0_NUM 0u 86 #define P1_1_PORT GPIO_PRT1 87 #define P1_1_PIN 1u 88 #define P1_1_NUM 1u 89 #define P1_2_PORT GPIO_PRT1 90 #define P1_2_PIN 2u 91 #define P1_2_NUM 2u 92 #define P1_3_PORT GPIO_PRT1 93 #define P1_3_PIN 3u 94 #define P1_3_NUM 3u 95 96 /* PORT 2 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 97 #define P2_0_PORT GPIO_PRT2 98 #define P2_0_PIN 0u 99 #define P2_0_NUM 0u 100 #define P2_1_PORT GPIO_PRT2 101 #define P2_1_PIN 1u 102 #define P2_1_NUM 1u 103 #define P2_2_PORT GPIO_PRT2 104 #define P2_2_PIN 2u 105 #define P2_2_NUM 2u 106 #define P2_3_PORT GPIO_PRT2 107 #define P2_3_PIN 3u 108 #define P2_3_NUM 3u 109 #define P2_4_PORT GPIO_PRT2 110 #define P2_4_PIN 4u 111 #define P2_4_NUM 4u 112 #define P2_5_PORT GPIO_PRT2 113 #define P2_5_PIN 5u 114 #define P2_5_NUM 5u 115 116 /* PORT 3 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 117 #define P3_0_PORT GPIO_PRT3 118 #define P3_0_PIN 0u 119 #define P3_0_NUM 0u 120 #define P3_1_PORT GPIO_PRT3 121 #define P3_1_PIN 1u 122 #define P3_1_NUM 1u 123 #define P3_2_PORT GPIO_PRT3 124 #define P3_2_PIN 2u 125 #define P3_2_NUM 2u 126 #define P3_3_PORT GPIO_PRT3 127 #define P3_3_PIN 3u 128 #define P3_3_NUM 3u 129 #define P3_4_PORT GPIO_PRT3 130 #define P3_4_PIN 4u 131 #define P3_4_NUM 4u 132 #define P3_5_PORT GPIO_PRT3 133 #define P3_5_PIN 5u 134 #define P3_5_NUM 5u 135 #define P3_6_PORT GPIO_PRT3 136 #define P3_6_PIN 6u 137 #define P3_6_NUM 6u 138 #define P3_7_PORT GPIO_PRT3 139 #define P3_7_PIN 7u 140 #define P3_7_NUM 7u 141 142 /* PORT 4 (GPIO_OVT, SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 143 #define P4_0_PORT GPIO_PRT4 144 #define P4_0_PIN 0u 145 #define P4_0_NUM 0u 146 #define P4_0_AMUXSEGMENT AMUXBUS_SAR 147 #define P4_1_PORT GPIO_PRT4 148 #define P4_1_PIN 1u 149 #define P4_1_NUM 1u 150 #define P4_1_AMUXSEGMENT AMUXBUS_SAR 151 152 /* PORT 5 (SLEW_EXT, DRIVE_EXT, SLEW_WIDTH, DRIVE_WIDTH) */ 153 #define P5_0_PORT GPIO_PRT5 154 #define P5_0_PIN 0u 155 #define P5_0_NUM 0u 156 #define P5_1_PORT GPIO_PRT5 157 #define P5_1_PIN 1u 158 #define P5_1_NUM 1u 159 160 /* Analog Connections */ 161 #define IOSS_ADFT0_NET_PORT 3u 162 #define IOSS_ADFT0_NET_PIN 0u 163 #define IOSS_ADFT1_NET_PORT 3u 164 #define IOSS_ADFT1_NET_PIN 1u 165 #define PASS_AREF_EXT_VREF_PORT 3u 166 #define PASS_AREF_EXT_VREF_PIN 7u 167 #define PASS_SARMUX_PADS0_PORT 3u 168 #define PASS_SARMUX_PADS0_PIN 0u 169 #define PASS_SARMUX_PADS1_PORT 3u 170 #define PASS_SARMUX_PADS1_PIN 1u 171 #define PASS_SARMUX_PADS2_PORT 3u 172 #define PASS_SARMUX_PADS2_PIN 2u 173 #define PASS_SARMUX_PADS3_PORT 3u 174 #define PASS_SARMUX_PADS3_PIN 3u 175 #define PASS_SARMUX_PADS4_PORT 3u 176 #define PASS_SARMUX_PADS4_PIN 4u 177 #define PASS_SARMUX_PADS5_PORT 3u 178 #define PASS_SARMUX_PADS5_PIN 5u 179 #define PASS_SARMUX_PADS6_PORT 3u 180 #define PASS_SARMUX_PADS6_PIN 6u 181 #define PASS_SARMUX_PADS7_PORT 3u 182 #define PASS_SARMUX_PADS7_PIN 7u 183 #define SRSS_WCO_IN_PORT 5u 184 #define SRSS_WCO_IN_PIN 0u 185 #define SRSS_WCO_OUT_PORT 5u 186 #define SRSS_WCO_OUT_PIN 1u 187 188 /* HSIOM Connections */ 189 typedef enum 190 { 191 /* Generic HSIOM connections */ 192 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 193 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 194 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 195 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 196 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 197 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 198 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 199 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 200 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 201 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 202 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 203 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 204 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 205 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 206 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 207 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 208 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 209 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 210 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 211 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 212 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 213 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 214 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 215 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 216 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 217 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 218 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 219 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 220 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 221 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 222 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 223 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 224 225 /* P0.0 */ 226 P0_0_GPIO = 0, /* GPIO controls 'out' */ 227 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 228 P0_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ 229 P0_0_BTSS_RF_TST_DATA4 = 11, /* Digital Active - btss.rf_tst_data[4] */ 230 P0_0_KEYSCAN_KS_COL6 = 14, /* Digital Deep Sleep - keyscan.ks_col[6] */ 231 P0_0_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 232 P0_0_PDM_PDM_CLK1 = 21, /* Digital Active - pdm.pdm_clk[1]:0 */ 233 P0_0_TDM_TDM_TX_MCK0 = 24, /* Digital Active - tdm.tdm_tx_mck[0]:0 */ 234 P0_0_TDM_TDM_RX_MCK0 = 25, /* Digital Active - tdm.tdm_rx_mck[0]:0 */ 235 P0_0_SCB0_SPI_SELECT1 = 30, /* Digital Deep Sleep - scb[0].spi_select1:0 */ 236 237 /* P0.1 */ 238 P0_1_GPIO = 0, /* GPIO controls 'out' */ 239 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 240 P0_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ 241 P0_1_BTSS_RF_TST_DATA5 = 11, /* Digital Active - btss.rf_tst_data[5] */ 242 P0_1_KEYSCAN_KS_COL7 = 14, /* Digital Deep Sleep - keyscan.ks_col[7] */ 243 P0_1_PDM_PDM_DATA1 = 21, /* Digital Active - pdm.pdm_data[1]:0 */ 244 P0_1_TDM_TDM_TX_SCK0 = 24, /* Digital Active - tdm.tdm_tx_sck[0]:0 */ 245 P0_1_SCB0_SPI_SELECT2 = 30, /* Digital Deep Sleep - scb[0].spi_select2:0 */ 246 247 /* P0.2 */ 248 P0_2_GPIO = 0, /* GPIO controls 'out' */ 249 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 250 P0_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ 251 P0_2_BTSS_RF_TST_DATA6 = 11, /* Digital Active - btss.rf_tst_data[6] */ 252 P0_2_KEYSCAN_KS_COL8 = 14, /* Digital Deep Sleep - keyscan.ks_col[8] */ 253 P0_2_SCB0_I2C_SCL = 15, /* Digital Deep Sleep - scb[0].i2c_scl:0 */ 254 P0_2_PERI_TR_IO_INPUT4 = 22, /* Digital Active - peri.tr_io_input[4]:0 */ 255 P0_2_CANFD0_TTCAN_RX0 = 23, /* Digital Active - canfd[0].ttcan_rx[0] */ 256 P0_2_TDM_TDM_TX_FSYNC0 = 24, /* Digital Active - tdm.tdm_tx_fsync[0]:0 */ 257 P0_2_SCB0_SPI_MOSI = 30, /* Digital Deep Sleep - scb[0].spi_mosi:0 */ 258 259 /* P0.3 */ 260 P0_3_GPIO = 0, /* GPIO controls 'out' */ 261 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 262 P0_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ 263 P0_3_BTSS_RF_TST_DATA7 = 11, /* Digital Active - btss.rf_tst_data[7] */ 264 P0_3_KEYSCAN_KS_COL9 = 14, /* Digital Deep Sleep - keyscan.ks_col[9] */ 265 P0_3_SCB0_I2C_SDA = 15, /* Digital Deep Sleep - scb[0].i2c_sda:0 */ 266 P0_3_PERI_TR_IO_INPUT5 = 22, /* Digital Active - peri.tr_io_input[5]:0 */ 267 P0_3_CANFD0_TTCAN_TX0 = 23, /* Digital Active - canfd[0].ttcan_tx[0] */ 268 P0_3_TDM_TDM_TX_SD0 = 24, /* Digital Active - tdm.tdm_tx_sd[0]:0 */ 269 P0_3_SCB0_SPI_MISO = 30, /* Digital Deep Sleep - scb[0].spi_miso:0 */ 270 271 /* P0.4 */ 272 P0_4_GPIO = 0, /* GPIO controls 'out' */ 273 P0_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 274 P0_4_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ 275 P0_4_BTSS_GPIO2 = 10, /* Digital Active - btss.gpio[2] */ 276 P0_4_KEYSCAN_KS_ROW0 = 14, /* Digital Deep Sleep - keyscan.ks_row[0] */ 277 P0_4_TDM_TDM_RX_SCK0 = 24, /* Digital Active - tdm.tdm_rx_sck[0]:0 */ 278 P0_4_SCB0_SPI_CLK = 30, /* Digital Deep Sleep - scb[0].spi_clk:0 */ 279 280 /* P0.5 */ 281 P0_5_GPIO = 0, /* GPIO controls 'out' */ 282 P0_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 283 P0_5_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ 284 P0_5_BTSS_GPIO3 = 10, /* Digital Active - btss.gpio[3] */ 285 P0_5_KEYSCAN_KS_ROW1 = 14, /* Digital Deep Sleep - keyscan.ks_row[1] */ 286 P0_5_TDM_TDM_RX_FSYNC0 = 24, /* Digital Active - tdm.tdm_rx_fsync[0]:0 */ 287 P0_5_SMIF_SPIHB_SELECT1 = 27, /* Digital Active - smif.spihb_select1 */ 288 P0_5_SCB0_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[0].spi_select0:0 */ 289 290 /* P1.0 */ 291 P1_0_GPIO = 0, /* GPIO controls 'out' */ 292 P1_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 293 P1_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ 294 P1_0_BTSS_DEBUG0 = 10, /* Digital Active - btss.debug[0] */ 295 P1_0_BTSS_RPU_TDO = 11, /* Digital Active - btss.rpu_tdo */ 296 P1_0_KEYSCAN_KS_ROW2 = 14, /* Digital Deep Sleep - keyscan.ks_row[2] */ 297 P1_0_PERI_TR_IO_OUTPUT0 = 23, /* Digital Active - peri.tr_io_output[0]:0 */ 298 P1_0_TDM_TDM_RX_SD0 = 24, /* Digital Active - tdm.tdm_rx_sd[0]:0 */ 299 P1_0_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 300 301 /* P1.1 */ 302 P1_1_GPIO = 0, /* GPIO controls 'out' */ 303 P1_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 304 P1_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ 305 P1_1_BTSS_DEBUG1 = 10, /* Digital Active - btss.debug[1] */ 306 P1_1_BTSS_RPU_TDI = 11, /* Digital Active - btss.rpu_tdi */ 307 P1_1_KEYSCAN_KS_ROW3 = 14, /* Digital Deep Sleep - keyscan.ks_row[3] */ 308 P1_1_PERI_TR_IO_OUTPUT1 = 23, /* Digital Active - peri.tr_io_output[1]:0 */ 309 P1_1_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 310 P1_1_IOSS_DDFT_PIN0 = 31, /* Digital Deep Sleep - ioss.ddft_pin[0]:0 */ 311 312 /* P1.2 */ 313 P1_2_GPIO = 0, /* GPIO controls 'out' */ 314 P1_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 315 P1_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ 316 P1_2_BTSS_DEBUG2 = 10, /* Digital Active - btss.debug[2] */ 317 P1_2_BTSS_RPU_SWD = 11, /* Digital Active - btss.rpu_swd */ 318 P1_2_KEYSCAN_KS_ROW4 = 14, /* Digital Deep Sleep - keyscan.ks_row[4] */ 319 P1_2_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 320 321 /* P1.3 */ 322 P1_3_GPIO = 0, /* GPIO controls 'out' */ 323 P1_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 324 P1_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ 325 P1_3_BTSS_DEBUG3 = 10, /* Digital Active - btss.debug[3] */ 326 P1_3_BTSS_RPU_TCK = 11, /* Digital Active - btss.rpu_tck */ 327 P1_3_KEYSCAN_KS_ROW5 = 14, /* Digital Deep Sleep - keyscan.ks_row[5] */ 328 P1_3_CPUSS_CLK_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.clk_swj_swclk_tclk */ 329 330 /* P2.0 */ 331 P2_0_GPIO = 0, /* GPIO controls 'out' */ 332 P2_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 333 P2_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ 334 P2_0_BTSS_DEBUG4 = 10, /* Digital Active - btss.debug[4] */ 335 P2_0_BTSS_RF_TST_DATA3 = 11, /* Digital Active - btss.rf_tst_data[3] */ 336 P2_0_KEYSCAN_KS_COL0 = 14, /* Digital Deep Sleep - keyscan.ks_col[0] */ 337 P2_0_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 338 P2_0_PERI_TR_IO_INPUT0 = 22, /* Digital Active - peri.tr_io_input[0]:0 */ 339 P2_0_SMIF_SPIHB_SELECT0 = 27, /* Digital Active - smif.spihb_select0 */ 340 P2_0_CPUSS_RST_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.rst_swj_trstn */ 341 342 /* P2.1 */ 343 P2_1_GPIO = 0, /* GPIO controls 'out' */ 344 P2_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 345 P2_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ 346 P2_1_BTSS_DEBUG5 = 10, /* Digital Active - btss.debug[5] */ 347 P2_1_BTSS_RPU_NTRST = 11, /* Digital Active - btss.rpu_ntrst */ 348 P2_1_KEYSCAN_KS_COL1 = 14, /* Digital Deep Sleep - keyscan.ks_col[1] */ 349 P2_1_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 350 P2_1_CPUSS_TRACE_DATA3 = 17, /* Digital Active - cpuss.trace_data[3]:0 */ 351 P2_1_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 352 P2_1_PERI_TR_IO_INPUT1 = 22, /* Digital Active - peri.tr_io_input[1]:0 */ 353 P2_1_LIN0_LIN_EN1 = 23, /* Digital Active - lin[0].lin_en[1]:0 */ 354 P2_1_SMIF_SPIHB_DATA3 = 27, /* Digital Active - smif.spihb_data3 */ 355 P2_1_IOSS_DDFT_PIN1 = 31, /* Digital Deep Sleep - ioss.ddft_pin[1]:0 */ 356 357 /* P2.2 */ 358 P2_2_GPIO = 0, /* GPIO controls 'out' */ 359 P2_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 360 P2_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ 361 P2_2_BTSS_DEBUG6 = 10, /* Digital Active - btss.debug[6] */ 362 P2_2_BTSS_RF_TST_CLK = 11, /* Digital Active - btss.rf_tst_clk */ 363 P2_2_KEYSCAN_KS_COL2 = 14, /* Digital Deep Sleep - keyscan.ks_col[2] */ 364 P2_2_CPUSS_TRACE_DATA2 = 17, /* Digital Active - cpuss.trace_data[2]:0 */ 365 P2_2_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 366 P2_2_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 367 P2_2_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 368 P2_2_LIN0_LIN_RX1 = 23, /* Digital Active - lin[0].lin_rx[1]:0 */ 369 P2_2_SMIF_SPIHB_DATA2 = 27, /* Digital Active - smif.spihb_data2 */ 370 371 /* P2.3 */ 372 P2_3_GPIO = 0, /* GPIO controls 'out' */ 373 P2_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 374 P2_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ 375 P2_3_BTSS_DEBUG7 = 10, /* Digital Active - btss.debug[7] */ 376 P2_3_BTSS_RF_TST_DATA0 = 11, /* Digital Active - btss.rf_tst_data[0] */ 377 P2_3_KEYSCAN_KS_COL3 = 14, /* Digital Deep Sleep - keyscan.ks_col[3] */ 378 P2_3_CPUSS_TRACE_DATA1 = 17, /* Digital Active - cpuss.trace_data[1]:0 */ 379 P2_3_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 380 P2_3_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 381 P2_3_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 382 P2_3_LIN0_LIN_TX1 = 23, /* Digital Active - lin[0].lin_tx[1]:0 */ 383 P2_3_SMIF_SPIHB_DATA1 = 27, /* Digital Active - smif.spihb_data1 */ 384 385 /* P2.4 */ 386 P2_4_GPIO = 0, /* GPIO controls 'out' */ 387 P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 388 P2_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ 389 P2_4_BTSS_DEBUG8 = 10, /* Digital Active - btss.debug[8] */ 390 P2_4_BTSS_RF_TST_DATA1 = 11, /* Digital Active - btss.rf_tst_data[1] */ 391 P2_4_KEYSCAN_KS_COL4 = 14, /* Digital Deep Sleep - keyscan.ks_col[4] */ 392 P2_4_CPUSS_TRACE_DATA0 = 17, /* Digital Active - cpuss.trace_data[0]:0 */ 393 P2_4_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 394 P2_4_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 395 P2_4_PERI_TR_IO_INPUT2 = 22, /* Digital Active - peri.tr_io_input[2]:0 */ 396 P2_4_SMIF_SPIHB_DATA0 = 27, /* Digital Active - smif.spihb_data0 */ 397 398 /* P2.5 */ 399 P2_5_GPIO = 0, /* GPIO controls 'out' */ 400 P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 401 P2_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ 402 P2_5_BTSS_DEBUG9 = 10, /* Digital Active - btss.debug[9] */ 403 P2_5_BTSS_RF_TST_DATA2 = 11, /* Digital Active - btss.rf_tst_data[2] */ 404 P2_5_KEYSCAN_KS_COL5 = 14, /* Digital Deep Sleep - keyscan.ks_col[5] */ 405 P2_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 406 P2_5_CPUSS_TRACE_CLOCK = 17, /* Digital Active - cpuss.trace_clock:0 */ 407 P2_5_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 408 P2_5_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 409 P2_5_PERI_TR_IO_INPUT3 = 22, /* Digital Active - peri.tr_io_input[3]:0 */ 410 P2_5_SMIF_SPIHB_CLK = 27, /* Digital Active - smif.spihb_clk */ 411 412 /* P3.0 */ 413 P3_0_GPIO = 0, /* GPIO controls 'out' */ 414 P3_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 415 P3_0_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ 416 P3_0_BTSS_ANTENNA_SWITCH_CTRL3 = 11, /* Digital Active - btss.antenna_switch_ctrl[3] */ 417 P3_0_KEYSCAN_KS_COL10 = 14, /* Digital Deep Sleep - keyscan.ks_col[10] */ 418 419 /* P3.1 */ 420 P3_1_GPIO = 0, /* GPIO controls 'out' */ 421 P3_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 422 P3_1_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ 423 P3_1_BTSS_GCI_GPIO3 = 11, /* Digital Active - btss.gci_gpio[3] */ 424 P3_1_KEYSCAN_KS_COL11 = 14, /* Digital Deep Sleep - keyscan.ks_col[11] */ 425 P3_1_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 426 427 /* P3.2 */ 428 P3_2_GPIO = 0, /* GPIO controls 'out' */ 429 P3_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 430 P3_2_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ 431 P3_2_BTSS_UART_RXD = 10, /* Digital Active - btss.uart_rxd:0 */ 432 P3_2_BTSS_GCI_GPIO2 = 11, /* Digital Active - btss.gci_gpio[2] */ 433 P3_2_KEYSCAN_KS_COL12 = 14, /* Digital Deep Sleep - keyscan.ks_col[12] */ 434 P3_2_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 435 436 /* P3.3 */ 437 P3_3_GPIO = 0, /* GPIO controls 'out' */ 438 P3_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 439 P3_3_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ 440 P3_3_BTSS_UART_TXD = 10, /* Digital Active - btss.uart_txd:0 */ 441 P3_3_BTSS_GCI_GPIO1 = 11, /* Digital Active - btss.gci_gpio[1] */ 442 P3_3_KEYSCAN_KS_COL13 = 14, /* Digital Deep Sleep - keyscan.ks_col[13] */ 443 P3_3_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 444 P3_3_PERI_TR_IO_INPUT6 = 22, /* Digital Active - peri.tr_io_input[6]:0 */ 445 446 /* P3.4 */ 447 P3_4_GPIO = 0, /* GPIO controls 'out' */ 448 P3_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 449 P3_4_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ 450 P3_4_BTSS_UART_RTS = 10, /* Digital Active - btss.uart_rts:0 */ 451 P3_4_BTSS_GCI_GPIO0 = 11, /* Digital Active - btss.gci_gpio[0] */ 452 P3_4_KEYSCAN_KS_COL14 = 14, /* Digital Deep Sleep - keyscan.ks_col[14] */ 453 P3_4_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 454 P3_4_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 455 P3_4_PDM_PDM_DATA0 = 21, /* Digital Active - pdm.pdm_data[0] */ 456 P3_4_PERI_TR_IO_INPUT7 = 22, /* Digital Active - peri.tr_io_input[7]:0 */ 457 458 /* P3.5 */ 459 P3_5_GPIO = 0, /* GPIO controls 'out' */ 460 P3_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 461 P3_5_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ 462 P3_5_BTSS_UART_CTS = 10, /* Digital Active - btss.uart_cts:0 */ 463 P3_5_BTSS_ANTENNA_SWITCH_CTRL0 = 11, /* Digital Active - btss.antenna_switch_ctrl[0] */ 464 P3_5_KEYSCAN_KS_COL15 = 14, /* Digital Deep Sleep - keyscan.ks_col[15] */ 465 P3_5_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 466 P3_5_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 467 P3_5_PDM_PDM_CLK0 = 21, /* Digital Active - pdm.pdm_clk[0] */ 468 P3_5_LIN0_LIN_EN0 = 23, /* Digital Active - lin[0].lin_en[0]:0 */ 469 470 /* P3.6 */ 471 P3_6_GPIO = 0, /* GPIO controls 'out' */ 472 P3_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 473 P3_6_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ 474 P3_6_BTSS_ANTENNA_SWITCH_CTRL1 = 11, /* Digital Active - btss.antenna_switch_ctrl[1] */ 475 P3_6_KEYSCAN_KS_COL16 = 14, /* Digital Deep Sleep - keyscan.ks_col[16] */ 476 P3_6_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 477 P3_6_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 478 P3_6_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 479 P3_6_PDM_PDM_CLK1 = 21, /* Digital Active - pdm.pdm_clk[1]:1 */ 480 P3_6_LIN0_LIN_RX0 = 23, /* Digital Active - lin[0].lin_rx[0]:0 */ 481 482 /* P3.7 */ 483 P3_7_GPIO = 0, /* GPIO controls 'out' */ 484 P3_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 485 P3_7_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ 486 P3_7_BTSS_ANTENNA_SWITCH_CTRL2 = 11, /* Digital Active - btss.antenna_switch_ctrl[2] */ 487 P3_7_KEYSCAN_KS_COL17 = 14, /* Digital Deep Sleep - keyscan.ks_col[17] */ 488 P3_7_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 489 P3_7_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 490 P3_7_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 491 P3_7_PDM_PDM_DATA1 = 21, /* Digital Active - pdm.pdm_data[1]:1 */ 492 P3_7_LIN0_LIN_TX0 = 23, /* Digital Active - lin[0].lin_tx[0]:0 */ 493 494 /* P4.0 */ 495 P4_0_GPIO = 0, /* GPIO controls 'out' */ 496 P4_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 497 P4_0_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ 498 P4_0_BTSS_SPI_MOSI = 10, /* Digital Active - btss.spi_mosi:0 */ 499 P4_0_KEYSCAN_KS_ROW6 = 14, /* Digital Deep Sleep - keyscan.ks_row[6] */ 500 P4_0_SCB0_I2C_SCL = 15, /* Digital Deep Sleep - scb[0].i2c_scl:1 */ 501 P4_0_SRSS_CAL_WAVE = 17, /* Digital Active - srss.cal_wave */ 502 503 /* P4.1 */ 504 P4_1_GPIO = 0, /* GPIO controls 'out' */ 505 P4_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 506 P4_1_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ 507 P4_1_BTSS_SPI_CLK = 10, /* Digital Active - btss.spi_clk:0 */ 508 P4_1_KEYSCAN_KS_ROW7 = 14, /* Digital Deep Sleep - keyscan.ks_row[7] */ 509 P4_1_SCB0_I2C_SDA = 15, /* Digital Deep Sleep - scb[0].i2c_sda:1 */ 510 511 /* P5.0 */ 512 P5_0_GPIO = 0, /* GPIO controls 'out' */ 513 P5_0_BTSS_GPIO0 = 10, /* Digital Active - btss.gpio[0] */ 514 P5_0_KEYSCAN_KS_COL18 = 14, /* Digital Deep Sleep - keyscan.ks_col[18] */ 515 516 /* P5.1 */ 517 P5_1_GPIO = 0, /* GPIO controls 'out' */ 518 P5_1_BTSS_GPIO1 = 10, /* Digital Active - btss.gpio[1] */ 519 P5_1_KEYSCAN_KS_COL19 = 14 /* Digital Deep Sleep - keyscan.ks_col[19] */ 520 } en_hsiom_sel_t; 521 522 #endif /* _GPIO_CYW20829_52_QFN_H_ */ 523 524 525 /* [] END OF FILE */ 526
