1 /***************************************************************************//** 2 * \file gpio_psoc6_03_100_tqfp.h 3 * 4 * \brief 5 * PSoC6_03 device GPIO header for 100-TQFP package 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _GPIO_PSOC6_03_100_TQFP_H_ 28 #define _GPIO_PSOC6_03_100_TQFP_H_ 29 30 /* Package type */ 31 enum 32 { 33 CY_GPIO_PACKAGE_QFN, 34 CY_GPIO_PACKAGE_BGA, 35 CY_GPIO_PACKAGE_CSP, 36 CY_GPIO_PACKAGE_WLCSP, 37 CY_GPIO_PACKAGE_LQFP, 38 CY_GPIO_PACKAGE_TQFP, 39 CY_GPIO_PACKAGE_TEQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_TQFP 44 #define CY_GPIO_PIN_COUNT 100u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_ANALOG_VDDD, 50 AMUXBUS_CSD0, 51 AMUXBUS_CSD1, 52 AMUXBUS_SAR, 53 AMUXBUS_VDDIO_1, 54 AMUXBUS_VSSA, 55 AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, 56 AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, 57 }; 58 59 /* AMUX Splitter Controls */ 60 typedef enum 61 { 62 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 63 AMUX_SPLIT_CTL_3 = 0x0003u /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 64 } cy_en_amux_split_t; 65 66 /* Port List */ 67 /* PORT 0 (GPIO) */ 68 #define P0_0_PORT GPIO_PRT0 69 #define P0_0_PIN 0u 70 #define P0_0_NUM 0u 71 #define P0_1_PORT GPIO_PRT0 72 #define P0_1_PIN 1u 73 #define P0_1_NUM 1u 74 #define P0_2_PORT GPIO_PRT0 75 #define P0_2_PIN 2u 76 #define P0_2_NUM 2u 77 #define P0_3_PORT GPIO_PRT0 78 #define P0_3_PIN 3u 79 #define P0_3_NUM 3u 80 #define P0_4_PORT GPIO_PRT0 81 #define P0_4_PIN 4u 82 #define P0_4_NUM 4u 83 #define P0_5_PORT GPIO_PRT0 84 #define P0_5_PIN 5u 85 #define P0_5_NUM 5u 86 87 /* PORT 2 (GPIO) */ 88 #define P2_0_PORT GPIO_PRT2 89 #define P2_0_PIN 0u 90 #define P2_0_NUM 0u 91 #define P2_1_PORT GPIO_PRT2 92 #define P2_1_PIN 1u 93 #define P2_1_NUM 1u 94 #define P2_2_PORT GPIO_PRT2 95 #define P2_2_PIN 2u 96 #define P2_2_NUM 2u 97 #define P2_3_PORT GPIO_PRT2 98 #define P2_3_PIN 3u 99 #define P2_3_NUM 3u 100 #define P2_4_PORT GPIO_PRT2 101 #define P2_4_PIN 4u 102 #define P2_4_NUM 4u 103 #define P2_5_PORT GPIO_PRT2 104 #define P2_5_PIN 5u 105 #define P2_5_NUM 5u 106 #define P2_6_PORT GPIO_PRT2 107 #define P2_6_PIN 6u 108 #define P2_6_NUM 6u 109 #define P2_7_PORT GPIO_PRT2 110 #define P2_7_PIN 7u 111 #define P2_7_NUM 7u 112 113 /* PORT 3 (GPIO_OVT) */ 114 #define P3_0_PORT GPIO_PRT3 115 #define P3_0_PIN 0u 116 #define P3_0_NUM 0u 117 #define P3_0_AMUXSEGMENT AMUXBUS_VSSA 118 #define P3_1_PORT GPIO_PRT3 119 #define P3_1_PIN 1u 120 #define P3_1_NUM 1u 121 #define P3_1_AMUXSEGMENT AMUXBUS_VSSA 122 123 /* PORT 5 (GPIO) */ 124 #define P5_0_PORT GPIO_PRT5 125 #define P5_0_PIN 0u 126 #define P5_0_NUM 0u 127 #define P5_1_PORT GPIO_PRT5 128 #define P5_1_PIN 1u 129 #define P5_1_NUM 1u 130 #define P5_6_PORT GPIO_PRT5 131 #define P5_6_PIN 6u 132 #define P5_6_NUM 6u 133 #define P5_7_PORT GPIO_PRT5 134 #define P5_7_PIN 7u 135 #define P5_7_NUM 7u 136 137 /* PORT 6 (GPIO) */ 138 #define P6_0_PORT GPIO_PRT6 139 #define P6_0_PIN 0u 140 #define P6_0_NUM 0u 141 #define P6_1_PORT GPIO_PRT6 142 #define P6_1_PIN 1u 143 #define P6_1_NUM 1u 144 #define P6_2_PORT GPIO_PRT6 145 #define P6_2_PIN 2u 146 #define P6_2_NUM 2u 147 #define P6_3_PORT GPIO_PRT6 148 #define P6_3_PIN 3u 149 #define P6_3_NUM 3u 150 #define P6_4_PORT GPIO_PRT6 151 #define P6_4_PIN 4u 152 #define P6_4_NUM 4u 153 #define P6_5_PORT GPIO_PRT6 154 #define P6_5_PIN 5u 155 #define P6_5_NUM 5u 156 #define P6_6_PORT GPIO_PRT6 157 #define P6_6_PIN 6u 158 #define P6_6_NUM 6u 159 #define P6_7_PORT GPIO_PRT6 160 #define P6_7_PIN 7u 161 #define P6_7_NUM 7u 162 163 /* PORT 7 (GPIO) */ 164 #define P7_0_PORT GPIO_PRT7 165 #define P7_0_PIN 0u 166 #define P7_0_NUM 0u 167 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 168 #define P7_1_PORT GPIO_PRT7 169 #define P7_1_PIN 1u 170 #define P7_1_NUM 1u 171 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 172 #define P7_2_PORT GPIO_PRT7 173 #define P7_2_PIN 2u 174 #define P7_2_NUM 2u 175 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 176 #define P7_3_PORT GPIO_PRT7 177 #define P7_3_PIN 3u 178 #define P7_3_NUM 3u 179 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 180 #define P7_4_PORT GPIO_PRT7 181 #define P7_4_PIN 4u 182 #define P7_4_NUM 4u 183 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 184 #define P7_5_PORT GPIO_PRT7 185 #define P7_5_PIN 5u 186 #define P7_5_NUM 5u 187 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 188 #define P7_6_PORT GPIO_PRT7 189 #define P7_6_PIN 6u 190 #define P7_6_NUM 6u 191 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 192 #define P7_7_PORT GPIO_PRT7 193 #define P7_7_PIN 7u 194 #define P7_7_NUM 7u 195 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 196 197 /* PORT 8 (GPIO) */ 198 #define P8_0_PORT GPIO_PRT8 199 #define P8_0_PIN 0u 200 #define P8_0_NUM 0u 201 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 202 #define P8_1_PORT GPIO_PRT8 203 #define P8_1_PIN 1u 204 #define P8_1_NUM 1u 205 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 206 #define P8_2_PORT GPIO_PRT8 207 #define P8_2_PIN 2u 208 #define P8_2_NUM 2u 209 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 210 #define P8_3_PORT GPIO_PRT8 211 #define P8_3_PIN 3u 212 #define P8_3_NUM 3u 213 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 214 215 /* PORT 9 (GPIO) */ 216 #define P9_0_PORT GPIO_PRT9 217 #define P9_0_PIN 0u 218 #define P9_0_NUM 0u 219 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 220 #define P9_1_PORT GPIO_PRT9 221 #define P9_1_PIN 1u 222 #define P9_1_NUM 1u 223 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 224 #define P9_2_PORT GPIO_PRT9 225 #define P9_2_PIN 2u 226 #define P9_2_NUM 2u 227 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 228 #define P9_3_PORT GPIO_PRT9 229 #define P9_3_PIN 3u 230 #define P9_3_NUM 3u 231 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 232 233 /* PORT 10 (GPIO) */ 234 #define P10_0_PORT GPIO_PRT10 235 #define P10_0_PIN 0u 236 #define P10_0_NUM 0u 237 #define P10_1_PORT GPIO_PRT10 238 #define P10_1_PIN 1u 239 #define P10_1_NUM 1u 240 #define P10_2_PORT GPIO_PRT10 241 #define P10_2_PIN 2u 242 #define P10_2_NUM 2u 243 #define P10_3_PORT GPIO_PRT10 244 #define P10_3_PIN 3u 245 #define P10_3_NUM 3u 246 #define P10_4_PORT GPIO_PRT10 247 #define P10_4_PIN 4u 248 #define P10_4_NUM 4u 249 #define P10_5_PORT GPIO_PRT10 250 #define P10_5_PIN 5u 251 #define P10_5_NUM 5u 252 #define P10_6_PORT GPIO_PRT10 253 #define P10_6_PIN 6u 254 #define P10_6_NUM 6u 255 #define P10_7_PORT GPIO_PRT10 256 #define P10_7_PIN 7u 257 #define P10_7_NUM 7u 258 259 /* PORT 11 (GPIO) */ 260 #define P11_0_PORT GPIO_PRT11 261 #define P11_0_PIN 0u 262 #define P11_0_NUM 0u 263 #define P11_1_PORT GPIO_PRT11 264 #define P11_1_PIN 1u 265 #define P11_1_NUM 1u 266 #define P11_2_PORT GPIO_PRT11 267 #define P11_2_PIN 2u 268 #define P11_2_NUM 2u 269 #define P11_3_PORT GPIO_PRT11 270 #define P11_3_PIN 3u 271 #define P11_3_NUM 3u 272 #define P11_4_PORT GPIO_PRT11 273 #define P11_4_PIN 4u 274 #define P11_4_NUM 4u 275 #define P11_5_PORT GPIO_PRT11 276 #define P11_5_PIN 5u 277 #define P11_5_NUM 5u 278 #define P11_6_PORT GPIO_PRT11 279 #define P11_6_PIN 6u 280 #define P11_6_NUM 6u 281 #define P11_7_PORT GPIO_PRT11 282 #define P11_7_PIN 7u 283 #define P11_7_NUM 7u 284 285 /* PORT 12 (GPIO) */ 286 #define P12_0_PORT GPIO_PRT12 287 #define P12_0_PIN 0u 288 #define P12_0_NUM 0u 289 #define P12_1_PORT GPIO_PRT12 290 #define P12_1_PIN 1u 291 #define P12_1_NUM 1u 292 #define P12_6_PORT GPIO_PRT12 293 #define P12_6_PIN 6u 294 #define P12_6_NUM 6u 295 #define P12_7_PORT GPIO_PRT12 296 #define P12_7_PIN 7u 297 #define P12_7_NUM 7u 298 299 /* PORT 14 (AUX) */ 300 #define USBDP_PORT GPIO_PRT14 301 #define USBDP_PIN 0u 302 #define USBDP_NUM 0u 303 #define P14_0_PORT GPIO_PRT14 304 #define P14_0_PIN 0u 305 #define P14_0_NUM 0u 306 #define USBDM_PORT GPIO_PRT14 307 #define USBDM_PIN 1u 308 #define USBDM_NUM 1u 309 #define P14_1_PORT GPIO_PRT14 310 #define P14_1_PIN 1u 311 #define P14_1_NUM 1u 312 313 /* Analog Connections */ 314 #define CSD_CMODPADD_PORT 7u 315 #define CSD_CMODPADD_PIN 1u 316 #define CSD_CMODPADS_PORT 7u 317 #define CSD_CMODPADS_PIN 1u 318 #define CSD_CSH_TANKPADD_PORT 7u 319 #define CSD_CSH_TANKPADD_PIN 2u 320 #define CSD_CSH_TANKPADS_PORT 7u 321 #define CSD_CSH_TANKPADS_PIN 2u 322 #define CSD_CSHIELDPADS_PORT 7u 323 #define CSD_CSHIELDPADS_PIN 7u 324 #define CSD_VREF_EXT_PORT 7u 325 #define CSD_VREF_EXT_PIN 3u 326 #define IOSS_ADFT0_NET_PORT 10u 327 #define IOSS_ADFT0_NET_PIN 0u 328 #define IOSS_ADFT1_NET_PORT 10u 329 #define IOSS_ADFT1_NET_PIN 1u 330 #define LPCOMP_INN_COMP0_PORT 5u 331 #define LPCOMP_INN_COMP0_PIN 7u 332 #define LPCOMP_INN_COMP1_PORT 6u 333 #define LPCOMP_INN_COMP1_PIN 3u 334 #define LPCOMP_INP_COMP0_PORT 5u 335 #define LPCOMP_INP_COMP0_PIN 6u 336 #define LPCOMP_INP_COMP1_PORT 6u 337 #define LPCOMP_INP_COMP1_PIN 2u 338 #define PASS_AREF_EXT_VREF_PORT 9u 339 #define PASS_AREF_EXT_VREF_PIN 3u 340 #define PASS_SARMUX_PADS0_PORT 10u 341 #define PASS_SARMUX_PADS0_PIN 0u 342 #define PASS_SARMUX_PADS1_PORT 10u 343 #define PASS_SARMUX_PADS1_PIN 1u 344 #define PASS_SARMUX_PADS2_PORT 10u 345 #define PASS_SARMUX_PADS2_PIN 2u 346 #define PASS_SARMUX_PADS3_PORT 10u 347 #define PASS_SARMUX_PADS3_PIN 3u 348 #define PASS_SARMUX_PADS4_PORT 10u 349 #define PASS_SARMUX_PADS4_PIN 4u 350 #define PASS_SARMUX_PADS5_PORT 10u 351 #define PASS_SARMUX_PADS5_PIN 5u 352 #define PASS_SARMUX_PADS6_PORT 10u 353 #define PASS_SARMUX_PADS6_PIN 6u 354 #define PASS_SARMUX_PADS7_PORT 10u 355 #define PASS_SARMUX_PADS7_PIN 7u 356 #define SRSS_ADFT_PIN0_PORT 10u 357 #define SRSS_ADFT_PIN0_PIN 0u 358 #define SRSS_ADFT_PIN1_PORT 10u 359 #define SRSS_ADFT_PIN1_PIN 1u 360 #define SRSS_ECO_IN_PORT 12u 361 #define SRSS_ECO_IN_PIN 6u 362 #define SRSS_ECO_OUT_PORT 12u 363 #define SRSS_ECO_OUT_PIN 7u 364 #define SRSS_WCO_IN_PORT 0u 365 #define SRSS_WCO_IN_PIN 0u 366 #define SRSS_WCO_OUT_PORT 0u 367 #define SRSS_WCO_OUT_PIN 1u 368 369 /* HSIOM Connections */ 370 typedef enum 371 { 372 /* Generic HSIOM connections */ 373 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 374 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 375 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 376 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 377 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 378 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 379 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 380 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 381 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 382 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 383 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 384 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 385 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 386 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 387 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 388 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 389 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 390 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 391 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 392 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 393 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 394 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 395 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 396 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 397 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 398 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 399 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 400 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 401 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 402 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 403 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 404 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 405 406 /* P0.0 */ 407 P0_0_GPIO = 0, /* GPIO controls 'out' */ 408 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 409 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 410 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 411 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 412 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 413 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 414 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 415 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 416 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 417 418 /* P0.1 */ 419 P0_1_GPIO = 0, /* GPIO controls 'out' */ 420 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 421 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 422 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 423 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 424 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 425 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 426 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 427 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 428 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 429 430 /* P0.2 */ 431 P0_2_GPIO = 0, /* GPIO controls 'out' */ 432 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 433 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 434 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 435 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 436 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 437 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 438 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 439 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 440 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 441 442 /* P0.3 */ 443 P0_3_GPIO = 0, /* GPIO controls 'out' */ 444 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 445 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 446 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 447 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 448 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 449 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 450 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 451 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 452 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 453 454 /* P0.4 */ 455 P0_4_GPIO = 0, /* GPIO controls 'out' */ 456 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 457 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 458 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 459 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 460 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 461 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 462 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 463 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 464 P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 465 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 466 467 /* P0.5 */ 468 P0_5_GPIO = 0, /* GPIO controls 'out' */ 469 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 470 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 471 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 472 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 473 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 474 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 475 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 476 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 477 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 478 P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 479 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 480 481 /* P2.0 */ 482 P2_0_GPIO = 0, /* GPIO controls 'out' */ 483 P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 484 P2_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 485 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 486 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 487 P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 488 P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 489 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 490 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 491 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 492 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 493 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 494 495 /* P2.1 */ 496 P2_1_GPIO = 0, /* GPIO controls 'out' */ 497 P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 498 P2_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 499 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 500 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 501 P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 502 P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 503 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 504 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 505 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 506 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 507 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 508 509 /* P2.2 */ 510 P2_2_GPIO = 0, /* GPIO controls 'out' */ 511 P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 512 P2_2_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 513 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 514 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 515 P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 516 P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 517 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 518 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 519 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 520 521 /* P2.3 */ 522 P2_3_GPIO = 0, /* GPIO controls 'out' */ 523 P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 524 P2_3_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 525 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 526 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 527 P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 528 P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 529 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 530 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 531 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 532 533 /* P2.4 */ 534 P2_4_GPIO = 0, /* GPIO controls 'out' */ 535 P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 536 P2_4_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 537 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 538 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 539 P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 540 P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 541 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 542 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 543 544 /* P2.5 */ 545 P2_5_GPIO = 0, /* GPIO controls 'out' */ 546 P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 547 P2_5_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 548 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 549 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 550 P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 551 P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 552 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 553 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 554 555 /* P2.6 */ 556 P2_6_GPIO = 0, /* GPIO controls 'out' */ 557 P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 558 P2_6_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 559 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 560 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 561 P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 562 P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 563 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 564 P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 565 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 566 567 /* P2.7 */ 568 P2_7_GPIO = 0, /* GPIO controls 'out' */ 569 P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 570 P2_7_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 571 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 572 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 573 P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 574 P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 575 P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 576 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 577 578 /* P3.0 */ 579 P3_0_GPIO = 0, /* GPIO controls 'out' */ 580 P3_0_AMUXA = 4, /* Analog mux bus A */ 581 P3_0_AMUXB = 5, /* Analog mux bus B */ 582 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 583 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 584 P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 585 P3_0_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 586 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 587 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 588 P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 589 P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 590 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 591 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 592 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 593 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 594 P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ 595 596 /* P3.1 */ 597 P3_1_GPIO = 0, /* GPIO controls 'out' */ 598 P3_1_AMUXA = 4, /* Analog mux bus A */ 599 P3_1_AMUXB = 5, /* Analog mux bus B */ 600 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 601 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 602 P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 603 P3_1_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 604 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 605 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 606 P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 607 P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 608 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 609 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 610 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 611 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 612 P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ 613 614 /* P5.0 */ 615 P5_0_GPIO = 0, /* GPIO controls 'out' */ 616 P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 617 P5_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 618 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 619 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 620 P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 621 P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 622 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 623 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 624 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 625 P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ 626 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 627 628 /* P5.1 */ 629 P5_1_GPIO = 0, /* GPIO controls 'out' */ 630 P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 631 P5_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 632 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 633 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 634 P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 635 P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 636 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 637 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 638 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 639 P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ 640 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 641 642 /* P5.6 */ 643 P5_6_GPIO = 0, /* GPIO controls 'out' */ 644 P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 645 P5_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 646 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 647 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 648 P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 649 P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 650 651 /* P5.7 */ 652 P5_7_GPIO = 0, /* GPIO controls 'out' */ 653 P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 654 P5_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 655 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 656 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 657 P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 658 P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 659 660 /* P6.0 */ 661 P6_0_GPIO = 0, /* GPIO controls 'out' */ 662 P6_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 663 P6_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 664 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 665 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 666 P6_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ 667 P6_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ 668 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 669 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 670 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 671 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 672 673 /* P6.1 */ 674 P6_1_GPIO = 0, /* GPIO controls 'out' */ 675 P6_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 676 P6_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 677 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ 678 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ 679 P6_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ 680 P6_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ 681 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 682 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 683 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 684 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 685 686 /* P6.2 */ 687 P6_2_GPIO = 0, /* GPIO controls 'out' */ 688 P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 689 P6_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 690 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 691 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 692 P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 693 P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 694 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 695 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 696 697 /* P6.3 */ 698 P6_3_GPIO = 0, /* GPIO controls 'out' */ 699 P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 700 P6_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 701 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 702 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 703 P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 704 P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 705 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 706 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 707 708 /* P6.4 */ 709 P6_4_GPIO = 0, /* GPIO controls 'out' */ 710 P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 711 P6_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 712 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 713 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 714 P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 715 P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 716 P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ 717 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 718 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 719 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 720 P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ 721 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 722 723 /* P6.5 */ 724 P6_5_GPIO = 0, /* GPIO controls 'out' */ 725 P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 726 P6_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 727 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 728 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 729 P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 730 P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 731 P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ 732 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 733 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 734 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 735 P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ 736 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 737 738 /* P6.6 */ 739 P6_6_GPIO = 0, /* GPIO controls 'out' */ 740 P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 741 P6_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 742 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 743 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 744 P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 745 P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 746 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 747 P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ 748 749 /* P6.7 */ 750 P6_7_GPIO = 0, /* GPIO controls 'out' */ 751 P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 752 P6_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 753 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 754 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 755 P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 756 P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 757 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 758 P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ 759 760 /* P7.0 */ 761 P7_0_GPIO = 0, /* GPIO controls 'out' */ 762 P7_0_AMUXA = 4, /* Analog mux bus A */ 763 P7_0_AMUXB = 5, /* Analog mux bus B */ 764 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 765 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 766 P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 767 P7_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 768 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ 769 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ 770 P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ 771 P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ 772 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 773 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 774 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 775 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 776 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 777 778 /* P7.1 */ 779 P7_1_GPIO = 0, /* GPIO controls 'out' */ 780 P7_1_AMUXA = 4, /* Analog mux bus A */ 781 P7_1_AMUXB = 5, /* Analog mux bus B */ 782 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 783 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 784 P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 785 P7_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 786 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ 787 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ 788 P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ 789 P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ 790 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 791 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 792 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 793 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 794 795 /* P7.2 */ 796 P7_2_GPIO = 0, /* GPIO controls 'out' */ 797 P7_2_AMUXA = 4, /* Analog mux bus A */ 798 P7_2_AMUXB = 5, /* Analog mux bus B */ 799 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 800 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 801 P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 802 P7_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 803 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 804 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 805 P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 806 P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 807 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 808 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 809 810 /* P7.3 */ 811 P7_3_GPIO = 0, /* GPIO controls 'out' */ 812 P7_3_AMUXA = 4, /* Analog mux bus A */ 813 P7_3_AMUXB = 5, /* Analog mux bus B */ 814 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 815 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 816 P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 817 P7_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 818 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 819 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 820 P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 821 P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 822 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 823 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 824 825 /* P7.4 */ 826 P7_4_GPIO = 0, /* GPIO controls 'out' */ 827 P7_4_AMUXA = 4, /* Analog mux bus A */ 828 P7_4_AMUXB = 5, /* Analog mux bus B */ 829 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 830 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 831 P7_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 832 P7_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 833 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 834 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 835 P7_4_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 836 P7_4_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 837 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 838 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 839 840 /* P7.5 */ 841 P7_5_GPIO = 0, /* GPIO controls 'out' */ 842 P7_5_AMUXA = 4, /* Analog mux bus A */ 843 P7_5_AMUXB = 5, /* Analog mux bus B */ 844 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 845 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 846 P7_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 847 P7_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ 848 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 849 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 850 P7_5_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 851 P7_5_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 852 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 853 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 854 855 /* P7.6 */ 856 P7_6_GPIO = 0, /* GPIO controls 'out' */ 857 P7_6_AMUXA = 4, /* Analog mux bus A */ 858 P7_6_AMUXB = 5, /* Analog mux bus B */ 859 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 860 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 861 P7_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 862 P7_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ 863 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 864 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 865 P7_6_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 866 P7_6_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 867 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 868 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 869 870 /* P7.7 */ 871 P7_7_GPIO = 0, /* GPIO controls 'out' */ 872 P7_7_AMUXA = 4, /* Analog mux bus A */ 873 P7_7_AMUXB = 5, /* Analog mux bus B */ 874 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 875 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 876 P7_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 877 P7_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 878 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 879 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 880 P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 881 P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 882 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 883 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 884 885 /* P8.0 */ 886 P8_0_GPIO = 0, /* GPIO controls 'out' */ 887 P8_0_AMUXA = 4, /* Analog mux bus A */ 888 P8_0_AMUXB = 5, /* Analog mux bus B */ 889 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 890 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 891 P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 892 P8_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 893 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 894 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 895 P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 896 P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 897 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 898 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 899 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 900 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 901 902 /* P8.1 */ 903 P8_1_GPIO = 0, /* GPIO controls 'out' */ 904 P8_1_AMUXA = 4, /* Analog mux bus A */ 905 P8_1_AMUXB = 5, /* Analog mux bus B */ 906 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 907 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 908 P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 909 P8_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 910 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 911 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 912 P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 913 P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 914 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 915 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 916 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 917 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 918 919 /* P8.2 */ 920 P8_2_GPIO = 0, /* GPIO controls 'out' */ 921 P8_2_AMUXA = 4, /* Analog mux bus A */ 922 P8_2_AMUXB = 5, /* Analog mux bus B */ 923 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 924 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 925 P8_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 926 P8_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:2 */ 927 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 928 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 929 P8_2_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 930 P8_2_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 931 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 932 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 933 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 934 935 /* P8.3 */ 936 P8_3_GPIO = 0, /* GPIO controls 'out' */ 937 P8_3_AMUXA = 4, /* Analog mux bus A */ 938 P8_3_AMUXB = 5, /* Analog mux bus B */ 939 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 940 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 941 P8_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 942 P8_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:2 */ 943 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 944 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 945 P8_3_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 946 P8_3_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 947 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 948 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 949 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 950 951 /* P9.0 */ 952 P9_0_GPIO = 0, /* GPIO controls 'out' */ 953 P9_0_AMUXA = 4, /* Analog mux bus A */ 954 P9_0_AMUXB = 5, /* Analog mux bus B */ 955 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 956 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 957 P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 958 P9_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:2 */ 959 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 960 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 961 P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 962 P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 963 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 964 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 965 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 966 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 967 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 968 969 /* P9.1 */ 970 P9_1_GPIO = 0, /* GPIO controls 'out' */ 971 P9_1_AMUXA = 4, /* Analog mux bus A */ 972 P9_1_AMUXB = 5, /* Analog mux bus B */ 973 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 974 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 975 P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 976 P9_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:2 */ 977 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 978 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 979 P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 980 P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 981 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 982 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 983 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 984 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 985 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 986 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 987 988 /* P9.2 */ 989 P9_2_GPIO = 0, /* GPIO controls 'out' */ 990 P9_2_AMUXA = 4, /* Analog mux bus A */ 991 P9_2_AMUXB = 5, /* Analog mux bus B */ 992 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 993 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 994 P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 995 P9_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:2 */ 996 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 997 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 998 P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 999 P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 1000 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1001 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1002 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1003 1004 /* P9.3 */ 1005 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1006 P9_3_AMUXA = 4, /* Analog mux bus A */ 1007 P9_3_AMUXB = 5, /* Analog mux bus B */ 1008 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1009 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1010 P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 1011 P9_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:2 */ 1012 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1013 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1014 P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1015 P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1016 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1017 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1018 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1019 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1020 1021 /* P10.0 */ 1022 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1023 P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 1024 P10_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:2 */ 1025 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1026 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1027 P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1028 P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1029 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1030 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1031 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1032 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1033 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1034 1035 /* P10.1 */ 1036 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1037 P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 1038 P10_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:2 */ 1039 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1040 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1041 P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1042 P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1043 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1044 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1045 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1046 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1047 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1048 1049 /* P10.2 */ 1050 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1051 P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 1052 P10_2_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:2 */ 1053 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1054 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1055 P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1056 P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1057 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1058 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1059 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1060 1061 /* P10.3 */ 1062 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1063 P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 1064 P10_3_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:2 */ 1065 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1066 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1067 P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1068 P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1069 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1070 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1071 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1072 1073 /* P10.4 */ 1074 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1075 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1076 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:3 */ 1077 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1078 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1079 P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1080 P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1081 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1082 1083 /* P10.5 */ 1084 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1085 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1086 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:3 */ 1087 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1088 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1089 P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1090 P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1091 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1092 1093 /* P10.6 */ 1094 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1095 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1096 P10_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:3 */ 1097 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1098 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1099 P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1100 P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1101 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 1102 1103 /* P10.7 */ 1104 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1105 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1106 P10_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:3 */ 1107 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1108 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1109 P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1110 P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1111 1112 /* P11.0 */ 1113 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1114 P11_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:6 */ 1115 P11_0_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:3 */ 1116 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1117 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1118 P11_0_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1119 P11_0_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1120 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1121 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 1122 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 1123 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 1124 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1125 1126 /* P11.1 */ 1127 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1128 P11_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:6 */ 1129 P11_1_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:3 */ 1130 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1131 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1132 P11_1_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1133 P11_1_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1134 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1135 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 1136 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 1137 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 1138 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1139 1140 /* P11.2 */ 1141 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1142 P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ 1143 P11_2_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:3 */ 1144 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1145 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1146 P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1147 P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1148 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1149 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1150 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1151 1152 /* P11.3 */ 1153 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1154 P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ 1155 P11_3_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:3 */ 1156 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1157 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1158 P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1159 P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1160 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1161 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1162 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1163 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1164 1165 /* P11.4 */ 1166 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1167 P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:7 */ 1168 P11_4_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:3 */ 1169 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1170 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1171 P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1172 P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1173 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1174 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1175 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1176 1177 /* P11.5 */ 1178 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1179 P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:7 */ 1180 P11_5_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:3 */ 1181 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1182 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1183 P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1184 P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1185 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1186 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1187 1188 /* P11.6 */ 1189 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1190 P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:7 */ 1191 P11_6_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:3 */ 1192 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1193 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1194 P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1195 P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1196 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1197 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1198 1199 /* P11.7 */ 1200 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1201 P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:7 */ 1202 P11_7_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:3 */ 1203 P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1204 P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1205 P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1206 P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1207 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1208 1209 /* P12.0 */ 1210 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1211 P12_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:7 */ 1212 P12_0_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:3 */ 1213 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1214 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1215 P12_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1216 P12_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1217 P12_0_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:1 */ 1218 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 1219 1220 /* P12.1 */ 1221 P12_1_GPIO = 0, /* GPIO controls 'out' */ 1222 P12_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:7 */ 1223 P12_1_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:3 */ 1224 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1225 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1226 P12_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1227 P12_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1228 P12_1_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:1 */ 1229 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 1230 1231 /* P12.6 */ 1232 P12_6_GPIO = 0, /* GPIO controls 'out' */ 1233 P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:7 */ 1234 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:3 */ 1235 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1236 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1237 P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1238 P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1239 1240 /* P12.7 */ 1241 P12_7_GPIO = 0, /* GPIO controls 'out' */ 1242 P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:7 */ 1243 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:3 */ 1244 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1245 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1246 P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1247 P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1248 1249 /* USBDP */ 1250 USBDP_GPIO = 0, /* GPIO controls 'out' */ 1251 1252 /* USBDM */ 1253 USBDM_GPIO = 0 /* GPIO controls 'out' */ 1254 } en_hsiom_sel_t; 1255 1256 #endif /* _GPIO_PSOC6_03_100_TQFP_H_ */ 1257 1258 1259 /* [] END OF FILE */ 1260
