Home
last modified time | relevance | path

Searched refs:MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0 (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_syspm_v4.c1802 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0; in Cy_SysPm_SetSRAMMacroPwrModeInline()
1839 MXSRAMC_PWR_MACRO_CTL_LOCK(sramNum) = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0; in Cy_SysPm_GetSRAMMacroPwrMode()
Dcy_syspm_v2.c2121 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0; in Cy_SysPm_SetSRAMMacroPwrModeInline()
2160 MXSRAMC_PWR_MACRO_CTL_LOCK = MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0; in Cy_SysPm_GetSRAMMacroPwrMode()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h2520 #define MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0 0X00000001U macro