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Searched refs:MDCLK_EN (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_udb.h223 …__IOM uint32_t MDCLK_EN; /*!< 0x00000000 Master Digital Clock Enable Register… member
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h821 #define UDB_BCTL_MDCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN)
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h461 #define UDB_BCTL_MDCLK_EN (((UDB_V1_Type *) cy_device->udbBase)->BCTL.MDCLK_EN)