1 /***************************************************************************//** 2 * \file cyip_srss_v2.h 3 * 4 * \brief 5 * SRSS IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_SRSS_V2_H_ 28 #define _CYIP_SRSS_V2_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * SRSS 34 *******************************************************************************/ 35 36 #define CSV_HF_CSV_V2_SECTION_SIZE 0x00000010UL 37 #define CSV_HF_V2_SECTION_SIZE 0x00000100UL 38 #define CSV_REF_CSV_V2_SECTION_SIZE 0x00000010UL 39 #define CSV_REF_V2_SECTION_SIZE 0x00000010UL 40 #define CSV_LF_CSV_V2_SECTION_SIZE 0x00000010UL 41 #define CSV_LF_V2_SECTION_SIZE 0x00000010UL 42 #define CSV_ILO_CSV_V2_SECTION_SIZE 0x00000010UL 43 #define CSV_ILO_V2_SECTION_SIZE 0x00000010UL 44 #define MCWDT_CTR_V2_SECTION_SIZE 0x00000020UL 45 #define MCWDT_V2_SECTION_SIZE 0x00000100UL 46 #define WDT_V2_SECTION_SIZE 0x00000080UL 47 #define SRSS_V2_SECTION_SIZE 0x00010000UL 48 49 /** 50 * \brief Active domain Clock Supervisor (CSV) registers (CSV_HF_CSV) 51 */ 52 typedef struct { 53 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 54 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 55 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 56 __IM uint32_t RESERVED; 57 } CSV_HF_CSV_V2_Type; /*!< Size = 16 (0x10) */ 58 59 /** 60 * \brief Clock Supervisor (CSV) registers for Root clocks (CSV_HF) 61 */ 62 typedef struct { 63 CSV_HF_CSV_V2_Type CSV[16]; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers */ 64 } CSV_HF_V2_Type; /*!< Size = 256 (0x100) */ 65 66 /** 67 * \brief Active domain Clock Supervisor (CSV) registers for CSV Reference clock (CSV_REF_CSV) 68 */ 69 typedef struct { 70 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 71 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 72 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 73 __IM uint32_t RESERVED; 74 } CSV_REF_CSV_V2_Type; /*!< Size = 16 (0x10) */ 75 76 /** 77 * \brief CSV registers for the CSV Reference clock (CSV_REF) 78 */ 79 typedef struct { 80 CSV_REF_CSV_V2_Type CSV; /*!< 0x00000000 Active domain Clock Supervisor (CSV) registers for CSV 81 Reference clock */ 82 } CSV_REF_V2_Type; /*!< Size = 16 (0x10) */ 83 84 /** 85 * \brief LF clock Clock Supervisor registers (CSV_LF_CSV) 86 */ 87 typedef struct { 88 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 89 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 90 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 91 __IM uint32_t RESERVED; 92 } CSV_LF_CSV_V2_Type; /*!< Size = 16 (0x10) */ 93 94 /** 95 * \brief CSV registers for LF clock (CSV_LF) 96 */ 97 typedef struct { 98 CSV_LF_CSV_V2_Type CSV; /*!< 0x00000000 LF clock Clock Supervisor registers */ 99 } CSV_LF_V2_Type; /*!< Size = 16 (0x10) */ 100 101 /** 102 * \brief ILO0 clock DeepSleep domain Clock Supervisor registers (CSV_ILO_CSV) 103 */ 104 typedef struct { 105 __IOM uint32_t REF_CTL; /*!< 0x00000000 Clock Supervision Reference Control */ 106 __IOM uint32_t REF_LIMIT; /*!< 0x00000004 Clock Supervision Reference Limits */ 107 __IOM uint32_t MON_CTL; /*!< 0x00000008 Clock Supervision Monitor Control */ 108 __IM uint32_t RESERVED; 109 } CSV_ILO_CSV_V2_Type; /*!< Size = 16 (0x10) */ 110 111 /** 112 * \brief CSV registers for HVILO clock (CSV_ILO) 113 */ 114 typedef struct { 115 CSV_ILO_CSV_V2_Type CSV; /*!< 0x00000000 ILO0 clock DeepSleep domain Clock Supervisor registers */ 116 } CSV_ILO_V2_Type; /*!< Size = 16 (0x10) */ 117 118 /** 119 * \brief MCWDT Configuration for Subcounter 0 and 1 (MCWDT_CTR) 120 */ 121 typedef struct { 122 __IOM uint32_t CTL; /*!< 0x00000000 MCWDT Subcounter Control Register */ 123 __IOM uint32_t LOWER_LIMIT; /*!< 0x00000004 MCWDT Subcounter Lower Limit Register */ 124 __IOM uint32_t UPPER_LIMIT; /*!< 0x00000008 MCWDT Subcounter Upper Limit Register */ 125 __IOM uint32_t WARN_LIMIT; /*!< 0x0000000C MCWDT Subcounter Warn Limit Register */ 126 __IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Register */ 127 __IOM uint32_t CNT; /*!< 0x00000014 MCWDT Subcounter Count Register */ 128 __IM uint32_t RESERVED[2]; 129 } MCWDT_CTR_V2_Type; /*!< Size = 32 (0x20) */ 130 131 /** 132 * \brief Multi-Counter Watchdog Timer (MCWDT) 133 */ 134 typedef struct { 135 MCWDT_CTR_V2_Type CTR[2]; /*!< 0x00000000 MCWDT Configuration for Subcounter 0 and 1 */ 136 __IOM uint32_t CPU_SELECT; /*!< 0x00000040 MCWDT CPU selection register */ 137 __IM uint32_t RESERVED[15]; 138 __IOM uint32_t CTR2_CTL; /*!< 0x00000080 MCWDT Subcounter 2 Control register */ 139 __IOM uint32_t CTR2_CONFIG; /*!< 0x00000084 MCWDT Subcounter 2 Configuration register */ 140 __IOM uint32_t CTR2_CNT; /*!< 0x00000088 MCWDT Subcounter 2 Count Register */ 141 __IM uint32_t RESERVED1; 142 __IOM uint32_t LOCK; /*!< 0x00000090 MCWDT Lock Register */ 143 __IOM uint32_t SERVICE; /*!< 0x00000094 MCWDT Service Register */ 144 __IM uint32_t RESERVED2[2]; 145 __IOM uint32_t INTR; /*!< 0x000000A0 MCWDT Interrupt Register */ 146 __IOM uint32_t INTR_SET; /*!< 0x000000A4 MCWDT Interrupt Set Register */ 147 __IOM uint32_t INTR_MASK; /*!< 0x000000A8 MCWDT Interrupt Mask Register */ 148 __IM uint32_t INTR_MASKED; /*!< 0x000000AC MCWDT Interrupt Masked Register */ 149 __IM uint32_t RESERVED3[20]; 150 } MCWDT_V2_Type; /*!< Size = 256 (0x100) */ 151 152 /** 153 * \brief Watchdog Timer (WDT) 154 */ 155 typedef struct { 156 __IOM uint32_t CTL; /*!< 0x00000000 WDT Control Register */ 157 __IOM uint32_t LOWER_LIMIT; /*!< 0x00000004 WDT Lower Limit Register */ 158 __IOM uint32_t UPPER_LIMIT; /*!< 0x00000008 WDT Upper Limit Register */ 159 __IOM uint32_t WARN_LIMIT; /*!< 0x0000000C WDT Warn Limit Register */ 160 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ 161 __IOM uint32_t CNT; /*!< 0x00000014 WDT Count Register */ 162 __IM uint32_t RESERVED[10]; 163 __IOM uint32_t LOCK; /*!< 0x00000040 WDT Lock register */ 164 __IOM uint32_t SERVICE; /*!< 0x00000044 WDT Service register */ 165 __IM uint32_t RESERVED1[2]; 166 __IOM uint32_t INTR; /*!< 0x00000050 WDT Interrupt Register */ 167 __IOM uint32_t INTR_SET; /*!< 0x00000054 WDT Interrupt Set Register */ 168 __IOM uint32_t INTR_MASK; /*!< 0x00000058 WDT Interrupt Mask Register */ 169 __IM uint32_t INTR_MASKED; /*!< 0x0000005C WDT Interrupt Masked Register */ 170 __IM uint32_t RESERVED2[8]; 171 } WDT_V2_Type; /*!< Size = 128 (0x80) */ 172 173 /** 174 * \brief SRSS Core Registers (ver2) (SRSS) 175 */ 176 typedef struct { 177 __IM uint32_t RESERVED[16]; 178 __IM uint32_t PWR_LVD_STATUS; /*!< 0x00000040 High Voltage / Low Voltage Detector (HVLVD) Status Register */ 179 __IM uint32_t PWR_LVD_STATUS2; /*!< 0x00000044 High Voltage / Low Voltage Detector (HVLVD) Status Register #2 */ 180 __IM uint32_t RESERVED1[46]; 181 __IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000100 Clock DSI Select Register */ 182 __IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000140 Fast Clock Output Select Register */ 183 __IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000144 Slow Clock Output Select Register */ 184 __IOM uint32_t CLK_CAL_CNT1; /*!< 0x00000148 Clock Calibration Counter 1 */ 185 __IM uint32_t CLK_CAL_CNT2; /*!< 0x0000014C Clock Calibration Counter 2 */ 186 __IM uint32_t RESERVED2[44]; 187 __IOM uint32_t SRSS_INTR; /*!< 0x00000200 SRSS Interrupt Register */ 188 __IOM uint32_t SRSS_INTR_SET; /*!< 0x00000204 SRSS Interrupt Set Register */ 189 __IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000208 SRSS Interrupt Mask Register */ 190 __IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000020C SRSS Interrupt Masked Register */ 191 __IM uint32_t RESERVED3[892]; 192 __IM uint32_t PWR_CTL; /*!< 0x00001000 Power Mode Control */ 193 __IOM uint32_t PWR_CTL2; /*!< 0x00001004 Power Mode Control 2 */ 194 __IOM uint32_t PWR_HIBERNATE; /*!< 0x00001008 HIBERNATE Mode Register */ 195 __IM uint32_t RESERVED4; 196 __IOM uint32_t PWR_BUCK_CTL; /*!< 0x00001010 SIMO Buck Control Register */ 197 __IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00001014 SIMO Buck Control Register 2 */ 198 __IOM uint32_t PWR_SSV_CTL; /*!< 0x00001018 Supply Supervision Control Register */ 199 __IM uint32_t PWR_SSV_STATUS; /*!< 0x0000101C Supply Supervision Status Register */ 200 __IOM uint32_t PWR_LVD_CTL; /*!< 0x00001020 High Voltage / Low Voltage Detector (HVLVD) Configuration 201 Register */ 202 __IOM uint32_t PWR_LVD_CTL2; /*!< 0x00001024 High Voltage / Low Voltage Detector (HVLVD) Configuration 203 Register #2 */ 204 __IM uint32_t RESERVED5[6]; 205 __IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00001040 HIBERNATE Data Register */ 206 __IM uint32_t RESERVED6[96]; 207 __IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00001200 Clock Path Select Register */ 208 __IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00001240 Clock Root Select Register */ 209 __IM uint32_t RESERVED7[96]; 210 CSV_HF_V2_Type CSV_HF; /*!< 0x00001400 Clock Supervisor (CSV) registers for Root clocks */ 211 __IOM uint32_t CLK_SELECT; /*!< 0x00001500 Clock selection register */ 212 __IOM uint32_t CLK_TIMER_CTL; /*!< 0x00001504 Timer Clock Control Register */ 213 __IOM uint32_t CLK_ILO0_CONFIG; /*!< 0x00001508 ILO0 Configuration */ 214 __IOM uint32_t CLK_ILO1_CONFIG; /*!< 0x0000150C ILO1 Configuration */ 215 __IM uint32_t RESERVED8[2]; 216 __IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00001518 IMO Configuration */ 217 __IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000151C ECO Configuration Register */ 218 __IOM uint32_t CLK_ECO_PRESCALE; /*!< 0x00001520 ECO Prescaler Configuration Register */ 219 __IM uint32_t CLK_ECO_STATUS; /*!< 0x00001524 ECO Status Register */ 220 __IOM uint32_t CLK_PILO_CONFIG; /*!< 0x00001528 Precision ILO Configuration Register */ 221 __IM uint32_t RESERVED9; 222 __IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00001530 FLL Configuration Register */ 223 __IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00001534 FLL Configuration Register 2 */ 224 __IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00001538 FLL Configuration Register 3 */ 225 __IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000153C FLL Configuration Register 4 */ 226 __IOM uint32_t CLK_FLL_STATUS; /*!< 0x00001540 FLL Status Register */ 227 __IOM uint32_t CLK_ECO_CONFIG2; /*!< 0x00001544 ECO Configuration Register 2 */ 228 __IM uint32_t RESERVED10[46]; 229 __IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00001600 PLL Configuration Register */ 230 __IM uint32_t RESERVED11; 231 __IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00001640 PLL Status Register */ 232 __IM uint32_t RESERVED12[33]; 233 __IOM uint32_t CSV_REF_SEL; /*!< 0x00001700 Select CSV Reference clock for Active domain */ 234 __IM uint32_t RESERVED13[3]; 235 CSV_REF_V2_Type CSV_REF; /*!< 0x00001710 CSV registers for the CSV Reference clock */ 236 CSV_LF_V2_Type CSV_LF; /*!< 0x00001720 CSV registers for LF clock */ 237 CSV_ILO_V2_Type CSV_ILO; /*!< 0x00001730 CSV registers for HVILO clock */ 238 __IM uint32_t RESERVED14[48]; 239 __IOM uint32_t RES_CAUSE; /*!< 0x00001800 Reset Cause Observation Register */ 240 __IOM uint32_t RES_CAUSE2; /*!< 0x00001804 Reset Cause Observation Register 2 */ 241 __IM uint32_t RESERVED15[1539]; 242 __IOM uint32_t CLK_TRIM_ILO0_CTL; /*!< 0x00003014 ILO0 Trim Register */ 243 __IM uint32_t RESERVED16[60]; 244 __IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x00003108 Power System Trim Register */ 245 __IM uint32_t RESERVED17[2]; 246 __IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x00003114 PILO Trim Register */ 247 __IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x00003118 PILO Trim Register 2 */ 248 __IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000311C PILO Trim Register 3 */ 249 __IM uint32_t RESERVED18[64]; 250 __IOM uint32_t CLK_TRIM_ILO1_CTL; /*!< 0x00003220 ILO1 Trim Register */ 251 __IM uint32_t RESERVED19[4983]; 252 MCWDT_V2_Type MCWDT[4]; /*!< 0x00008000 Multi-Counter Watchdog Timer */ 253 __IM uint32_t RESERVED20[3840]; 254 WDT_V2_Type WDT_STRUCT; /*!< 0x0000C000 Watchdog Timer */ 255 } SRSS_V2_Type; /*!< Size = 49280 (0xC080) */ 256 257 258 /* CSV_HF_CSV.REF_CTL */ 259 #define CSV_HF_CSV_V2_REF_CTL_STARTUP_Pos 0UL 260 #define CSV_HF_CSV_V2_REF_CTL_STARTUP_Msk 0xFFFFUL 261 #define CSV_HF_CSV_V2_REF_CTL_CSV_ACTION_Pos 30UL 262 #define CSV_HF_CSV_V2_REF_CTL_CSV_ACTION_Msk 0x40000000UL 263 #define CSV_HF_CSV_V2_REF_CTL_CSV_EN_Pos 31UL 264 #define CSV_HF_CSV_V2_REF_CTL_CSV_EN_Msk 0x80000000UL 265 /* CSV_HF_CSV.REF_LIMIT */ 266 #define CSV_HF_CSV_V2_REF_LIMIT_LOWER_Pos 0UL 267 #define CSV_HF_CSV_V2_REF_LIMIT_LOWER_Msk 0xFFFFUL 268 #define CSV_HF_CSV_V2_REF_LIMIT_UPPER_Pos 16UL 269 #define CSV_HF_CSV_V2_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 270 /* CSV_HF_CSV.MON_CTL */ 271 #define CSV_HF_CSV_V2_MON_CTL_PERIOD_Pos 0UL 272 #define CSV_HF_CSV_V2_MON_CTL_PERIOD_Msk 0xFFFFUL 273 274 275 /* CSV_REF_CSV.REF_CTL */ 276 #define CSV_REF_CSV_V2_REF_CTL_STARTUP_Pos 0UL 277 #define CSV_REF_CSV_V2_REF_CTL_STARTUP_Msk 0xFFFFUL 278 #define CSV_REF_CSV_V2_REF_CTL_CSV_ACTION_Pos 30UL 279 #define CSV_REF_CSV_V2_REF_CTL_CSV_ACTION_Msk 0x40000000UL 280 #define CSV_REF_CSV_V2_REF_CTL_CSV_EN_Pos 31UL 281 #define CSV_REF_CSV_V2_REF_CTL_CSV_EN_Msk 0x80000000UL 282 /* CSV_REF_CSV.REF_LIMIT */ 283 #define CSV_REF_CSV_V2_REF_LIMIT_LOWER_Pos 0UL 284 #define CSV_REF_CSV_V2_REF_LIMIT_LOWER_Msk 0xFFFFUL 285 #define CSV_REF_CSV_V2_REF_LIMIT_UPPER_Pos 16UL 286 #define CSV_REF_CSV_V2_REF_LIMIT_UPPER_Msk 0xFFFF0000UL 287 /* CSV_REF_CSV.MON_CTL */ 288 #define CSV_REF_CSV_V2_MON_CTL_PERIOD_Pos 0UL 289 #define CSV_REF_CSV_V2_MON_CTL_PERIOD_Msk 0xFFFFUL 290 291 292 /* CSV_LF_CSV.REF_CTL */ 293 #define CSV_LF_CSV_V2_REF_CTL_STARTUP_Pos 0UL 294 #define CSV_LF_CSV_V2_REF_CTL_STARTUP_Msk 0xFFUL 295 #define CSV_LF_CSV_V2_REF_CTL_CSV_EN_Pos 31UL 296 #define CSV_LF_CSV_V2_REF_CTL_CSV_EN_Msk 0x80000000UL 297 /* CSV_LF_CSV.REF_LIMIT */ 298 #define CSV_LF_CSV_V2_REF_LIMIT_LOWER_Pos 0UL 299 #define CSV_LF_CSV_V2_REF_LIMIT_LOWER_Msk 0xFFUL 300 #define CSV_LF_CSV_V2_REF_LIMIT_UPPER_Pos 16UL 301 #define CSV_LF_CSV_V2_REF_LIMIT_UPPER_Msk 0xFF0000UL 302 /* CSV_LF_CSV.MON_CTL */ 303 #define CSV_LF_CSV_V2_MON_CTL_PERIOD_Pos 0UL 304 #define CSV_LF_CSV_V2_MON_CTL_PERIOD_Msk 0xFFUL 305 306 307 /* CSV_ILO_CSV.REF_CTL */ 308 #define CSV_ILO_CSV_V2_REF_CTL_STARTUP_Pos 0UL 309 #define CSV_ILO_CSV_V2_REF_CTL_STARTUP_Msk 0xFFUL 310 #define CSV_ILO_CSV_V2_REF_CTL_CSV_EN_Pos 31UL 311 #define CSV_ILO_CSV_V2_REF_CTL_CSV_EN_Msk 0x80000000UL 312 /* CSV_ILO_CSV.REF_LIMIT */ 313 #define CSV_ILO_CSV_V2_REF_LIMIT_LOWER_Pos 0UL 314 #define CSV_ILO_CSV_V2_REF_LIMIT_LOWER_Msk 0xFFUL 315 #define CSV_ILO_CSV_V2_REF_LIMIT_UPPER_Pos 16UL 316 #define CSV_ILO_CSV_V2_REF_LIMIT_UPPER_Msk 0xFF0000UL 317 /* CSV_ILO_CSV.MON_CTL */ 318 #define CSV_ILO_CSV_V2_MON_CTL_PERIOD_Pos 0UL 319 #define CSV_ILO_CSV_V2_MON_CTL_PERIOD_Msk 0xFFUL 320 321 322 /* MCWDT_CTR.CTL */ 323 #define MCWDT_CTR_V2_CTL_ENABLED_Pos 0UL 324 #define MCWDT_CTR_V2_CTL_ENABLED_Msk 0x1UL 325 #define MCWDT_CTR_V2_CTL_ENABLE_Pos 31UL 326 #define MCWDT_CTR_V2_CTL_ENABLE_Msk 0x80000000UL 327 /* MCWDT_CTR.LOWER_LIMIT */ 328 #define MCWDT_CTR_V2_LOWER_LIMIT_LOWER_LIMIT_Pos 0UL 329 #define MCWDT_CTR_V2_LOWER_LIMIT_LOWER_LIMIT_Msk 0xFFFFUL 330 /* MCWDT_CTR.UPPER_LIMIT */ 331 #define MCWDT_CTR_V2_UPPER_LIMIT_UPPER_LIMIT_Pos 0UL 332 #define MCWDT_CTR_V2_UPPER_LIMIT_UPPER_LIMIT_Msk 0xFFFFUL 333 /* MCWDT_CTR.WARN_LIMIT */ 334 #define MCWDT_CTR_V2_WARN_LIMIT_WARN_LIMIT_Pos 0UL 335 #define MCWDT_CTR_V2_WARN_LIMIT_WARN_LIMIT_Msk 0xFFFFUL 336 /* MCWDT_CTR.CONFIG */ 337 #define MCWDT_CTR_V2_CONFIG_LOWER_ACTION_Pos 0UL 338 #define MCWDT_CTR_V2_CONFIG_LOWER_ACTION_Msk 0x3UL 339 #define MCWDT_CTR_V2_CONFIG_UPPER_ACTION_Pos 4UL 340 #define MCWDT_CTR_V2_CONFIG_UPPER_ACTION_Msk 0x30UL 341 #define MCWDT_CTR_V2_CONFIG_WARN_ACTION_Pos 8UL 342 #define MCWDT_CTR_V2_CONFIG_WARN_ACTION_Msk 0x100UL 343 #define MCWDT_CTR_V2_CONFIG_AUTO_SERVICE_Pos 12UL 344 #define MCWDT_CTR_V2_CONFIG_AUTO_SERVICE_Msk 0x1000UL 345 #define MCWDT_CTR_V2_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 346 #define MCWDT_CTR_V2_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 347 #define MCWDT_CTR_V2_CONFIG_SLEEPDEEP_PAUSE_Pos 30UL 348 #define MCWDT_CTR_V2_CONFIG_SLEEPDEEP_PAUSE_Msk 0x40000000UL 349 #define MCWDT_CTR_V2_CONFIG_DEBUG_RUN_Pos 31UL 350 #define MCWDT_CTR_V2_CONFIG_DEBUG_RUN_Msk 0x80000000UL 351 /* MCWDT_CTR.CNT */ 352 #define MCWDT_CTR_V2_CNT_CNT_Pos 0UL 353 #define MCWDT_CTR_V2_CNT_CNT_Msk 0xFFFFUL 354 355 356 /* MCWDT.CPU_SELECT */ 357 #define MCWDT_V2_CPU_SELECT_CPU_SEL_Pos 0UL 358 #define MCWDT_V2_CPU_SELECT_CPU_SEL_Msk 0x3UL 359 /* MCWDT.CTR2_CTL */ 360 #define MCWDT_V2_CTR2_CTL_ENABLED_Pos 0UL 361 #define MCWDT_V2_CTR2_CTL_ENABLED_Msk 0x1UL 362 #define MCWDT_V2_CTR2_CTL_ENABLE_Pos 31UL 363 #define MCWDT_V2_CTR2_CTL_ENABLE_Msk 0x80000000UL 364 /* MCWDT.CTR2_CONFIG */ 365 #define MCWDT_V2_CTR2_CONFIG_ACTION_Pos 0UL 366 #define MCWDT_V2_CTR2_CONFIG_ACTION_Msk 0x1UL 367 #define MCWDT_V2_CTR2_CONFIG_BITS_Pos 16UL 368 #define MCWDT_V2_CTR2_CONFIG_BITS_Msk 0x1F0000UL 369 #define MCWDT_V2_CTR2_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 370 #define MCWDT_V2_CTR2_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 371 #define MCWDT_V2_CTR2_CONFIG_SLEEPDEEP_PAUSE_Pos 30UL 372 #define MCWDT_V2_CTR2_CONFIG_SLEEPDEEP_PAUSE_Msk 0x40000000UL 373 #define MCWDT_V2_CTR2_CONFIG_DEBUG_RUN_Pos 31UL 374 #define MCWDT_V2_CTR2_CONFIG_DEBUG_RUN_Msk 0x80000000UL 375 /* MCWDT.CTR2_CNT */ 376 #define MCWDT_V2_CTR2_CNT_CNT2_Pos 0UL 377 #define MCWDT_V2_CTR2_CNT_CNT2_Msk 0xFFFFFFFFUL 378 /* MCWDT.LOCK */ 379 #define MCWDT_V2_LOCK_MCWDT_LOCK_Pos 0UL 380 #define MCWDT_V2_LOCK_MCWDT_LOCK_Msk 0x3UL 381 /* MCWDT.SERVICE */ 382 #define MCWDT_V2_SERVICE_CTR0_SERVICE_Pos 0UL 383 #define MCWDT_V2_SERVICE_CTR0_SERVICE_Msk 0x1UL 384 #define MCWDT_V2_SERVICE_CTR1_SERVICE_Pos 1UL 385 #define MCWDT_V2_SERVICE_CTR1_SERVICE_Msk 0x2UL 386 /* MCWDT.INTR */ 387 #define MCWDT_V2_INTR_CTR0_INT_Pos 0UL 388 #define MCWDT_V2_INTR_CTR0_INT_Msk 0x1UL 389 #define MCWDT_V2_INTR_CTR1_INT_Pos 1UL 390 #define MCWDT_V2_INTR_CTR1_INT_Msk 0x2UL 391 #define MCWDT_V2_INTR_CTR2_INT_Pos 2UL 392 #define MCWDT_V2_INTR_CTR2_INT_Msk 0x4UL 393 /* MCWDT.INTR_SET */ 394 #define MCWDT_V2_INTR_SET_CTR0_INT_Pos 0UL 395 #define MCWDT_V2_INTR_SET_CTR0_INT_Msk 0x1UL 396 #define MCWDT_V2_INTR_SET_CTR1_INT_Pos 1UL 397 #define MCWDT_V2_INTR_SET_CTR1_INT_Msk 0x2UL 398 #define MCWDT_V2_INTR_SET_CTR2_INT_Pos 2UL 399 #define MCWDT_V2_INTR_SET_CTR2_INT_Msk 0x4UL 400 /* MCWDT.INTR_MASK */ 401 #define MCWDT_V2_INTR_MASK_CTR0_INT_Pos 0UL 402 #define MCWDT_V2_INTR_MASK_CTR0_INT_Msk 0x1UL 403 #define MCWDT_V2_INTR_MASK_CTR1_INT_Pos 1UL 404 #define MCWDT_V2_INTR_MASK_CTR1_INT_Msk 0x2UL 405 #define MCWDT_V2_INTR_MASK_CTR2_INT_Pos 2UL 406 #define MCWDT_V2_INTR_MASK_CTR2_INT_Msk 0x4UL 407 /* MCWDT.INTR_MASKED */ 408 #define MCWDT_V2_INTR_MASKED_CTR0_INT_Pos 0UL 409 #define MCWDT_V2_INTR_MASKED_CTR0_INT_Msk 0x1UL 410 #define MCWDT_V2_INTR_MASKED_CTR1_INT_Pos 1UL 411 #define MCWDT_V2_INTR_MASKED_CTR1_INT_Msk 0x2UL 412 #define MCWDT_V2_INTR_MASKED_CTR2_INT_Pos 2UL 413 #define MCWDT_V2_INTR_MASKED_CTR2_INT_Msk 0x4UL 414 415 416 /* WDT.CTL */ 417 #define WDT_V2_CTL_ENABLED_Pos 0UL 418 #define WDT_V2_CTL_ENABLED_Msk 0x1UL 419 #define WDT_V2_CTL_ENABLE_Pos 31UL 420 #define WDT_V2_CTL_ENABLE_Msk 0x80000000UL 421 /* WDT.LOWER_LIMIT */ 422 #define WDT_V2_LOWER_LIMIT_LOWER_LIMIT_Pos 0UL 423 #define WDT_V2_LOWER_LIMIT_LOWER_LIMIT_Msk 0xFFFFFFFFUL 424 /* WDT.UPPER_LIMIT */ 425 #define WDT_V2_UPPER_LIMIT_UPPER_LIMIT_Pos 0UL 426 #define WDT_V2_UPPER_LIMIT_UPPER_LIMIT_Msk 0xFFFFFFFFUL 427 /* WDT.WARN_LIMIT */ 428 #define WDT_V2_WARN_LIMIT_WARN_LIMIT_Pos 0UL 429 #define WDT_V2_WARN_LIMIT_WARN_LIMIT_Msk 0xFFFFFFFFUL 430 /* WDT.CONFIG */ 431 #define WDT_V2_CONFIG_LOWER_ACTION_Pos 0UL 432 #define WDT_V2_CONFIG_LOWER_ACTION_Msk 0x1UL 433 #define WDT_V2_CONFIG_UPPER_ACTION_Pos 4UL 434 #define WDT_V2_CONFIG_UPPER_ACTION_Msk 0x10UL 435 #define WDT_V2_CONFIG_WARN_ACTION_Pos 8UL 436 #define WDT_V2_CONFIG_WARN_ACTION_Msk 0x100UL 437 #define WDT_V2_CONFIG_AUTO_SERVICE_Pos 12UL 438 #define WDT_V2_CONFIG_AUTO_SERVICE_Msk 0x1000UL 439 #define WDT_V2_CONFIG_DEBUG_TRIGGER_EN_Pos 28UL 440 #define WDT_V2_CONFIG_DEBUG_TRIGGER_EN_Msk 0x10000000UL 441 #define WDT_V2_CONFIG_DPSLP_PAUSE_Pos 29UL 442 #define WDT_V2_CONFIG_DPSLP_PAUSE_Msk 0x20000000UL 443 #define WDT_V2_CONFIG_HIB_PAUSE_Pos 30UL 444 #define WDT_V2_CONFIG_HIB_PAUSE_Msk 0x40000000UL 445 #define WDT_V2_CONFIG_DEBUG_RUN_Pos 31UL 446 #define WDT_V2_CONFIG_DEBUG_RUN_Msk 0x80000000UL 447 /* WDT.CNT */ 448 #define WDT_V2_CNT_CNT_Pos 0UL 449 #define WDT_V2_CNT_CNT_Msk 0xFFFFFFFFUL 450 /* WDT.LOCK */ 451 #define WDT_V2_LOCK_WDT_LOCK_Pos 0UL 452 #define WDT_V2_LOCK_WDT_LOCK_Msk 0x3UL 453 /* WDT.SERVICE */ 454 #define WDT_V2_SERVICE_SERVICE_Pos 0UL 455 #define WDT_V2_SERVICE_SERVICE_Msk 0x1UL 456 /* WDT.INTR */ 457 #define WDT_V2_INTR_WDT_Pos 0UL 458 #define WDT_V2_INTR_WDT_Msk 0x1UL 459 /* WDT.INTR_SET */ 460 #define WDT_V2_INTR_SET_WDT_Pos 0UL 461 #define WDT_V2_INTR_SET_WDT_Msk 0x1UL 462 /* WDT.INTR_MASK */ 463 #define WDT_V2_INTR_MASK_WDT_Pos 0UL 464 #define WDT_V2_INTR_MASK_WDT_Msk 0x1UL 465 /* WDT.INTR_MASKED */ 466 #define WDT_V2_INTR_MASKED_WDT_Pos 0UL 467 #define WDT_V2_INTR_MASKED_WDT_Msk 0x1UL 468 469 470 /* SRSS.PWR_LVD_STATUS */ 471 #define SRSS_V2_PWR_LVD_STATUS_HVLVD1_OUT_Pos 0UL 472 #define SRSS_V2_PWR_LVD_STATUS_HVLVD1_OUT_Msk 0x1UL 473 /* SRSS.PWR_LVD_STATUS2 */ 474 #define SRSS_V2_PWR_LVD_STATUS2_HVLVD2_OUT_Pos 0UL 475 #define SRSS_V2_PWR_LVD_STATUS2_HVLVD2_OUT_Msk 0x1UL 476 /* SRSS.CLK_DSI_SELECT */ 477 #define SRSS_V2_CLK_DSI_SELECT_DSI_MUX_Pos 0UL 478 #define SRSS_V2_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL 479 /* SRSS.CLK_OUTPUT_FAST */ 480 #define SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL 481 #define SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL 482 #define SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL 483 #define SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL 484 #define SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL 485 #define SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL 486 #define SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL 487 #define SRSS_V2_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL 488 #define SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL 489 #define SRSS_V2_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL 490 #define SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL 491 #define SRSS_V2_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL 492 /* SRSS.CLK_OUTPUT_SLOW */ 493 #define SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL 494 #define SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL 495 #define SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL 496 #define SRSS_V2_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL 497 /* SRSS.CLK_CAL_CNT1 */ 498 #define SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL 499 #define SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL 500 #define SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL 501 #define SRSS_V2_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL 502 /* SRSS.CLK_CAL_CNT2 */ 503 #define SRSS_V2_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL 504 #define SRSS_V2_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL 505 /* SRSS.SRSS_INTR */ 506 #define SRSS_V2_SRSS_INTR_HVLVD1_Pos 1UL 507 #define SRSS_V2_SRSS_INTR_HVLVD1_Msk 0x2UL 508 #define SRSS_V2_SRSS_INTR_HVLVD2_Pos 2UL 509 #define SRSS_V2_SRSS_INTR_HVLVD2_Msk 0x4UL 510 #define SRSS_V2_SRSS_INTR_CLK_CAL_Pos 5UL 511 #define SRSS_V2_SRSS_INTR_CLK_CAL_Msk 0x20UL 512 /* SRSS.SRSS_INTR_SET */ 513 #define SRSS_V2_SRSS_INTR_SET_HVLVD1_Pos 1UL 514 #define SRSS_V2_SRSS_INTR_SET_HVLVD1_Msk 0x2UL 515 #define SRSS_V2_SRSS_INTR_SET_HVLVD2_Pos 2UL 516 #define SRSS_V2_SRSS_INTR_SET_HVLVD2_Msk 0x4UL 517 #define SRSS_V2_SRSS_INTR_SET_CLK_CAL_Pos 5UL 518 #define SRSS_V2_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL 519 /* SRSS.SRSS_INTR_MASK */ 520 #define SRSS_V2_SRSS_INTR_MASK_HVLVD1_Pos 1UL 521 #define SRSS_V2_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL 522 #define SRSS_V2_SRSS_INTR_MASK_HVLVD2_Pos 2UL 523 #define SRSS_V2_SRSS_INTR_MASK_HVLVD2_Msk 0x4UL 524 #define SRSS_V2_SRSS_INTR_MASK_CLK_CAL_Pos 5UL 525 #define SRSS_V2_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL 526 /* SRSS.SRSS_INTR_MASKED */ 527 #define SRSS_V2_SRSS_INTR_MASKED_HVLVD1_Pos 1UL 528 #define SRSS_V2_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL 529 #define SRSS_V2_SRSS_INTR_MASKED_HVLVD2_Pos 2UL 530 #define SRSS_V2_SRSS_INTR_MASKED_HVLVD2_Msk 0x4UL 531 #define SRSS_V2_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL 532 #define SRSS_V2_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL 533 /* SRSS.PWR_CTL */ 534 #define SRSS_V2_PWR_CTL_POWER_MODE_Pos 0UL 535 #define SRSS_V2_PWR_CTL_POWER_MODE_Msk 0x3UL 536 #define SRSS_V2_PWR_CTL_DEBUG_SESSION_Pos 4UL 537 #define SRSS_V2_PWR_CTL_DEBUG_SESSION_Msk 0x10UL 538 #define SRSS_V2_PWR_CTL_LPM_READY_Pos 5UL 539 #define SRSS_V2_PWR_CTL_LPM_READY_Msk 0x20UL 540 /* SRSS.PWR_CTL2 */ 541 #define SRSS_V2_PWR_CTL2_LINREG_DIS_Pos 0UL 542 #define SRSS_V2_PWR_CTL2_LINREG_DIS_Msk 0x1UL 543 #define SRSS_V2_PWR_CTL2_LINREG_OK_Pos 1UL 544 #define SRSS_V2_PWR_CTL2_LINREG_OK_Msk 0x2UL 545 #define SRSS_V2_PWR_CTL2_LINREG_LPMODE_Pos 2UL 546 #define SRSS_V2_PWR_CTL2_LINREG_LPMODE_Msk 0x4UL 547 #define SRSS_V2_PWR_CTL2_DPSLP_REG_DIS_Pos 4UL 548 #define SRSS_V2_PWR_CTL2_DPSLP_REG_DIS_Msk 0x10UL 549 #define SRSS_V2_PWR_CTL2_RET_REG_DIS_Pos 8UL 550 #define SRSS_V2_PWR_CTL2_RET_REG_DIS_Msk 0x100UL 551 #define SRSS_V2_PWR_CTL2_NWELL_REG_DIS_Pos 12UL 552 #define SRSS_V2_PWR_CTL2_NWELL_REG_DIS_Msk 0x1000UL 553 #define SRSS_V2_PWR_CTL2_REFV_DIS_Pos 16UL 554 #define SRSS_V2_PWR_CTL2_REFV_DIS_Msk 0x10000UL 555 #define SRSS_V2_PWR_CTL2_REFV_OK_Pos 17UL 556 #define SRSS_V2_PWR_CTL2_REFV_OK_Msk 0x20000UL 557 #define SRSS_V2_PWR_CTL2_REFVBUF_DIS_Pos 20UL 558 #define SRSS_V2_PWR_CTL2_REFVBUF_DIS_Msk 0x100000UL 559 #define SRSS_V2_PWR_CTL2_REFVBUF_OK_Pos 21UL 560 #define SRSS_V2_PWR_CTL2_REFVBUF_OK_Msk 0x200000UL 561 #define SRSS_V2_PWR_CTL2_REFVBUF_LPMODE_Pos 22UL 562 #define SRSS_V2_PWR_CTL2_REFVBUF_LPMODE_Msk 0x400000UL 563 #define SRSS_V2_PWR_CTL2_REFI_DIS_Pos 24UL 564 #define SRSS_V2_PWR_CTL2_REFI_DIS_Msk 0x1000000UL 565 #define SRSS_V2_PWR_CTL2_REFI_OK_Pos 25UL 566 #define SRSS_V2_PWR_CTL2_REFI_OK_Msk 0x2000000UL 567 #define SRSS_V2_PWR_CTL2_REFI_LPMODE_Pos 26UL 568 #define SRSS_V2_PWR_CTL2_REFI_LPMODE_Msk 0x4000000UL 569 #define SRSS_V2_PWR_CTL2_PORBOD_LPMODE_Pos 27UL 570 #define SRSS_V2_PWR_CTL2_PORBOD_LPMODE_Msk 0x8000000UL 571 #define SRSS_V2_PWR_CTL2_BGREF_LPMODE_Pos 28UL 572 #define SRSS_V2_PWR_CTL2_BGREF_LPMODE_Msk 0x10000000UL 573 #define SRSS_V2_PWR_CTL2_PLL_LS_BYPASS_Pos 31UL 574 #define SRSS_V2_PWR_CTL2_PLL_LS_BYPASS_Msk 0x80000000UL 575 /* SRSS.PWR_HIBERNATE */ 576 #define SRSS_V2_PWR_HIBERNATE_TOKEN_Pos 0UL 577 #define SRSS_V2_PWR_HIBERNATE_TOKEN_Msk 0xFFUL 578 #define SRSS_V2_PWR_HIBERNATE_UNLOCK_Pos 8UL 579 #define SRSS_V2_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL 580 #define SRSS_V2_PWR_HIBERNATE_FREEZE_Pos 17UL 581 #define SRSS_V2_PWR_HIBERNATE_FREEZE_Msk 0x20000UL 582 #define SRSS_V2_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL 583 #define SRSS_V2_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL 584 #define SRSS_V2_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL 585 #define SRSS_V2_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL 586 #define SRSS_V2_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL 587 #define SRSS_V2_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL 588 #define SRSS_V2_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL 589 #define SRSS_V2_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL 590 #define SRSS_V2_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL 591 #define SRSS_V2_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL 592 #define SRSS_V2_PWR_HIBERNATE_HIBERNATE_Pos 31UL 593 #define SRSS_V2_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL 594 /* SRSS.PWR_BUCK_CTL */ 595 #define SRSS_V2_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL 596 #define SRSS_V2_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL 597 #define SRSS_V2_PWR_BUCK_CTL_BUCK_EN_Pos 30UL 598 #define SRSS_V2_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL 599 #define SRSS_V2_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL 600 #define SRSS_V2_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL 601 /* SRSS.PWR_BUCK_CTL2 */ 602 #define SRSS_V2_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL 603 #define SRSS_V2_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL 604 #define SRSS_V2_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL 605 #define SRSS_V2_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL 606 #define SRSS_V2_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL 607 #define SRSS_V2_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL 608 /* SRSS.PWR_SSV_CTL */ 609 #define SRSS_V2_PWR_SSV_CTL_BODVDDD_VSEL_Pos 0UL 610 #define SRSS_V2_PWR_SSV_CTL_BODVDDD_VSEL_Msk 0x1UL 611 #define SRSS_V2_PWR_SSV_CTL_BODVDDD_ENABLE_Pos 3UL 612 #define SRSS_V2_PWR_SSV_CTL_BODVDDD_ENABLE_Msk 0x8UL 613 #define SRSS_V2_PWR_SSV_CTL_BODVDDA_VSEL_Pos 4UL 614 #define SRSS_V2_PWR_SSV_CTL_BODVDDA_VSEL_Msk 0x10UL 615 #define SRSS_V2_PWR_SSV_CTL_BODVDDA_ACTION_Pos 6UL 616 #define SRSS_V2_PWR_SSV_CTL_BODVDDA_ACTION_Msk 0xC0UL 617 #define SRSS_V2_PWR_SSV_CTL_BODVDDA_ENABLE_Pos 8UL 618 #define SRSS_V2_PWR_SSV_CTL_BODVDDA_ENABLE_Msk 0x100UL 619 #define SRSS_V2_PWR_SSV_CTL_BODVCCD_ENABLE_Pos 11UL 620 #define SRSS_V2_PWR_SSV_CTL_BODVCCD_ENABLE_Msk 0x800UL 621 #define SRSS_V2_PWR_SSV_CTL_OVDVDDD_VSEL_Pos 16UL 622 #define SRSS_V2_PWR_SSV_CTL_OVDVDDD_VSEL_Msk 0x10000UL 623 #define SRSS_V2_PWR_SSV_CTL_OVDVDDD_ENABLE_Pos 19UL 624 #define SRSS_V2_PWR_SSV_CTL_OVDVDDD_ENABLE_Msk 0x80000UL 625 #define SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Pos 20UL 626 #define SRSS_V2_PWR_SSV_CTL_OVDVDDA_VSEL_Msk 0x100000UL 627 #define SRSS_V2_PWR_SSV_CTL_OVDVDDA_ACTION_Pos 22UL 628 #define SRSS_V2_PWR_SSV_CTL_OVDVDDA_ACTION_Msk 0xC00000UL 629 #define SRSS_V2_PWR_SSV_CTL_OVDVDDA_ENABLE_Pos 24UL 630 #define SRSS_V2_PWR_SSV_CTL_OVDVDDA_ENABLE_Msk 0x1000000UL 631 #define SRSS_V2_PWR_SSV_CTL_OVDVCCD_ENABLE_Pos 27UL 632 #define SRSS_V2_PWR_SSV_CTL_OVDVCCD_ENABLE_Msk 0x8000000UL 633 /* SRSS.PWR_SSV_STATUS */ 634 #define SRSS_V2_PWR_SSV_STATUS_BODVDDD_OK_Pos 0UL 635 #define SRSS_V2_PWR_SSV_STATUS_BODVDDD_OK_Msk 0x1UL 636 #define SRSS_V2_PWR_SSV_STATUS_BODVDDA_OK_Pos 1UL 637 #define SRSS_V2_PWR_SSV_STATUS_BODVDDA_OK_Msk 0x2UL 638 #define SRSS_V2_PWR_SSV_STATUS_BODVCCD_OK_Pos 2UL 639 #define SRSS_V2_PWR_SSV_STATUS_BODVCCD_OK_Msk 0x4UL 640 #define SRSS_V2_PWR_SSV_STATUS_OVDVDDD_OK_Pos 8UL 641 #define SRSS_V2_PWR_SSV_STATUS_OVDVDDD_OK_Msk 0x100UL 642 #define SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Pos 9UL 643 #define SRSS_V2_PWR_SSV_STATUS_OVDVDDA_OK_Msk 0x200UL 644 #define SRSS_V2_PWR_SSV_STATUS_OVDVCCD_OK_Pos 10UL 645 #define SRSS_V2_PWR_SSV_STATUS_OVDVCCD_OK_Msk 0x400UL 646 #define SRSS_V2_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Pos 16UL 647 #define SRSS_V2_PWR_SSV_STATUS_OCD_ACT_LINREG_OK_Msk 0x10000UL 648 #define SRSS_V2_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Pos 17UL 649 #define SRSS_V2_PWR_SSV_STATUS_OCD_DPSLP_REG_OK_Msk 0x20000UL 650 /* SRSS.PWR_LVD_CTL */ 651 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL 652 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL 653 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL 654 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL 655 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL 656 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL 657 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Pos 8UL 658 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_TRIPSEL_HT_Msk 0x1F00UL 659 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Pos 14UL 660 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_DPSLP_EN_HT_Msk 0x4000UL 661 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Pos 15UL 662 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_EN_HT_Msk 0x8000UL 663 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Pos 16UL 664 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_EDGE_SEL_Msk 0x30000UL 665 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_ACTION_Pos 18UL 666 #define SRSS_V2_PWR_LVD_CTL_HVLVD1_ACTION_Msk 0x40000UL 667 /* SRSS.PWR_LVD_CTL2 */ 668 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Pos 8UL 669 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_TRIPSEL_HT_Msk 0x1F00UL 670 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Pos 14UL 671 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_DPSLP_EN_HT_Msk 0x4000UL 672 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_EN_HT_Pos 15UL 673 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_EN_HT_Msk 0x8000UL 674 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Pos 16UL 675 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_EDGE_SEL_Msk 0x30000UL 676 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_ACTION_Pos 18UL 677 #define SRSS_V2_PWR_LVD_CTL2_HVLVD2_ACTION_Msk 0x40000UL 678 /* SRSS.PWR_HIB_DATA */ 679 #define SRSS_V2_PWR_HIB_DATA_HIB_DATA_Pos 0UL 680 #define SRSS_V2_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL 681 /* SRSS.CLK_PATH_SELECT */ 682 #define SRSS_V2_CLK_PATH_SELECT_PATH_MUX_Pos 0UL 683 #define SRSS_V2_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL 684 /* SRSS.CLK_ROOT_SELECT */ 685 #define SRSS_V2_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL 686 #define SRSS_V2_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL 687 #define SRSS_V2_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL 688 #define SRSS_V2_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL 689 #define SRSS_V2_CLK_ROOT_SELECT_ENABLE_Pos 31UL 690 #define SRSS_V2_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL 691 /* SRSS.CLK_SELECT */ 692 #define SRSS_V2_CLK_SELECT_LFCLK_SEL_Pos 0UL 693 #define SRSS_V2_CLK_SELECT_LFCLK_SEL_Msk 0x7UL 694 #define SRSS_V2_CLK_SELECT_PUMP_SEL_Pos 8UL 695 #define SRSS_V2_CLK_SELECT_PUMP_SEL_Msk 0xF00UL 696 #define SRSS_V2_CLK_SELECT_PUMP_DIV_Pos 12UL 697 #define SRSS_V2_CLK_SELECT_PUMP_DIV_Msk 0x7000UL 698 #define SRSS_V2_CLK_SELECT_PUMP_ENABLE_Pos 15UL 699 #define SRSS_V2_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL 700 /* SRSS.CLK_TIMER_CTL */ 701 #define SRSS_V2_CLK_TIMER_CTL_TIMER_SEL_Pos 0UL 702 #define SRSS_V2_CLK_TIMER_CTL_TIMER_SEL_Msk 0x1UL 703 #define SRSS_V2_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 8UL 704 #define SRSS_V2_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 0x300UL 705 #define SRSS_V2_CLK_TIMER_CTL_TIMER_DIV_Pos 16UL 706 #define SRSS_V2_CLK_TIMER_CTL_TIMER_DIV_Msk 0xFF0000UL 707 #define SRSS_V2_CLK_TIMER_CTL_ENABLE_Pos 31UL 708 #define SRSS_V2_CLK_TIMER_CTL_ENABLE_Msk 0x80000000UL 709 /* SRSS.CLK_ILO0_CONFIG */ 710 #define SRSS_V2_CLK_ILO0_CONFIG_ILO0_BACKUP_Pos 0UL 711 #define SRSS_V2_CLK_ILO0_CONFIG_ILO0_BACKUP_Msk 0x1UL 712 #define SRSS_V2_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Pos 30UL 713 #define SRSS_V2_CLK_ILO0_CONFIG_ILO0_MON_ENABLE_Msk 0x40000000UL 714 #define SRSS_V2_CLK_ILO0_CONFIG_ENABLE_Pos 31UL 715 #define SRSS_V2_CLK_ILO0_CONFIG_ENABLE_Msk 0x80000000UL 716 /* SRSS.CLK_ILO1_CONFIG */ 717 #define SRSS_V2_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Pos 30UL 718 #define SRSS_V2_CLK_ILO1_CONFIG_ILO1_MON_ENABLE_Msk 0x40000000UL 719 #define SRSS_V2_CLK_ILO1_CONFIG_ENABLE_Pos 31UL 720 #define SRSS_V2_CLK_ILO1_CONFIG_ENABLE_Msk 0x80000000UL 721 /* SRSS.CLK_IMO_CONFIG */ 722 #define SRSS_V2_CLK_IMO_CONFIG_ENABLE_Pos 31UL 723 #define SRSS_V2_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL 724 /* SRSS.CLK_ECO_CONFIG */ 725 #define SRSS_V2_CLK_ECO_CONFIG_AGC_EN_Pos 1UL 726 #define SRSS_V2_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL 727 #define SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Pos 27UL 728 #define SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_DISABLE_Msk 0x8000000UL 729 #define SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Pos 28UL 730 #define SRSS_V2_CLK_ECO_CONFIG_ECO_DIV_ENABLE_Msk 0x10000000UL 731 #define SRSS_V2_CLK_ECO_CONFIG_ECO_EN_Pos 31UL 732 #define SRSS_V2_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL 733 /* SRSS.CLK_ECO_PRESCALE */ 734 #define SRSS_V2_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Pos 0UL 735 #define SRSS_V2_CLK_ECO_PRESCALE_ECO_DIV_ENABLED_Msk 0x1UL 736 #define SRSS_V2_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Pos 8UL 737 #define SRSS_V2_CLK_ECO_PRESCALE_ECO_FRAC_DIV_Msk 0xFF00UL 738 #define SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Pos 16UL 739 #define SRSS_V2_CLK_ECO_PRESCALE_ECO_INT_DIV_Msk 0x3FF0000UL 740 /* SRSS.CLK_ECO_STATUS */ 741 #define SRSS_V2_CLK_ECO_STATUS_ECO_OK_Pos 0UL 742 #define SRSS_V2_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL 743 #define SRSS_V2_CLK_ECO_STATUS_ECO_READY_Pos 1UL 744 #define SRSS_V2_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL 745 /* SRSS.CLK_PILO_CONFIG */ 746 #define SRSS_V2_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL 747 #define SRSS_V2_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL 748 #define SRSS_V2_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL 749 #define SRSS_V2_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL 750 #define SRSS_V2_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL 751 #define SRSS_V2_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL 752 #define SRSS_V2_CLK_PILO_CONFIG_PILO_EN_Pos 31UL 753 #define SRSS_V2_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL 754 /* SRSS.CLK_FLL_CONFIG */ 755 #define SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL 756 #define SRSS_V2_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL 757 #define SRSS_V2_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL 758 #define SRSS_V2_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL 759 #define SRSS_V2_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL 760 #define SRSS_V2_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL 761 /* SRSS.CLK_FLL_CONFIG2 */ 762 #define SRSS_V2_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL 763 #define SRSS_V2_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL 764 #define SRSS_V2_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL 765 #define SRSS_V2_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0xFF0000UL 766 #define SRSS_V2_CLK_FLL_CONFIG2_UPDATE_TOL_Pos 24UL 767 #define SRSS_V2_CLK_FLL_CONFIG2_UPDATE_TOL_Msk 0xFF000000UL 768 /* SRSS.CLK_FLL_CONFIG3 */ 769 #define SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL 770 #define SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL 771 #define SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL 772 #define SRSS_V2_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL 773 #define SRSS_V2_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL 774 #define SRSS_V2_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL 775 #define SRSS_V2_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL 776 #define SRSS_V2_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL 777 /* SRSS.CLK_FLL_CONFIG4 */ 778 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL 779 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL 780 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL 781 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL 782 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL 783 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL 784 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL 785 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL 786 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL 787 #define SRSS_V2_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL 788 /* SRSS.CLK_FLL_STATUS */ 789 #define SRSS_V2_CLK_FLL_STATUS_LOCKED_Pos 0UL 790 #define SRSS_V2_CLK_FLL_STATUS_LOCKED_Msk 0x1UL 791 #define SRSS_V2_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 792 #define SRSS_V2_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 793 #define SRSS_V2_CLK_FLL_STATUS_CCO_READY_Pos 2UL 794 #define SRSS_V2_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL 795 /* SRSS.CLK_ECO_CONFIG2 */ 796 #define SRSS_V2_CLK_ECO_CONFIG2_WDTRIM_Pos 0UL 797 #define SRSS_V2_CLK_ECO_CONFIG2_WDTRIM_Msk 0x7UL 798 #define SRSS_V2_CLK_ECO_CONFIG2_ATRIM_Pos 4UL 799 #define SRSS_V2_CLK_ECO_CONFIG2_ATRIM_Msk 0xF0UL 800 #define SRSS_V2_CLK_ECO_CONFIG2_FTRIM_Pos 8UL 801 #define SRSS_V2_CLK_ECO_CONFIG2_FTRIM_Msk 0x300UL 802 #define SRSS_V2_CLK_ECO_CONFIG2_RTRIM_Pos 10UL 803 #define SRSS_V2_CLK_ECO_CONFIG2_RTRIM_Msk 0xC00UL 804 #define SRSS_V2_CLK_ECO_CONFIG2_GTRIM_Pos 12UL 805 #define SRSS_V2_CLK_ECO_CONFIG2_GTRIM_Msk 0x7000UL 806 /* SRSS.CLK_PLL_CONFIG */ 807 #define SRSS_V2_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL 808 #define SRSS_V2_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL 809 #define SRSS_V2_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL 810 #define SRSS_V2_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL 811 #define SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL 812 #define SRSS_V2_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL 813 #define SRSS_V2_CLK_PLL_CONFIG_LOCK_DELAY_Pos 25UL 814 #define SRSS_V2_CLK_PLL_CONFIG_LOCK_DELAY_Msk 0x6000000UL 815 #define SRSS_V2_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL 816 #define SRSS_V2_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL 817 #define SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL 818 #define SRSS_V2_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL 819 #define SRSS_V2_CLK_PLL_CONFIG_ENABLE_Pos 31UL 820 #define SRSS_V2_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL 821 /* SRSS.CLK_PLL_STATUS */ 822 #define SRSS_V2_CLK_PLL_STATUS_LOCKED_Pos 0UL 823 #define SRSS_V2_CLK_PLL_STATUS_LOCKED_Msk 0x1UL 824 #define SRSS_V2_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL 825 #define SRSS_V2_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL 826 /* SRSS.CSV_REF_SEL */ 827 #define SRSS_V2_CSV_REF_SEL_REF_MUX_Pos 0UL 828 #define SRSS_V2_CSV_REF_SEL_REF_MUX_Msk 0x7UL 829 /* SRSS.RES_CAUSE */ 830 #define SRSS_V2_RES_CAUSE_RESET_WDT_Pos 0UL 831 #define SRSS_V2_RES_CAUSE_RESET_WDT_Msk 0x1UL 832 #define SRSS_V2_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL 833 #define SRSS_V2_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL 834 #define SRSS_V2_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL 835 #define SRSS_V2_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL 836 #define SRSS_V2_RES_CAUSE_RESET_TC_DBGRESET_Pos 3UL 837 #define SRSS_V2_RES_CAUSE_RESET_TC_DBGRESET_Msk 0x8UL 838 #define SRSS_V2_RES_CAUSE_RESET_SOFT_Pos 4UL 839 #define SRSS_V2_RES_CAUSE_RESET_SOFT_Msk 0x10UL 840 #define SRSS_V2_RES_CAUSE_RESET_MCWDT0_Pos 5UL 841 #define SRSS_V2_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL 842 #define SRSS_V2_RES_CAUSE_RESET_MCWDT1_Pos 6UL 843 #define SRSS_V2_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL 844 #define SRSS_V2_RES_CAUSE_RESET_MCWDT2_Pos 7UL 845 #define SRSS_V2_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL 846 #define SRSS_V2_RES_CAUSE_RESET_MCWDT3_Pos 8UL 847 #define SRSS_V2_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL 848 #define SRSS_V2_RES_CAUSE_RESET_XRES_Pos 16UL 849 #define SRSS_V2_RES_CAUSE_RESET_XRES_Msk 0x10000UL 850 #define SRSS_V2_RES_CAUSE_RESET_BODVDDD_Pos 17UL 851 #define SRSS_V2_RES_CAUSE_RESET_BODVDDD_Msk 0x20000UL 852 #define SRSS_V2_RES_CAUSE_RESET_BODVDDA_Pos 18UL 853 #define SRSS_V2_RES_CAUSE_RESET_BODVDDA_Msk 0x40000UL 854 #define SRSS_V2_RES_CAUSE_RESET_BODVCCD_Pos 19UL 855 #define SRSS_V2_RES_CAUSE_RESET_BODVCCD_Msk 0x80000UL 856 #define SRSS_V2_RES_CAUSE_RESET_OVDVDDD_Pos 20UL 857 #define SRSS_V2_RES_CAUSE_RESET_OVDVDDD_Msk 0x100000UL 858 #define SRSS_V2_RES_CAUSE_RESET_OVDVDDA_Pos 21UL 859 #define SRSS_V2_RES_CAUSE_RESET_OVDVDDA_Msk 0x200000UL 860 #define SRSS_V2_RES_CAUSE_RESET_OVDVCCD_Pos 22UL 861 #define SRSS_V2_RES_CAUSE_RESET_OVDVCCD_Msk 0x400000UL 862 #define SRSS_V2_RES_CAUSE_RESET_OCD_ACT_LINREG_Pos 23UL 863 #define SRSS_V2_RES_CAUSE_RESET_OCD_ACT_LINREG_Msk 0x800000UL 864 #define SRSS_V2_RES_CAUSE_RESET_OCD_DPSLP_LINREG_Pos 24UL 865 #define SRSS_V2_RES_CAUSE_RESET_OCD_DPSLP_LINREG_Msk 0x1000000UL 866 #define SRSS_V2_RES_CAUSE_RESET_PXRES_Pos 28UL 867 #define SRSS_V2_RES_CAUSE_RESET_PXRES_Msk 0x10000000UL 868 #define SRSS_V2_RES_CAUSE_RESET_STRUCT_XRES_Pos 29UL 869 #define SRSS_V2_RES_CAUSE_RESET_STRUCT_XRES_Msk 0x20000000UL 870 #define SRSS_V2_RES_CAUSE_RESET_PORVDDD_Pos 30UL 871 #define SRSS_V2_RES_CAUSE_RESET_PORVDDD_Msk 0x40000000UL 872 /* SRSS.RES_CAUSE2 */ 873 #define SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Pos 0UL 874 #define SRSS_V2_RES_CAUSE2_RESET_CSV_HF_Msk 0xFFFFUL 875 #define SRSS_V2_RES_CAUSE2_RESET_CSV_REF_Pos 16UL 876 #define SRSS_V2_RES_CAUSE2_RESET_CSV_REF_Msk 0x10000UL 877 /* SRSS.CLK_TRIM_ILO0_CTL */ 878 #define SRSS_V2_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Pos 0UL 879 #define SRSS_V2_CLK_TRIM_ILO0_CTL_ILO0_FTRIM_Msk 0x3FUL 880 #define SRSS_V2_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Pos 8UL 881 #define SRSS_V2_CLK_TRIM_ILO0_CTL_ILO0_MONTRIM_Msk 0xF00UL 882 /* SRSS.PWR_TRIM_PWRSYS_CTL */ 883 #define SRSS_V2_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL 884 #define SRSS_V2_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL 885 #define SRSS_V2_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL 886 #define SRSS_V2_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL 887 /* SRSS.CLK_TRIM_PILO_CTL */ 888 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL 889 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL 890 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL 891 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL 892 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL 893 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL 894 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL 895 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL 896 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL 897 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL 898 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL 899 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL 900 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL 901 #define SRSS_V2_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL 902 /* SRSS.CLK_TRIM_PILO_CTL2 */ 903 #define SRSS_V2_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL 904 #define SRSS_V2_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL 905 #define SRSS_V2_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL 906 #define SRSS_V2_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL 907 #define SRSS_V2_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL 908 #define SRSS_V2_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL 909 /* SRSS.CLK_TRIM_PILO_CTL3 */ 910 #define SRSS_V2_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL 911 #define SRSS_V2_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL 912 /* SRSS.CLK_TRIM_ILO1_CTL */ 913 #define SRSS_V2_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Pos 0UL 914 #define SRSS_V2_CLK_TRIM_ILO1_CTL_ILO1_FTRIM_Msk 0x3FUL 915 #define SRSS_V2_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Pos 8UL 916 #define SRSS_V2_CLK_TRIM_ILO1_CTL_ILO1_MONTRIM_Msk 0xF00UL 917 918 919 #endif /* _CYIP_SRSS_V2_H_ */ 920 921 922 /* [] END OF FILE */ 923
