1 /* 2 * $ Copyright Cypress Semiconductor Apache2 $ 3 */ 4 5 #ifndef INCLUDED_WHD_M2M_H_ 6 #define INCLUDED_WHD_M2M_H_ 7 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 /****************************************************** 13 * M2M Constants 14 ******************************************************/ 15 //GCI Registers 16 #define GCI_INT_MASK_REG 0x4fe40018 /* When the31st bit of this Reg is set, Doorbell Interrupts to the IP(BT/WLAN) are enabled */ 17 #define GCI_INT_STATUS_REG 0x4fe40014 /* Read Only Reg - 31st bit indicates a DB Interrupt to the BT is pending.If it is set, Indicates a WL2BT Doorbell Interrupt is pending */ 18 #define GCI_DB_INT_STATUS_REG 0x4fe4063c /* To check which DB interrupt is triggerd by WLAN */ 19 #define GCI_DB_INT_MASK_REG 0x4fe40640 /* This register is writable by BT only and readable by both WLAN and BT. This register resets with BT reset */ 20 21 #define GCI_DB_INT_STS_BIT (1 << 31) /* 31st bit of GCI_INT_MASK_REG */ 22 23 /* DB Bits for Doorbell Interrupt Mask Register(GCI_DB_INT_MASK_REG) */ 24 #define GCI_H2D_SET_BIT_DB0 0x0001 25 #define GCI_H2D_SET_BIT_DB1 0x0002 26 #define GCI_H2D_SET_BIT_DB2 0x0004 27 #define GCI_H2D_SET_BIT_DB3 0x0008 28 #define GCI_H2D_SET_BIT_DB4 0x0010 29 #define GCI_H2D_SET_BIT_DB5 0x0020 30 #define GCI_H2D_SET_BIT_DB6 0x0040 31 #define GCI_H2D_SET_BIT_DB7 0x0080 32 #define GCI_H2D_SET_ALL_DB (GCI_H2D_SET_BIT_DB0 | GCI_H2D_SET_BIT_DB1 | GCI_H2D_SET_BIT_DB2 | \ 33 GCI_H2D_SET_BIT_DB3 | \ 34 GCI_H2D_SET_BIT_DB4 | GCI_H2D_SET_BIT_DB5 | GCI_H2D_SET_BIT_DB6 | \ 35 GCI_H2D_SET_BIT_DB7) 36 37 /* These registers are writable by BT only and readable by both WLAN and BT. These registers reset with BT reset */ 38 #define GCI_BT2WL_DB0_REG 0x4fe4066c 39 #define GCI_BT2WL_DB1_REG 0x4fe40670 40 #define GCI_BT2WL_DB2_REG 0x4fe40674 41 #define GCI_BT2WL_DB3_REG 0x4fe40678 42 #define GCI_BT2WL_DB4_REG 0x4fe4067c 43 #define GCI_BT2WL_DB5_REG 0x4fe40680 44 #define GCI_BT2WL_DB6_REG 0x4fe40684 45 #define GCI_BT2WL_DB7_REG 0x4fe40688 46 47 /* These registers are writable by WLAN only and readable by both WLAN and BT. These registers reset with WLAN reset */ 48 #define GCI_WL2BT_DB0_REG 0x4fe40644 49 #define GCI_WL2BT_DB1_REG 0x4fe40648 50 #define GCI_WL2BT_DB2_REG 0x4fe4064c 51 #define GCI_WL2BT_DB3_REG 0x4fe40650 52 #define GCI_WL2BT_DB4_REG 0x4fe40654 53 #define GCI_WL2BT_DB5_REG 0x4fe40658 54 #define GCI_WL2BT_DB6_REG 0x4fe4065c 55 #define GCI_WL2BT_DB7_REG 0x4fe40660 56 57 /* These register readable by both WLAN and BT. These registers reset with WLAN reset. http://twiki.cypress.com/do/view/Mwgroup/CurrentGciProgGuide#BT2WL%20Clock%20Request%20and%20Sta */ 58 #define GCI_WL2BT_CLOCK_CSR 0x4fe406A0 59 60 /* These register readable by both WLAN and BT. These registers reset with BT reset. */ 61 #define GCI_BT2WL_CLOCK_CSR 0x4fe406A4 62 63 /* The final control value is OR of individual values from each IP's register */ 64 #define GCI_CTSS_CLOCK_CSR 0x4fe40700 65 66 /* GCI_CHIP_CLOCK_CSR Bits */ 67 #define GCI_FORCE_ALP ( (uint32_t)0x01 ) /* Force ALP request to backplane */ 68 #define GCI_FORCE_HT ( (uint32_t)0x02 ) /* Force HT request to backplane */ 69 #define GCI_FORCE_ILP ( (uint32_t)0x04 ) /* Force ILP request to backplane */ 70 #define GCI_ALP_AVAIL_REQ ( (uint32_t)0x08 ) /* Make ALP ready (power up xtal) */ 71 #define GCI_HT_AVAIL_REQ ( (uint32_t)0x10 ) /* Make HT ready (power up PLL) */ 72 #define GCI_FORCE_HW_CLKREQ_OFF ( (uint32_t)0x20 ) /* Squelch clock requests from HW */ 73 #define GCI_ALP_AVAIL ( (uint32_t)0x10000 ) /* Status: ALP is ready */ 74 #define GCI_HT_AVAIL ( (uint32_t)0x20000 ) /* Status: HT is ready */ 75 #define GCI_BT_ON_ALP ( (uint32_t)0x40000 ) 76 #define GCI_BT_ON_HT ( (uint32_t)0x80000 ) 77 78 /* Hatchet1-CP(through GCI) Security Handshake Register */ 79 #define M2M_REG_DAR_H2D_MSG_0 0x4fe40634 80 #define M2M_REG_DAR_D2H_MSG_0 0x4fe4062c 81 #define M2M_REG_DAR_SC0_MSG_0 0x4fe40628 82 83 /* Bootloader handshake flags - dongle to host */ 84 #define M2M_BLHS_D2H_START (1 << 0) 85 #define M2M_BLHS_D2H_READY (1 << 1) 86 #define M2M_BLHS_D2H_STEADY (1 << 2) 87 #define M2M_BLHS_D2H_TRXHDR_PARSE_DONE (1 << 3) 88 #define M2M_BLHS_D2H_VALDN_START (1 << 4) 89 #define M2M_BLHS_D2H_VALDN_RESULT (1 << 5) 90 #define M2M_BLHS_D2H_VALDN_DONE (1 << 6) 91 92 /* Bootloader handshake flags - host to dongle */ 93 #define M2M_BLHS_H2D_BL_INIT 0 94 #define M2M_BLHS_H2D_DL_FW_START (1 << 0) 95 #define M2M_BLHS_H2D_DL_FW_DONE (1 << 1) 96 #define M2M_BLHS_H2D_DL_NVRAM_DONE (1 << 2) 97 #define M2M_BLHS_H2D_BL_RESET_ON_ERROR (1 << 3) 98 99 #ifdef __cplusplus 100 } /* extern "C" */ 101 #endif 102 103 #endif /* ifndef INCLUDED_WHD_M2M_H_ */ 104 105
