1 /***************************************************************************//**
2 * \file cy_device.h
3 * \version 2.0
4 *
5 * This file specifies the structure for core and peripheral block HW base
6 * addresses, versions, and parameters.
7 *
8 ********************************************************************************/
9 #ifndef CY_DEVICE_H_
10 #define CY_DEVICE_H_
11
12 #include <stdint.h>
13 #include <stddef.h>
14
15 #include "cy_utils.h"
16
17 #ifndef BOY2_UUT
18 #include "cy_device_headers.h"
19 #endif
20
21 #include "startup_cat1b.h"
22
23
24 CY_MISRA_FP_BLOCK_START('MISRA C-2012 Rule 8.6', 1, \
25 'Checked manually. The definition is a part of linker script.')
26
27 #ifdef _GPIO_CYW20829_56_QFN_H_
28 #define _GPIO_CYW20829B0_56_QFN_H_
29 #endif
30
31 #ifdef _GPIO_CYW20829_40_QFN_H_
32 #define _GPIO_CYW20829B0_40_QFN_H_
33 #endif
34
35 /* Device descriptor type */
36 typedef struct
37 {
38 /* Base HW addresses */
39 uint32_t hsiomBase;
40 uint32_t gpioBase;
41
42 /* IP block versions: [7:4] major, [3:0] minor */
43 uint8_t dwVersion;
44
45 /* Parameters */
46 uint8_t cpussDw0ChNr;
47 uint8_t cpussDw1ChNr;
48 uint8_t epMonitorNr;
49
50 /* Peripheral register offsets */
51
52 /* DW registers */
53 uint16_t dwChOffset;
54 uint16_t dwChSize;
55 uint8_t dwChCtlPrioPos;
56 uint8_t dwChCtlPreemptablePos;
57 uint8_t dwStatusChIdxPos;
58 uint32_t dwStatusChIdxMsk;
59
60 uint8_t tcpwmCC1Present;
61 uint8_t tcpwmAMCPresent;
62 uint8_t tcpwmSMCPrecent;
63
64 } cy_stc_device_t;
65
66 /* Pointer to device configuration structure */
67 #define CY_DEVICE_CFG (&cy_deviceIpBlockCfg)
68
69
70 /*******************************************************************************
71 * Global Variables
72 *******************************************************************************/
73
74 extern const cy_stc_device_t cy_deviceIpBlockCfg;
75 extern const cy_stc_device_t* cy_device;
76
77 /*******************************************************************************
78 * Global Extern Functions
79 *******************************************************************************/
80
81 /*******************************************************************************
82 * Macro Definitions
83 *******************************************************************************/
84 #if (__SAUREGION_PRESENT==1)
85 #define SECURE_ALIAS_OFFSET (0x10000000UL)
86 #ifdef CY_PDL_TZ_ENABLED
87 #define GET_ALIAS_ADDRESS(addr) (uint32_t)(((uint32_t)(addr)) | SECURE_ALIAS_OFFSET)
88 #else
89 #define GET_ALIAS_ADDRESS(addr) (uint32_t)(((uint32_t)(addr)) & ~SECURE_ALIAS_OFFSET)
90 #endif
91 #else
92 #define GET_ALIAS_ADDRESS(addr) (uint32_t)(addr)
93 #endif /* (__SAUREGION_PRESENT==1) */
94
95
96 #if defined(CY_DEVICE_BOY2)
97 #ifndef NORMAL_PROVISIONED_LCS
98 #define CM33_NS_PC_VALUE (1u)
99 #define CM33_S_PC_VALUE (0u)
100 #else
101 #define CM33_NS_PC_VALUE (3u)
102 #define CM33_S_PC_VALUE (2u)
103 #endif
104 #endif
105
106 /*******************************************************************************
107 * Function Prototypes
108 *******************************************************************************/
109
110 void Cy_PDL_Init(const cy_stc_device_t * device);
111
112 /*******************************************************************************
113 * Register Access Helper Macros
114 *******************************************************************************/
115 #define CY_DEVICE_CAT1B /* Device Category */
116 /*******************************************************************************
117 * SDHC
118 *******************************************************************************/
119 #define SDHC_WRAP_CTL(base) (((SDHC_Type *)(base))->WRAP.CTL)
120 #define SDHC_CORE_SDMASA_R(base) (((SDHC_Type *)(base))->CORE.SDMASA_R)
121 #define SDHC_CORE_BLOCKSIZE_R(base) (((SDHC_Type *)(base))->CORE.BLOCKSIZE_R)
122 #define SDHC_CORE_BLOCKCOUNT_R(base) (((SDHC_Type *)(base))->CORE.BLOCKCOUNT_R)
123 #define SDHC_CORE_ARGUMENT_R(base) (((SDHC_Type *)(base))->CORE.ARGUMENT_R)
124 #define SDHC_CORE_XFER_MODE_R(base) (((SDHC_Type *)(base))->CORE.XFER_MODE_R)
125 #define SDHC_CORE_CMD_R(base) (((SDHC_Type *)(base))->CORE.CMD_R)
126 #define SDHC_CORE_RESP01_R(base) (((SDHC_Type *)(base))->CORE.RESP01_R)
127 #define SDHC_CORE_RESP23_R(base) (((SDHC_Type *)(base))->CORE.RESP23_R)
128 #define SDHC_CORE_RESP45_R(base) (((SDHC_Type *)(base))->CORE.RESP45_R)
129 #define SDHC_CORE_RESP67_R(base) (((SDHC_Type *)(base))->CORE.RESP67_R)
130 #define SDHC_CORE_BUF_DATA_R(base) (((SDHC_Type *)(base))->CORE.BUF_DATA_R)
131 #define SDHC_CORE_PSTATE_REG(base) (((SDHC_Type *)(base))->CORE.PSTATE_REG)
132 #define SDHC_CORE_HOST_CTRL1_R(base) (((SDHC_Type *)(base))->CORE.HOST_CTRL1_R)
133 #define SDHC_CORE_PWR_CTRL_R(base) (((SDHC_Type *)(base))->CORE.PWR_CTRL_R)
134 #define SDHC_CORE_BGAP_CTRL_R(base) (((SDHC_Type *)(base))->CORE.BGAP_CTRL_R)
135 #define SDHC_CORE_WUP_CTRL_R(base) (((SDHC_Type *)(base))->CORE.WUP_CTRL_R)
136 #define SDHC_CORE_CLK_CTRL_R(base) (((SDHC_Type *)(base))->CORE.CLK_CTRL_R)
137 #define SDHC_CORE_TOUT_CTRL_R(base) (((SDHC_Type *)(base))->CORE.TOUT_CTRL_R)
138 #define SDHC_CORE_SW_RST_R(base) (((SDHC_Type *)(base))->CORE.SW_RST_R)
139 #define SDHC_CORE_NORMAL_INT_STAT_R(base) (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_R)
140 #define SDHC_CORE_ERROR_INT_STAT_R(base) (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_R)
141 #define SDHC_CORE_NORMAL_INT_STAT_EN_R(base) (((SDHC_Type *)(base))->CORE.NORMAL_INT_STAT_EN_R)
142 #define SDHC_CORE_ERROR_INT_STAT_EN_R(base) (((SDHC_Type *)(base))->CORE.ERROR_INT_STAT_EN_R)
143 #define SDHC_CORE_NORMAL_INT_SIGNAL_EN_R(base) (((SDHC_Type *)(base))->CORE.NORMAL_INT_SIGNAL_EN_R)
144 #define SDHC_CORE_ERROR_INT_SIGNAL_EN_R(base) (((SDHC_Type *)(base))->CORE.ERROR_INT_SIGNAL_EN_R)
145 #define SDHC_CORE_AUTO_CMD_STAT_R(base) (((SDHC_Type *)(base))->CORE.AUTO_CMD_STAT_R)
146 #define SDHC_CORE_HOST_CTRL2_R(base) (((SDHC_Type *)(base))->CORE.HOST_CTRL2_R)
147 #define SDHC_CORE_CAPABILITIES1_R(base) (((SDHC_Type *)(base))->CORE.CAPABILITIES1_R)
148 #define SDHC_CORE_CAPABILITIES2_R(base) (((SDHC_Type *)(base))->CORE.CAPABILITIES2_R)
149 #define SDHC_CORE_CURR_CAPABILITIES1_R(base) (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES1_R)
150 #define SDHC_CORE_CURR_CAPABILITIES2_R(base) (((SDHC_Type *)(base))->CORE.CURR_CAPABILITIES2_R)
151 #define SDHC_CORE_ADMA_ERR_STAT_R(base) (((SDHC_Type *)(base))->CORE.ADMA_ERR_STAT_R)
152 #define SDHC_CORE_ADMA_SA_LOW_R(base) (((SDHC_Type *)(base))->CORE.ADMA_SA_LOW_R)
153 #define SDHC_CORE_ADMA_ID_LOW_R(base) (((SDHC_Type *)(base))->CORE.ADMA_ID_LOW_R)
154 #define SDHC_CORE_EMMC_CTRL_R(base) (((SDHC_Type *)(base))->CORE.EMMC_CTRL_R)
155 #define SDHC_CORE_GP_OUT_R(base) (((SDHC_Type *)(base))->CORE.GP_OUT_R)
156
157 /*******************************************************************************
158 * SMARTIO
159 *******************************************************************************/
160
161 #define SMARTIO_PRT_CTL(base) (((SMARTIO_PRT_Type *)(base))->CTL)
162 #define SMARTIO_PRT_SYNC_CTL(base) (((SMARTIO_PRT_Type *)(base))->SYNC_CTL)
163 #define SMARTIO_PRT_LUT_SEL(base, idx) (((SMARTIO_PRT_Type *)(base))->LUT_SEL[idx])
164 #define SMARTIO_PRT_LUT_CTL(base, idx) (((SMARTIO_PRT_Type *)(base))->LUT_CTL[idx])
165 #define SMARTIO_PRT_DU_SEL(base) (((SMARTIO_PRT_Type *)(base))->DU_SEL)
166 #define SMARTIO_PRT_DU_CTL(base) (((SMARTIO_PRT_Type *)(base))->DU_CTL)
167 #define SMARTIO_PRT_DATA(base) (((SMARTIO_PRT_Type *)(base))->DATA)
168
169
170 /*******************************************************************************
171 * SMIF
172 *******************************************************************************/
173 #if ((defined(CY_IP_MXSMIF_VERSION)) && (CY_IP_MXSMIF_VERSION>=3))
174 /* For backward compatibility of API, use first crypto device as default device */
175 #define SMIF_CRYPTO_CMD(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_CMD)
176 #define SMIF_CRYPTO_ADDR(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_ADDR)
177 #define SMIF_CRYPTO_MASK(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_MASK)
178 #define SMIF_CRYPTO_SUBREGION(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_SUBREGION)
179 #define SMIF_CRYPTO_INPUT0(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT0)
180 #define SMIF_CRYPTO_INPUT1(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT1)
181 #define SMIF_CRYPTO_INPUT2(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT2)
182 #define SMIF_CRYPTO_INPUT3(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_INPUT3)
183 #define SMIF_CRYPTO_KEY0(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY0)
184 #define SMIF_CRYPTO_KEY1(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY1)
185 #define SMIF_CRYPTO_KEY2(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY2)
186 #define SMIF_CRYPTO_KEY3(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_KEY3)
187 #define SMIF_CRYPTO_OUTPUT0(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT0)
188 #define SMIF_CRYPTO_OUTPUT1(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT1)
189 #define SMIF_CRYPTO_OUTPUT2(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT2)
190 #define SMIF_CRYPTO_OUTPUT3(base) (((SMIF_Type*) base)->SMIF_CRYPTO_BLOCK[0].CRYPTO_OUTPUT3)
191 #else
192 #define SMIF_CRYPTO_CMD(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_CMD)
193 #define SMIF_CRYPTO_ADDR(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_ADDR)
194 #define SMIF_CRYPTO_MASK(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_MASK)
195 #define SMIF_CRYPTO_SUBREGION(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_SUBREGION)
196 #define SMIF_CRYPTO_INPUT0(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT0)
197 #define SMIF_CRYPTO_INPUT1(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT1)
198 #define SMIF_CRYPTO_INPUT2(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT2)
199 #define SMIF_CRYPTO_INPUT3(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_INPUT3)
200 #define SMIF_CRYPTO_KEY0(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY0)
201 #define SMIF_CRYPTO_KEY1(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY1)
202 #define SMIF_CRYPTO_KEY2(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY2)
203 #define SMIF_CRYPTO_KEY3(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_KEY3)
204 #define SMIF_CRYPTO_OUTPUT0(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT0)
205 #define SMIF_CRYPTO_OUTPUT1(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT1)
206 #define SMIF_CRYPTO_OUTPUT2(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT2)
207 #define SMIF_CRYPTO_OUTPUT3(base) (((SMIF_SMIF_CRYPTO_Type *)(base))->CRYPTO_OUTPUT3)
208 #endif
209
210 #define SMIF_CRYPTO_IDX(base, deviceIndex) (((SMIF_Type *)(base))->SMIF_CRYPTO_BLOCK[deviceIndex])
211
212 #define SMIF_CRYPTO_IDX_CMD(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_CMD)
213 #define SMIF_CRYPTO_IDX_ADDR(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_ADDR)
214 #define SMIF_CRYPTO_IDX_MASK(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_MASK)
215 #define SMIF_CRYPTO_IDX_SUBREGION(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_SUBREGION)
216 #define SMIF_CRYPTO_IDX_INPUT0(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT0)
217 #define SMIF_CRYPTO_IDX_INPUT1(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT1)
218 #define SMIF_CRYPTO_IDX_INPUT2(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT2)
219 #define SMIF_CRYPTO_IDX_INPUT3(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_INPUT3)
220 #define SMIF_CRYPTO_IDX_KEY0(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY0)
221 #define SMIF_CRYPTO_IDX_KEY1(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY1)
222 #define SMIF_CRYPTO_IDX_KEY2(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY2)
223 #define SMIF_CRYPTO_IDX_KEY3(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_KEY3)
224 #define SMIF_CRYPTO_IDX_OUTPUT0(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT0)
225 #define SMIF_CRYPTO_IDX_OUTPUT1(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT1)
226 #define SMIF_CRYPTO_IDX_OUTPUT2(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT2)
227 #define SMIF_CRYPTO_IDX_OUTPUT3(base, deviceIndex) (SMIF_CRYPTO_IDX(base, deviceIndex).CRYPTO_OUTPUT3)
228
229
230 #define SMIF_DEVICE_CTL(base) (((SMIF_DEVICE_Type *)(base))->CTL)
231 #define SMIF_DEVICE_ADDR(base) (((SMIF_DEVICE_Type *)(base))->ADDR)
232 #define SMIF_DEVICE_ADDR_CTL(base) (((SMIF_DEVICE_Type *)(base))->ADDR_CTL)
233 #define SMIF_DEVICE_MASK(base) (((SMIF_DEVICE_Type *)(base))->MASK)
234 #define SMIF_DEVICE_RD_CMD_CTL(base) (((SMIF_DEVICE_Type *)(base))->RD_CMD_CTL)
235 #define SMIF_DEVICE_RD_ADDR_CTL(base) (((SMIF_DEVICE_Type *)(base))->RD_ADDR_CTL)
236 #define SMIF_DEVICE_RD_MODE_CTL(base) (((SMIF_DEVICE_Type *)(base))->RD_MODE_CTL)
237 #define SMIF_DEVICE_RD_DUMMY_CTL(base) (((SMIF_DEVICE_Type *)(base))->RD_DUMMY_CTL)
238 #define SMIF_DEVICE_RD_DATA_CTL(base) (((SMIF_DEVICE_Type *)(base))->RD_DATA_CTL)
239 #define SMIF_DEVICE_RD_BOUND_CTL(base) (((SMIF_DEVICE_Type *)(base))->RD_BOUND_CTL)
240 #define SMIF_DEVICE_WR_CMD_CTL(base) (((SMIF_DEVICE_Type *)(base))->WR_CMD_CTL)
241 #define SMIF_DEVICE_WR_ADDR_CTL(base) (((SMIF_DEVICE_Type *)(base))->WR_ADDR_CTL)
242 #define SMIF_DEVICE_WR_MODE_CTL(base) (((SMIF_DEVICE_Type *)(base))->WR_MODE_CTL)
243 #define SMIF_DEVICE_WR_DUMMY_CTL(base) (((SMIF_DEVICE_Type *)(base))->WR_DUMMY_CTL)
244 #define SMIF_DEVICE_WR_DATA_CTL(base) (((SMIF_DEVICE_Type *)(base))->WR_DATA_CTL)
245
246 #define SMIF_DEVICE_IDX(base, deviceIndex) (((SMIF_Type *)(base))->DEVICE[deviceIndex])
247
248 #define SMIF_DEVICE_IDX_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).CTL)
249 #define SMIF_DEVICE_IDX_ADDR(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR)
250 #define SMIF_DEVICE_IDX_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).ADDR_CTL)
251 #define SMIF_DEVICE_IDX_MASK(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).MASK)
252 #define SMIF_DEVICE_IDX_RD_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_CMD_CTL)
253 #define SMIF_DEVICE_IDX_RD_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_ADDR_CTL)
254 #define SMIF_DEVICE_IDX_RD_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_MODE_CTL)
255 #define SMIF_DEVICE_IDX_RD_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DUMMY_CTL)
256 #define SMIF_DEVICE_IDX_RD_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).RD_DATA_CTL)
257 #define SMIF_DEVICE_IDX_WR_CMD_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_CMD_CTL)
258 #define SMIF_DEVICE_IDX_WR_ADDR_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_ADDR_CTL)
259 #define SMIF_DEVICE_IDX_WR_MODE_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_MODE_CTL)
260 #define SMIF_DEVICE_IDX_WR_DUMMY_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DUMMY_CTL)
261 #define SMIF_DEVICE_IDX_WR_DATA_CTL(base, deviceIndex) (SMIF_DEVICE_IDX(base, deviceIndex).WR_DATA_CTL)
262
263 #define SMIF_CTL(base) (((SMIF_Type *)(base))->CTL)
264 #define SMIF_STATUS(base) (((SMIF_Type *)(base))->STATUS)
265 #define SMIF_INT_CLOCK_DELAY_TAP_SEL0(base) (((SMIF_Type *)(base))->INT_CLOCK_DELAY_TAP_SEL0)
266 #define SMIF_INT_CLOCK_DELAY_TAP_SEL1(base) (((SMIF_Type *)(base))->INT_CLOCK_DELAY_TAP_SEL1)
267 #define SMIF_DL_CTL(base) (((SMIF_Type *)(base))->DL_CTL)
268 #define SMIF_DL_STATUS0(base) (((SMIF_Type *)(base))->DL_STATUS0)
269 #define SMIF_DL_STATUS1(base) (((SMIF_Type *)(base))->DL_STATUS1)
270 #define SMIF_TX_CMD_FIFO_STATUS(base) (((SMIF_Type *)(base))->TX_CMD_FIFO_STATUS)
271 #define SMIF_TX_CMD_MMIO_FIFO_STATUS(base) (((SMIF_Type *)(base))->TX_CMD_MMIO_FIFO_STATUS)
272 #define SMIF_TX_CMD_MMIO_FIFO_WR(base) (((SMIF_Type *)(base))->TX_CMD_MMIO_FIFO_WR)
273 #define SMIF_TX_DATA_MMIO_FIFO_CTL(base) (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_CTL)
274 #define SMIF_TX_DATA_FIFO_STATUS(base) (((SMIF_Type *)(base))->TX_DATA_FIFO_STATUS)
275 #define SMIF_TX_DATA_MMIO_FIFO_STATUS(base) (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_STATUS)
276 #define SMIF_TX_DATA_MMIO_FIFO_WR1(base) (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR1)
277 #define SMIF_TX_DATA_MMIO_FIFO_WR2(base) (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR2)
278 #define SMIF_TX_DATA_MMIO_FIFO_WR4(base) (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR4)
279 #define SMIF_TX_DATA_MMIO_FIFO_WR1ODD(base) (((SMIF_Type *)(base))->TX_DATA_MMIO_FIFO_WR1ODD)
280 #define SMIF_RX_DATA_MMIO_FIFO_CTL(base) (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_CTL)
281 #define SMIF_RX_DATA_MMIO_FIFO_STATUS(base) (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_STATUS)
282 #define SMIF_RX_DATA_FIFO_STATUS(base) (((SMIF_Type *)(base))->RX_DATA_FIFO_STATUS)
283 #define SMIF_RX_DATA_MMIO_FIFO_RD1(base) (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1)
284 #define SMIF_RX_DATA_MMIO_FIFO_RD2(base) (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD2)
285 #define SMIF_RX_DATA_MMIO_FIFO_RD4(base) (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD4)
286 #define SMIF_RX_DATA_MMIO_FIFO_RD1_SILENT(base) (((SMIF_Type *)(base))->RX_DATA_MMIO_FIFO_RD1_SILENT)
287 #define SMIF_SLOW_CA_CTL(base) (((SMIF_Type *)(base))->SLOW_CA_CTL)
288 #define SMIF_SLOW_CA_CMD(base) (((SMIF_Type *)(base))->SLOW_CA_CMD)
289 #define SMIF_FAST_CA_CTL(base) (((SMIF_Type *)(base))->FAST_CA_CTL)
290 #define SMIF_FAST_CA_CMD(base) (((SMIF_Type *)(base))->FAST_CA_CMD)
291 #define SMIF_CRC_CMD(base) (((SMIF_Type *)(base))->CRC_CMD)
292 #define SMIF_CRC_INPUT0(base) (((SMIF_Type *)(base))->CRC_INPUT0)
293 #define SMIF_CRC_INPUT1(base) (((SMIF_Type *)(base))->CRC_INPUT1)
294 #define SMIF_CRC_OUTPUT(base) (((SMIF_Type *)(base))->CRC_OUTPUT)
295 #define SMIF_INTR(base) (((SMIF_Type *)(base))->INTR)
296 #define SMIF_INTR_SET(base) (((SMIF_Type *)(base))->INTR_SET)
297 #define SMIF_INTR_MASK(base) (((SMIF_Type *)(base))->INTR_MASK)
298 #define SMIF_INTR_MASKED(base) (((SMIF_Type *)(base))->INTR_MASKED)
299
300 /*******************************************************************************
301 * DW
302 *******************************************************************************/
303
304
305 #define CY_DW (0UL)
306 #define CY_DW_CRC (1UL)
307 #define CY_DW0_BASE DW0
308 #define CY_DW1_BASE DW1
309 #define CY_DW0_CH_NR CPUSS_DW0_CH_NR
310 #define CY_DW1_CH_NR CPUSS_DW1_CH_NR
311
312 #define CY_DW_CH_CTL_PRIO_Pos ((uint32_t)(DW_CH_STRUCT_CH_CTL_PRIO_Pos))
313 #define CY_DW_CH_CTL_PRIO_Msk ((uint32_t)(0x3UL << CY_DW_CH_CTL_PRIO_Pos))
314 #define CY_DW_CH_CTL_PREEMPTABLE_Pos ((uint32_t)(DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos))
315 #define CY_DW_CH_CTL_PREEMPTABLE_Msk ((uint32_t)(0x1UL << CY_DW_CH_CTL_PREEMPTABLE_Pos))
316 #define CY_DW_STATUS_CH_IDX_Pos ((uint32_t)(DW_STATUS_CH_IDX_Pos))
317 #define CY_DW_STATUS_CH_IDX_Msk (DW_STATUS_CH_IDX_Msk)
318
319 #define DW_CTL(base) (((DW_Type*)(base))->CTL)
320 #define DW_STATUS(base) (((DW_Type const*)(base))->STATUS)
321 #define DW_DESCR_SRC(base) (((DW_Type*)(base))->ACT_DESCR_SRC)
322 #define DW_DESCR_DST(base) (((DW_Type*)(base))->ACT_DESCR_DST)
323
324 #define DW_CRC_CTL(base) (((DW_Type*)(base))->CRC_CTL)
325 #define DW_CRC_DATA_CTL(base) (((DW_Type*)(base))->CRC_DATA_CTL)
326 #define DW_CRC_REM_CTL(base) (((DW_Type*)(base))->CRC_REM_CTL)
327 #define DW_CRC_POL_CTL(base) (((DW_Type*)(base))->CRC_POL_CTL)
328 #define DW_CRC_LFSR_CTL(base) (((DW_Type*)(base))->CRC_LFSR_CTL)
329
330 #define DW_CH_OFFSET (uint32_t)(offsetof(DW_Type, CH_STRUCT))
331 #define DW_CH_SIZE (uint32_t)(sizeof(DW_CH_STRUCT_Type))
332
333 #define DW_CH(base, chan) ((DW_CH_STRUCT_Type*)((uint32_t)(base) + DW_CH_OFFSET + (chan * DW_CH_SIZE)))
334 #define DW_CH_CTL(base, chan) (DW_CH((base), (chan))->CH_CTL)
335 #define DW_CH_STATUS(base, chan) (DW_CH((base), (chan))->CH_STATUS)
336 #define DW_CH_IDX(base, chan) (DW_CH((base), (chan))->CH_IDX)
337 #define DW_CH_CURR_PTR(base, chan) (DW_CH((base), (chan))->CH_CURR_PTR)
338
339 #define DW_CH_INTR(base, chan) (DW_CH((base), (chan))->INTR)
340 #define DW_CH_INTR_SET(base, chan) (DW_CH((base), (chan))->INTR_SET)
341 #define DW_CH_INTR_MASK(base, chan) (DW_CH((base), (chan))->INTR_MASK)
342 #define DW_CH_INTR_MASKED(base, chan) (DW_CH((base), (chan))->INTR_MASKED)
343 #define DW_CH_TR_CMD(base, chan) (DW_CH((base), (chan))->TR_CMD)
344
345 #if defined (CY_IP_MXDW)
346 #define DW_V2_CRC_CTL_DATA_REVERSE_Msk DW_CRC_CTL_DATA_REVERSE_Msk
347 #define DW_V2_CRC_CTL_REM_REVERSE_Msk DW_CRC_CTL_REM_REVERSE_Msk
348 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Msk DW_CRC_DATA_CTL_DATA_XOR_Msk
349 #define DW_V2_CRC_REM_CTL_REM_XOR_Msk DW_CRC_REM_CTL_REM_XOR_Msk
350 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk DW_CRC_POL_CTL_POLYNOMIAL_Msk
351 #define DW_V2_CRC_LFSR_CTL_LFSR32_Msk DW_CRC_LFSR_CTL_LFSR32_Msk
352 #define DW_V2_CRC_CTL_DATA_REVERSE_Pos DW_CRC_CTL_DATA_REVERSE_Pos
353 #define DW_V2_CRC_CTL_REM_REVERSE_Pos DW_CRC_CTL_REM_REVERSE_Pos
354 #define DW_V2_CRC_DATA_CTL_DATA_XOR_Pos DW_CRC_DATA_CTL_DATA_XOR_Pos
355 #define DW_V2_CRC_REM_CTL_REM_XOR_Pos DW_CRC_REM_CTL_REM_XOR_Pos
356 #define DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos DW_CRC_POL_CTL_POLYNOMIAL_Pos
357 #define DW_V2_CRC_LFSR_CTL_LFSR32_Pos DW_CRC_LFSR_CTL_LFSR32_Pos
358 #endif /* CY_IP_MXDW */
359
360 /*******************************************************************************
361 * DMAC
362 *******************************************************************************/
363 #if defined (CY_IP_MXAHBDMAC)
364 #define CY_DMAC_CH_NR (4UL)
365 #define DMAC_CTL(base) (((MXAHBDMAC_Type*)(base))->CTL)
366 #define DMAC_ACTIVE(base) (((MXAHBDMAC_Type const*)(base))->ACTIVE)
367 #define DMAC_CH(base, chan) (&(((MXAHBDMAC_Type*)(base))->CH[(chan)]))
368 #define DMAC_CH_CTL(base, chan) (DMAC_CH(base, chan)->CTL)
369 #define DMAC_CH_IDX(base, chan) (DMAC_CH(base, chan)->IDX)
370 #define DMAC_CH_CURR(base, chan) (DMAC_CH(base, chan)->CURR)
371 #define DMAC_CH_DESCR_SRC(base, chan) (DMAC_CH(base, chan)->DESCR_SRC)
372 #define DMAC_CH_DESCR_DST(base, chan) (DMAC_CH(base, chan)->DESCR_DST)
373 #define DMAC_CH_INTR(base, chan) (DMAC_CH(base, chan)->INTR)
374 #define DMAC_CH_INTR_SET(base, chan) (DMAC_CH(base, chan)->INTR_SET)
375 #define DMAC_CH_INTR_MASK(base, chan) (DMAC_CH(base, chan)->INTR_MASK)
376 #define DMAC_CH_INTR_MASKED(base, chan) (DMAC_CH(base, chan)->INTR_MASKED)
377
378 typedef MXAHBDMAC_Type DMAC_Type;
379 #define DMAC MXAHBDMAC0_BASE
380
381 #define DMAC_CH_V2_INTR_COMPLETION_Msk MXAHBDMAC_CH_INTR_COMPLETION_Msk
382 #define DMAC_CH_V2_INTR_COMPLETION_Pos MXAHBDMAC_CH_INTR_COMPLETION_Pos
383 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk MXAHBDMAC_CH_INTR_SRC_BUS_ERROR_Msk
384 #define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos MXAHBDMAC_CH_INTR_SRC_BUS_ERROR_Pos
385 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk MXAHBDMAC_CH_INTR_DST_BUS_ERROR_Msk
386 #define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos MXAHBDMAC_CH_INTR_DST_BUS_ERROR_Pos
387 #define DMAC_CH_V2_INTR_SRC_MISAL_Msk MXAHBDMAC_CH_INTR_SRC_MISAL_Msk
388 #define DMAC_CH_V2_INTR_SRC_MISAL_Pos MXAHBDMAC_CH_INTR_SRC_MISAL_Pos
389 #define DMAC_CH_V2_INTR_DST_MISAL_Msk MXAHBDMAC_CH_INTR_DST_MISAL_Msk
390 #define DMAC_CH_V2_INTR_DST_MISAL_Pos MXAHBDMAC_CH_INTR_DST_MISAL_Pos
391 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk MXAHBDMAC_CH_INTR_CURR_PTR_NULL_Msk
392 #define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos MXAHBDMAC_CH_INTR_CURR_PTR_NULL_Pos
393 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk MXAHBDMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk
394 #define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos MXAHBDMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos
395 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk MXAHBDMAC_CH_INTR_DESCR_BUS_ERROR_Msk
396 #define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos MXAHBDMAC_CH_INTR_DESCR_BUS_ERROR_Pos
397 #define DMAC_Type MXAHBDMAC_Type
398 #define DMAC_V2_CTL_ENABLED_Msk MXAHBDMAC_CTL_ENABLED_Msk
399 #define DMAC_V2_CTL_ENABLED_Pos MXAHBDMAC_CTL_ENABLED_Pos
400 #define DMAC_V2_ACTIVE_ACTIVE_Msk MXAHBDMAC_ACTIVE_ACTIVE_Msk
401 #define DMAC_V2_ACTIVE_ACTIVE_Pos MXAHBDMAC_ACTIVE_ACTIVE_Pos
402 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_INTR_TYPE_Msk
403 #define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_INTR_TYPE_Pos
404 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk
405 #define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos
406 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk
407 #define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos
408 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk MXAHBDMAC_CH_DESCR_CTL_DATA_SIZE_Msk
409 #define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos MXAHBDMAC_CH_DESCR_CTL_DATA_SIZE_Pos
410 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk MXAHBDMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Msk
411 #define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos MXAHBDMAC_CH_DESCR_CTL_SRC_TRANSFER_SIZE_Pos
412 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk MXAHBDMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Msk
413 #define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos MXAHBDMAC_CH_DESCR_CTL_DST_TRANSFER_SIZE_Pos
414 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk MXAHBDMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk
415 #define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos MXAHBDMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos
416 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk MXAHBDMAC_CH_DESCR_CTL_DESCR_TYPE_Msk
417 #define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos MXAHBDMAC_CH_DESCR_CTL_DESCR_TYPE_Pos
418 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk MXAHBDMAC_CH_DESCR_CTL_CH_DISABLE_Msk
419 #define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos MXAHBDMAC_CH_DESCR_CTL_CH_DISABLE_Pos
420 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk MXAHBDMAC_CH_DESCR_X_INCR_SRC_X_Msk
421 #define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos MXAHBDMAC_CH_DESCR_X_INCR_SRC_X_Pos
422 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk MXAHBDMAC_CH_DESCR_X_INCR_DST_X_Msk
423 #define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos MXAHBDMAC_CH_DESCR_X_INCR_DST_X_Pos
424 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk MXAHBDMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk
425 #define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos MXAHBDMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos
426 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk MXAHBDMAC_CH_DESCR_Y_INCR_SRC_Y_Msk
427 #define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos MXAHBDMAC_CH_DESCR_Y_INCR_SRC_Y_Pos
428 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk MXAHBDMAC_CH_DESCR_Y_INCR_DST_Y_Msk
429 #define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos MXAHBDMAC_CH_DESCR_Y_INCR_DST_Y_Pos
430 #define DMAC_CH_V2_CTL_ENABLED_Msk MXAHBDMAC_CH_CTL_ENABLED_Msk
431 #define DMAC_CH_V2_CTL_ENABLED_Pos MXAHBDMAC_CH_CTL_ENABLED_Pos
432 #define DMAC_CH_V2_CTL_PRIO_Msk MXAHBDMAC_CH_CTL_PRIO_Msk
433 #define DMAC_CH_V2_CTL_PRIO_Pos MXAHBDMAC_CH_CTL_PRIO_Pos
434 #define DMAC_CH_V2_IDX_X_Msk MXAHBDMAC_CH_IDX_X_Msk
435 #define DMAC_CH_V2_IDX_X_Pos MXAHBDMAC_CH_IDX_X_Pos
436 #define DMAC_CH_V2_IDX_Y_Msk MXAHBDMAC_CH_IDX_Y_Msk
437 #define DMAC_CH_V2_IDX_Y_Pos MXAHBDMAC_CH_IDX_Y_Pos
438 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk MXAHBDMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk
439 #define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos MXAHBDMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos
440 #define DMAC_CH_V2_CTL_B_Msk MXAHBDMAC_CH_CTL_B_Msk
441 #define DMAC_CH_V2_CTL_B_Pos MXAHBDMAC_CH_CTL_B_Pos
442 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk MXAHBDMAC_CH_DESCR_X_SIZE_X_COUNT_Msk
443 #define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos MXAHBDMAC_CH_DESCR_X_SIZE_X_COUNT_Pos
444
445 #endif
446
447 /*******************************************************************************
448 * CRYPTOLITE
449 *******************************************************************************/
450 #define CY_PLATFORM_REMAP_ADDRESS_CRYPTOLITE(addr) (Cy_Platform_RemapAddr(addr))
451
452
453 #if defined(CY_DEVICE_BOY2)
Cy_Platform_RemapAddr(const void * addr)454 static inline void * Cy_Platform_RemapAddr(const void *addr)
455 {
456 uint32_t remapAddr, offset;
457
458 #if defined(COMPONENT_SECURE_DEVICE)
459 /* FLASH Address Secure */
460 if (((uint32_t)addr >= CY_FLASH_S_SBUS_BASE) &&
461 ((uint32_t)addr < (CY_FLASH_S_SBUS_BASE + CY_FLASH_SIZE)))
462 {
463 offset = (uint32_t)addr - CY_FLASH_S_SBUS_BASE;
464 remapAddr = CY_FLASH_S_CBUS_BASE + offset;
465 }
466 /* SFLASH Address Secure */
467 else if (((uint32_t)addr >= CY_SFLASH_S_SBUS_BASE) &&
468 ((uint32_t)addr < (CY_SFLASH_S_SBUS_BASE + CY_SFLASH_SIZE)))
469 {
470 offset = (uint32_t)addr - CY_SFLASH_S_SBUS_BASE;
471 remapAddr = CY_SFLASH_S_CBUS_BASE + offset;
472 }
473 /* SRAM Address Secure */
474 else if (((uint32_t)addr >= CY_SRAM0_S_CBUS_BASE) &&
475 ((uint32_t)addr < (CY_SRAM0_S_CBUS_BASE + CY_SRAM0_SIZE)))
476 {
477 offset = (uint32_t)addr - CY_SRAM0_S_CBUS_BASE;
478 remapAddr = CY_SRAM0_S_SBUS_BASE + offset;
479 }
480 #else
481 /* FLASH Address Non-Secure */
482 if (((uint32_t)addr >= CY_FLASH_NS_SBUS_BASE) &&
483 ((uint32_t)addr < (CY_FLASH_NS_SBUS_BASE + CY_FLASH_SIZE)))
484 {
485 offset = (uint32_t)addr - CY_FLASH_NS_SBUS_BASE;
486 remapAddr = CY_FLASH_NS_CBUS_BASE + offset;
487 }
488 /* SFLASH Address Non-Secure */
489 else if (((uint32_t)addr >= CY_SFLASH_NS_SBUS_BASE) &&
490 ((uint32_t)addr < (CY_SFLASH_NS_SBUS_BASE + CY_SFLASH_SIZE)))
491 {
492 offset = (uint32_t)addr - CY_SFLASH_NS_SBUS_BASE;
493 remapAddr = CY_SFLASH_NS_CBUS_BASE + offset;
494 }
495 /* SRAM Address Non-Secure */
496 else if (((uint32_t)addr >= CY_SRAM0_NS_CBUS_BASE) &&
497 ((uint32_t)addr < (CY_SRAM0_NS_CBUS_BASE + CY_SRAM0_SIZE)))
498 {
499 offset = (uint32_t)addr - CY_SRAM0_NS_CBUS_BASE;
500 remapAddr = CY_SRAM0_NS_SBUS_BASE + offset;
501 }
502 #endif
503 else
504 {
505 remapAddr = (uint32_t)addr;
506 }
507 return (void *)remapAddr;
508 }
509 #else
Cy_Platform_RemapAddr(const void * addr)510 static inline void * Cy_Platform_RemapAddr(const void *addr)
511 {
512 uint32_t remapAddr, offset;
513
514 /* XIP Address*/
515 if (((uint32_t)addr >= CY_XIP_NS_CBUS_BASE) &&
516 ((uint32_t)addr < (CY_XIP_NS_CBUS_BASE + CY_XIP_SIZE)))
517 {
518 offset = (uint32_t)addr - CY_XIP_NS_CBUS_BASE;
519 remapAddr = CY_XIP_NS_SBUS_BASE + offset;
520 }
521 /* SRAM Address*/
522 else if (((uint32_t)addr >= CY_SRAM0_NS_CBUS_BASE) &&
523 ((uint32_t)addr < (CY_SRAM0_NS_CBUS_BASE + CY_SRAM0_SIZE)))
524 {
525 offset = (uint32_t)addr - CY_SRAM0_NS_CBUS_BASE;
526 remapAddr = CY_SRAM0_NS_SBUS_BASE + offset;
527 }
528 else
529 {
530 remapAddr = (uint32_t)addr;
531 }
532 return (void *)remapAddr;
533
534 }
535
536
537
538
539
540 #endif
541
542 /*******************************************************************************
543 * IOSS
544 *******************************************************************************/
545
546 #define CY_GPIO_BASE ((uint32_t)GPIO_BASE)
547
548 #define GPIO_SEC_INTR_CAUSE0 ((GPIO)->SEC_INTR_CAUSE0)
549 #define GPIO_SEC_INTR_CAUSE1 ((GPIO)->SEC_INTR_CAUSE1)
550 #define GPIO_SEC_INTR_CAUSE2 ((GPIO)->SEC_INTR_CAUSE2)
551 #define GPIO_SEC_INTR_CAUSE3 ((GPIO)->SEC_INTR_CAUSE3)
552 #define GPIO_INTR_CAUSE0 ((GPIO)->INTR_CAUSE0)
553 #define GPIO_INTR_CAUSE1 ((GPIO)->INTR_CAUSE1)
554 #define GPIO_INTR_CAUSE2 ((GPIO)->INTR_CAUSE2)
555 #define GPIO_INTR_CAUSE3 ((GPIO)->INTR_CAUSE3)
556
557 #define GPIO_PRT_OUT(base) (((GPIO_PRT_Type*)(base))->OUT)
558 #define GPIO_PRT_OUT_CLR(base) (((GPIO_PRT_Type*)(base))->OUT_CLR)
559 #define GPIO_PRT_OUT_SET(base) (((GPIO_PRT_Type*)(base))->OUT_SET)
560 #define GPIO_PRT_OUT_INV(base) (((GPIO_PRT_Type*)(base))->OUT_INV)
561 #define GPIO_PRT_IN(base) (((GPIO_PRT_Type*)(base))->IN)
562 #define GPIO_PRT_INTR(base) (((GPIO_PRT_Type*)(base))->INTR)
563 #define GPIO_PRT_INTR_MASK(base) (((GPIO_PRT_Type*)(base))->INTR_MASK)
564 #define GPIO_PRT_INTR_MASKED(base) (((GPIO_PRT_Type*)(base))->INTR_MASKED)
565 #define GPIO_PRT_INTR_SET(base) (((GPIO_PRT_Type*)(base))->INTR_SET)
566 #define GPIO_PRT_INTR_CFG(base) (((GPIO_PRT_Type*)(base))->INTR_CFG)
567 #define GPIO_PRT_CFG(base) (((GPIO_PRT_Type*)(base))->CFG)
568 #define GPIO_PRT_CFG_IN(base) (((GPIO_PRT_Type*)(base))->CFG_IN)
569 #define GPIO_PRT_CFG_OUT(base) (((GPIO_PRT_Type*)(base))->CFG_OUT)
570 #define GPIO_PRT_CFG_SIO(base) (((GPIO_PRT_Type*)(base))->CFG_SIO)
571 #define GPIO_PRT_SLEW_EXT(base) (((GPIO_PRT_Type*)(base))->CFG_SLEW_EXT)
572 #define GPIO_PRT_DRIVE_EXT0(base) (((GPIO_PRT_Type*)(base))->CFG_DRIVE_EXT0)
573 #define GPIO_PRT_DRIVE_EXT1(base) (((GPIO_PRT_Type*)(base))->CFG_DRIVE_EXT1)
574 #define GPIO_PRT_CFG_IN_AUTOLVL(base) (((GPIO_PRT_Type*)(base))->CFG_IN_AUTOLVL)
575
576 #define CY_HSIOM_BASE ((uint32_t)HSIOM_BASE)
577
578 #define HSIOM_PRT_PORT_SEL0(base) (((HSIOM_PRT_Type *)(base))->PORT_SEL0)
579 #define HSIOM_PRT_PORT_SEL1(base) (((HSIOM_PRT_Type *)(base))->PORT_SEL1)
580
581 #if (IOSS_HSIOM_HSIOM_SEC_PORT_NR != 0) || (CPUSS_CM33_0_SECEXT_PRESENT != 0)
582 #define CY_HSIOM_SECURE_BASE ((uint32_t)&HSIOM->SECURE_PRT[0])
583 #endif /* IOSS_HSIOM_HSIOM_SEC_PORT_NR, CPUSS_CM33_0_SECEXT_PRESENT */
584
585
586 #define HSIOM_SEC_PRT_NONSEC_MASK(base) (((HSIOM_SECURE_PRT_Type *)(base))->NONSECURE_MASK)
587
588
589 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_Type *)HSIOM_BASE)->AMUX_SPLIT_CTL[switchCtrl])
590
591 /*******************************************************************************
592 * SCB
593 *******************************************************************************/
594 #define SCB_CTRL(base) (((CySCB_Type*) (base))->CTRL)
595 #define SCB_SPI_CTRL(base) (((CySCB_Type*) (base))->SPI_CTRL)
596 #define SCB_SPI_STATUS(base) (((CySCB_Type*) (base))->SPI_STATUS)
597 #define SCB_SPI_TX_CTRL(base) (((CySCB_Type*) (base))->SPI_TX_CTRL)
598 #define SCB_SPI_RX_CTRL(base) (((CySCB_Type*) (base))->SPI_RX_CTRL)
599 #define SCB_UART_CTRL(base) (((CySCB_Type*) (base))->UART_CTRL)
600 #define SCB_UART_TX_CTRL(base) (((CySCB_Type*) (base))->UART_TX_CTRL)
601 #define SCB_UART_RX_CTRL(base) (((CySCB_Type*) (base))->UART_RX_CTRL)
602 #define SCB_UART_FLOW_CTRL(base) (((CySCB_Type*) (base))->UART_FLOW_CTRL)
603 #define SCB_I2C_CTRL(base) (((CySCB_Type*) (base))->I2C_CTRL)
604 #define SCB_I2C_STATUS(base) (((CySCB_Type*) (base))->I2C_STATUS)
605 #define SCB_I2C_M_CMD(base) (((CySCB_Type*) (base))->I2C_M_CMD)
606 #define SCB_I2C_S_CMD(base) (((CySCB_Type*) (base))->I2C_S_CMD)
607 #define SCB_I2C_CFG(base) (((CySCB_Type*) (base))->I2C_CFG)
608 #define SCB_I2C_STRETCH_CTRL(base) (((CySCB_Type*) (base))->I2C_STRETCH_CTRL)
609 #define SCB_I2C_STRETCH_STATUS(base) (((CySCB_Type*) (base))->I2C_STRETCH_STATUS)
610 #define SCB_TX_CTRL(base) (((CySCB_Type*) (base))->TX_CTRL)
611 #define SCB_TX_FIFO_CTRL(base) (((CySCB_Type*) (base))->TX_FIFO_CTRL)
612 #define SCB_TX_FIFO_STATUS(base) (((CySCB_Type*) (base))->TX_FIFO_STATUS)
613 #define SCB_TX_FIFO_WR(base) (((CySCB_Type*) (base))->TX_FIFO_WR)
614 #define SCB_RX_CTRL(base) (((CySCB_Type*) (base))->RX_CTRL)
615 #define SCB_RX_FIFO_CTRL(base) (((CySCB_Type*) (base))->RX_FIFO_CTRL)
616 #define SCB_RX_FIFO_STATUS(base) (((CySCB_Type*) (base))->RX_FIFO_STATUS)
617 #define SCB_RX_MATCH(base) (((CySCB_Type*) (base))->RX_MATCH)
618 #define SCB_RX_FIFO_RD(base) (((CySCB_Type*) (base))->RX_FIFO_RD)
619 #define SCB_INTR_CAUSE(base) (((CySCB_Type*) (base))->INTR_CAUSE)
620 #define SCB_INTR_I2C_EC(base) (((CySCB_Type*) (base))->INTR_I2C_EC)
621 #define SCB_INTR_I2C_EC_MASK(base) (((CySCB_Type*) (base))->INTR_I2C_EC_MASK)
622 #define SCB_INTR_I2C_EC_MASKED(base) (((CySCB_Type*) (base))->INTR_I2C_EC_MASKED)
623 #define SCB_INTR_SPI_EC(base) (((CySCB_Type*) (base))->INTR_SPI_EC)
624 #define SCB_INTR_SPI_EC_MASK(base) (((CySCB_Type*) (base))->INTR_SPI_EC_MASK)
625 #define SCB_INTR_SPI_EC_MASKED(base) (((CySCB_Type*) (base))->INTR_SPI_EC_MASKED)
626 #define SCB_INTR_M(base) (((CySCB_Type*) (base))->INTR_M)
627 #define SCB_INTR_M_SET(base) (((CySCB_Type*) (base))->INTR_M_SET)
628 #define SCB_INTR_M_MASK(base) (((CySCB_Type*) (base))->INTR_M_MASK)
629 #define SCB_INTR_M_MASKED(base) (((CySCB_Type*) (base))->INTR_M_MASKED)
630 #define SCB_INTR_S(base) (((CySCB_Type*) (base))->INTR_S)
631 #define SCB_INTR_S_SET(base) (((CySCB_Type*) (base))->INTR_S_SET)
632 #define SCB_INTR_S_MASK(base) (((CySCB_Type*) (base))->INTR_S_MASK)
633 #define SCB_INTR_S_MASKED(base) (((CySCB_Type*) (base))->INTR_S_MASKED)
634 #define SCB_INTR_TX(base) (((CySCB_Type*) (base))->INTR_TX)
635 #define SCB_INTR_TX_SET(base) (((CySCB_Type*) (base))->INTR_TX_SET)
636 #define SCB_INTR_TX_MASK(base) (((CySCB_Type*) (base))->INTR_TX_MASK)
637 #define SCB_INTR_TX_MASKED(base) (((CySCB_Type*) (base))->INTR_TX_MASKED)
638 #define SCB_INTR_RX(base) (((CySCB_Type*) (base))->INTR_RX)
639 #define SCB_INTR_RX_SET(base) (((CySCB_Type*) (base))->INTR_RX_SET)
640 #define SCB_INTR_RX_MASK(base) (((CySCB_Type*) (base))->INTR_RX_MASK)
641 #define SCB_INTR_RX_MASKED(base) (((CySCB_Type*) (base))->INTR_RX_MASKED)
642
643 #if(CY_IP_MXSCB_VERSION>=4)
644 #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos SCB_SPI_CTRL_LATE_SAMPLE_Pos
645 #define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk SCB_SPI_CTRL_LATE_SAMPLE_Msk
646 #endif
647
648
649 /*******************************************************************************
650 * I3C
651 *******************************************************************************/
652
653
654 #define I3C_CORE_DEVICE_CTRL(base) (((I3C_CORE_Type*) (base))->DEVICE_CTRL)
655 #define I3C_CORE_DEVICE_ADDR(base) (((I3C_CORE_Type*) (base))->DEVICE_ADDR)
656 #define I3C_CORE_HW_CAPABILITY(base) (((I3C_CORE_Type*) (base))->HW_CAPABILITY)
657 #define I3C_CORE_COMMAND_QUEUE_PORT(base) (((I3C_CORE_Type*) (base))->COMMAND_QUEUE_PORT)
658 #define I3C_CORE_RESPONSE_QUEUE_PORT(base) (((I3C_CORE_Type*) (base))->RESPONSE_QUEUE_PORT)
659 #define I3C_CORE_TX_RX_DATA_PORT(base) (((I3C_CORE_Type*) (base))->TX_RX_DATA_PORT)
660 #define I3C_CORE_IBI_QUEUE_STATUS(base) (((I3C_CORE_Type*) (base))->IBI_QUEUE_STATUS)
661 #define I3C_CORE_QUEUE_THLD_CTRL(base) (((I3C_CORE_Type*) (base))->QUEUE_THLD_CTRL)
662 #define I3C_CORE_DATA_BUFFER_THLD_CTRL(base) (((I3C_CORE_Type*) (base))->DATA_BUFFER_THLD_CTRL)
663 #define I3C_CORE_IBI_QUEUE_CTRL(base) (((I3C_CORE_Type*) (base))->IBI_QUEUE_CTRL)
664 #define I3C_CORE_IBI_MR_REQ_REJECT(base) (((I3C_CORE_Type*) (base))->IBI_MR_REQ_REJECT)
665 #define I3C_CORE_IBI_SIR_REQ_REJECT(base) (((I3C_CORE_Type*) (base))->IBI_SIR_REQ_REJECT)
666 #define I3C_CORE_RESET_CTRL(base) (((I3C_CORE_Type*) (base))->RESET_CTRL)
667 #define I3C_CORE_SLV_EVENT_STATUS(base) (((I3C_CORE_Type*) (base))->SLV_EVENT_STATUS)
668 #define I3C_CORE_INTR_STATUS(base) (((I3C_CORE_Type*) (base))->INTR_STATUS)
669 #define I3C_CORE_INTR_STATUS_EN(base) (((I3C_CORE_Type*) (base))->INTR_STATUS_EN)
670 #define I3C_CORE_INTR_SIGNAL_EN(base) (((I3C_CORE_Type*) (base))->INTR_SIGNAL_EN)
671 #define I3C_CORE_INTR_FORCE(base) (((I3C_CORE_Type*) (base))->INTR_FORCE)
672 #define I3C_CORE_QUEUE_STATUS_LEVEL(base) (((I3C_CORE_Type*) (base))->QUEUE_STATUS_LEVEL)
673 #define I3C_CORE_DATA_BUFFER_STATUS_LEVEL(base) (((I3C_CORE_Type*) (base))->DATA_BUFFER_STATUS_LEVEL)
674 #define I3C_CORE_PRESENT_STATE(base) (((I3C_CORE_Type*) (base))->PRESENT_STATE)
675 #define I3C_CORE_CCC_DEVICE_STATUS(base) (((I3C_CORE_Type*) (base))->CCC_DEVICE_STATUS)
676 #define I3C_CORE_DEVICE_ADDR_TABLE_POINTER(base) (((I3C_CORE_Type*) (base))->DEVICE_ADDR_TABLE_POINTER)
677 #define I3C_CORE_DEV_CHAR_TABLE_POINTER(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE_POINTER)
678 #define I3C_CORE_VENDOR_SPECIFIC_REG_POINTER(base) (((I3C_CORE_Type*) (base))->VENDOR_SPECIFIC_REG_POINTER)
679 #define I3C_CORE_SLV_PID_VALUE(base) (((I3C_CORE_Type*) (base))->SLV_PID_VALUE)
680 #define I3C_CORE_SLV_CHAR_CTRL(base) (((I3C_CORE_Type*) (base))->SLV_CHAR_CTRL)
681 #define I3C_CORE_SLV_MAX_LEN(base) (((I3C_CORE_Type*) (base))->SLV_MAX_LEN)
682 #define I3C_CORE_MAX_READ_TURNAROUND(base) (((I3C_CORE_Type*) (base))->MAX_READ_TURNAROUND)
683 #define I3C_CORE_MAX_DATA_SPEED(base) (((I3C_CORE_Type*) (base))->MAX_DATA_SPEED)
684 #define I3C_CORE_SLV_INTR_REQ(base) (((I3C_CORE_Type*) (base))->SLV_INTR_REQ)
685 #define I3C_CORE_DEVICE_CTRL_EXTENDED(base) (((I3C_CORE_Type*) (base))->DEVICE_CTRL_EXTENDED)
686 #define I3C_CORE_SCL_I3C_OD_TIMING(base) (((I3C_CORE_Type*) (base))->SCL_I3C_OD_TIMING)
687 #define I3C_CORE_SCL_I3C_PP_TIMING(base) (((I3C_CORE_Type*) (base))->SCL_I3C_PP_TIMING)
688 #define I3C_CORE_SCL_I2C_FM_TIMING(base) (((I3C_CORE_Type*) (base))->SCL_I2C_FM_TIMING)
689 #define I3C_CORE_SCL_I2C_FMP_TIMING(base) (((I3C_CORE_Type*) (base))->SCL_I2C_FMP_TIMING)
690 #define I3C_CORE_SCL_EXT_LCNT_TIMING(base) (((I3C_CORE_Type*) (base))->SCL_EXT_LCNT_TIMING)
691 #define I3C_CORE_SCL_EXT_TERMN_LCNT_TIMING(base) (((I3C_CORE_Type*) (base))->SCL_EXT_TERMN_LCNT_TIMING)
692 #define I3C_CORE_SDA_HOLD_DLY_TIMING(base) (((I3C_CORE_Type*) (base))->SDA_HOLD_DLY_TIMING)
693 #define I3C_CORE_BUS_FREE_AVAIL_TIMING(base) (((I3C_CORE_Type*) (base))->BUS_FREE_AVAIL_TIMING)
694 #define I3C_CORE_BUS_IDLE_TIMING(base) (((I3C_CORE_Type*) (base))->BUS_IDLE_TIMING)
695 #define I3C_CORE_I3C_VER_ID(base) (((I3C_CORE_Type*) (base))->I3C_VER_ID)
696 #define I3C_CORE_I3C_VER_TYPE(base) (((I3C_CORE_Type*) (base))->I3C_VER_TYPE)
697 #define I3C_CORE_QUEUE_SIZE_CAPABILITY(base) (((I3C_CORE_Type*) (base))->QUEUE_SIZE_CAPABILITY)
698 #define I3C_CORE_DEV_CHAR_TABLE1_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC1)
699 #define I3C_CORE_DEV_CHAR_TABLE1_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC2)
700 #define I3C_CORE_DEV_CHAR_TABLE1_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC3)
701 #define I3C_CORE_DEV_CHAR_TABLE1_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE1_LOC4)
702 #define I3C_CORE_DEV_CHAR_TABLE2_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC1)
703 #define I3C_CORE_DEV_CHAR_TABLE2_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC2)
704 #define I3C_CORE_DEV_CHAR_TABLE2_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC3)
705 #define I3C_CORE_DEV_CHAR_TABLE2_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE2_LOC4)
706 #define I3C_CORE_DEV_CHAR_TABLE3_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC1)
707 #define I3C_CORE_DEV_CHAR_TABLE3_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC2)
708 #define I3C_CORE_DEV_CHAR_TABLE3_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC3)
709 #define I3C_CORE_DEV_CHAR_TABLE3_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE3_LOC4)
710 #define I3C_CORE_DEV_CHAR_TABLE4_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC1)
711 #define I3C_CORE_DEV_CHAR_TABLE4_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC2)
712 #define I3C_CORE_DEV_CHAR_TABLE4_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC3)
713 #define I3C_CORE_DEV_CHAR_TABLE4_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE4_LOC4)
714 #define I3C_CORE_DEV_CHAR_TABLE5_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC1)
715 #define I3C_CORE_DEV_CHAR_TABLE5_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC2)
716 #define I3C_CORE_DEV_CHAR_TABLE5_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC3)
717 #define I3C_CORE_DEV_CHAR_TABLE5_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE5_LOC4)
718 #define I3C_CORE_DEV_CHAR_TABLE6_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC1)
719 #define I3C_CORE_DEV_CHAR_TABLE6_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC2)
720 #define I3C_CORE_DEV_CHAR_TABLE6_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC3)
721 #define I3C_CORE_DEV_CHAR_TABLE6_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE6_LOC4)
722 #define I3C_CORE_DEV_CHAR_TABLE7_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC1)
723 #define I3C_CORE_DEV_CHAR_TABLE7_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC2)
724 #define I3C_CORE_DEV_CHAR_TABLE7_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC3)
725 #define I3C_CORE_DEV_CHAR_TABLE7_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE7_LOC4)
726 #define I3C_CORE_DEV_CHAR_TABLE8_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC1)
727 #define I3C_CORE_DEV_CHAR_TABLE8_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC2)
728 #define I3C_CORE_DEV_CHAR_TABLE8_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC3)
729 #define I3C_CORE_DEV_CHAR_TABLE8_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE8_LOC4)
730 #define I3C_CORE_DEV_CHAR_TABLE9_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC1)
731 #define I3C_CORE_DEV_CHAR_TABLE9_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC2)
732 #define I3C_CORE_DEV_CHAR_TABLE9_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC3)
733 #define I3C_CORE_DEV_CHAR_TABLE9_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE9_LOC4)
734 #define I3C_CORE_DEV_CHAR_TABLE10_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC1)
735 #define I3C_CORE_DEV_CHAR_TABLE10_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC2)
736 #define I3C_CORE_DEV_CHAR_TABLE10_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC3)
737 #define I3C_CORE_DEV_CHAR_TABLE10_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE10_LOC4)
738 #define I3C_CORE_DEV_CHAR_TABLE11_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC1)
739 #define I3C_CORE_DEV_CHAR_TABLE11_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC2)
740 #define I3C_CORE_DEV_CHAR_TABLE11_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC3)
741 #define I3C_CORE_DEV_CHAR_TABLE11_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_CHAR_TABLE11_LOC4)
742 #define I3C_CORE_DEV_ADDR_TABLE_LOC1(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC1)
743 #define I3C_CORE_DEV_ADDR_TABLE_LOC2(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC2)
744 #define I3C_CORE_DEV_ADDR_TABLE_LOC3(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC3)
745 #define I3C_CORE_DEV_ADDR_TABLE_LOC4(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC4)
746 #define I3C_CORE_DEV_ADDR_TABLE_LOC5(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC5)
747 #define I3C_CORE_DEV_ADDR_TABLE_LOC6(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC6)
748 #define I3C_CORE_DEV_ADDR_TABLE_LOC7(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC7)
749 #define I3C_CORE_DEV_ADDR_TABLE_LOC8(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC8)
750 #define I3C_CORE_DEV_ADDR_TABLE_LOC9(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC9)
751 #define I3C_CORE_DEV_ADDR_TABLE_LOC10(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC10)
752 #define I3C_CORE_DEV_ADDR_TABLE_LOC11(base) (((I3C_CORE_Type*) (base))->DEV_ADDR_TABLE_LOC11)
753
754 /*******************************************************************************
755 * EFUSE
756 ******************************************************************************/
757
758 #define EFUSE_CTL(base) (((EFUSE_Type *) (base))->CTL)
759 #define EFUSE_TEST(base) (((EFUSE_Type *) (base))->TEST)
760 #define EFUSE_CMD(base) (((EFUSE_Type *) (base))->CMD)
761 #define EFUSE_CONFIG(base) (((EFUSE_Type *) (base))->CONFIG)
762 #define EFUSE_SEQ_DEFAULT(base) (((EFUSE_Type *) (base))->SEQ_DEFAULT)
763 #define EFUSE_SEQ_READ_CTL_0(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_0)
764 #define EFUSE_SEQ_READ_CTL_1(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_1)
765 #define EFUSE_SEQ_READ_CTL_2(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_2)
766 #define EFUSE_SEQ_READ_CTL_3(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_3)
767 #define EFUSE_SEQ_READ_CTL_4(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_4)
768 #define EFUSE_SEQ_READ_CTL_5(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_5)
769 #define EFUSE_SEQ_READ_CTL_6(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_6)
770 #define EFUSE_SEQ_READ_CTL_7(base) (((EFUSE_Type *) (base))->SEQ_READ_CTL_7)
771 #define EFUSE_SEQ_PROGRAM_CTL_0(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_0)
772 #define EFUSE_SEQ_PROGRAM_CTL_1(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_1)
773 #define EFUSE_SEQ_PROGRAM_CTL_2(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_2)
774 #define EFUSE_SEQ_PROGRAM_CTL_3(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_3)
775 #define EFUSE_SEQ_PROGRAM_CTL_4(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_4)
776 #define EFUSE_SEQ_PROGRAM_CTL_5(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_5)
777 #define EFUSE_SEQ_PROGRAM_CTL_6(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_6)
778 #define EFUSE_SEQ_PROGRAM_CTL_7(base) (((EFUSE_Type *) (base))->SEQ_PROGRAM_CTL_7)
779 #define EFUSE_BOOTROW(base) (((EFUSE_Type *) (base))->BOOTROW)
780
781 /*******************************************************************************
782 * FAULT
783 *******************************************************************************/
784
785 #define FAULT_CTL(base) (((FAULT_STRUCT_Type *)(base))->CTL)
786 #define FAULT_STATUS(base) (((FAULT_STRUCT_Type *)(base))->STATUS)
787 #define FAULT_DATA(base) (((FAULT_STRUCT_Type *)(base))->DATA)
788 #define FAULT_PENDING0(base) (((FAULT_STRUCT_Type *)(base))->PENDING0)
789 #define FAULT_PENDING1(base) (((FAULT_STRUCT_Type *)(base))->PENDING1)
790 #define FAULT_PENDING2(base) (((FAULT_STRUCT_Type *)(base))->PENDING2)
791 #define FAULT_MASK0(base) (((FAULT_STRUCT_Type *)(base))->MASK0)
792 #define FAULT_MASK1(base) (((FAULT_STRUCT_Type *)(base))->MASK1)
793 #define FAULT_MASK2(base) (((FAULT_STRUCT_Type *)(base))->MASK2)
794 #define FAULT_INTR(base) (((FAULT_STRUCT_Type *)(base))->INTR)
795 #define FAULT_INTR_SET(base) (((FAULT_STRUCT_Type *)(base))->INTR_SET)
796 #define FAULT_INTR_MASK(base) (((FAULT_STRUCT_Type *)(base))->INTR_MASK)
797 #define FAULT_INTR_MASKED(base) (((FAULT_STRUCT_Type *)(base))->INTR_MASKED)
798
799 /**
800 * \brief Instances of Fault data register.
801 */
802 typedef enum
803 {
804 CY_SYSFAULT_MPU_0 = 0, /* Bus master 0 MPU/SMPU. */
805 CY_SYSFAULT_MPU_1 = 1, /* Bus master 1 MPU. See MPU_0 description. */
806 CY_SYSFAULT_MPU_2 = 2, /* Bus master 2 MPU. See MPU_0 description. */
807 CY_SYSFAULT_MPU_3 = 3, /* Bus master 3 MPU. See MPU_0 description. */
808 CY_SYSFAULT_MPU_4 = 4, /* Bus master 4 MPU. See MPU_0 description. */
809 CY_SYSFAULT_MPU_5 = 5, /* Bus master 5 MPU. See MPU_0 description. */
810 CY_SYSFAULT_MPU_6 = 6, /* Bus master 6 MPU. See MPU_0 description. */
811 CY_SYSFAULT_MPU_7 = 7, /* Bus master 7 MPU. See MPU_0 description. */
812 CY_SYSFAULT_MPU_8 = 8, /* Bus master 8 MPU. See MPU_0 description. */
813 CY_SYSFAULT_MPU_9 = 9, /* Bus master 9 MPU. See MPU_0 description. */
814 CY_SYSFAULT_MPU_10 = 10, /* Bus master 10 MPU. See MPU_0 description. */
815 CY_SYSFAULT_MPU_11 = 11, /* Bus master 11 MPU. See MPU_0 description. */
816 CY_SYSFAULT_MPU_12 = 12, /* Bus master 12 MPU. See MPU_0 description. */
817 CY_SYSFAULT_MPU_13 = 13, /* Bus master 13 MPU. See MPU_0 description. */
818 CY_SYSFAULT_MPU_14 = 14, /* Bus master 14 MPU. See MPU_0 description. */
819 CY_SYSFAULT_MPU_15 = 15, /* Bus master 15 MPU. See MPU_0 description. */
820 CY_SYSFAULT_CM4_SYS_MPU = 16, /* CM4 system bus AHB-Lite interface MPU. See MPU_0 description. */
821 CY_SYSFAULT_CM4_CODE_MPU = 17, /* CM4 code bus AHB-Lite interface MPU for non flash controller accesses. See MPU_0 description. */
822 CM4_CODE_FLASHC_MPU = 18, /* CM4 code bus AHB-Lite interface MPU for flash controller accesses. See MPU_0 description. */
823 CY_SYSFAULT_MS_PPU_4 = 25, /* Peripheral interconnect, master interface 4 PPU. See MS_PPU_0 description. */
824 CY_SYSFAULT_PERI_ECC = 26, /* Peripheral interconnect, protection structures SRAM, correctable ECC error: */
825 CY_SYSFAULT_PERI_NC_ECC = 27, /* Peripheral interconnect, protection structures SRAM, non-correctable ECC error. */
826 CY_SYSFAULT_MS_PPU_0 = 28, /* Peripheral interconnect, master interface 0 PPU. */
827 CY_SYSFAULT_MS_PPU_1 = 29, /* Peripheral interconnect, master interface 1 PPU. See MS_PPU_0 description. */
828 CY_SYSFAULT_MS_PPU_2 = 30, /* Peripheral interconnect, master interface 2 PPU. See MS_PPU_0 description. */
829 CY_SYSFAULT_MS_PPU_3 = 31, /* Peripheral interconnect, master interface 3 PPU. See MS_PPU_0 description. */
830 CY_SYSFAULT_GROUP_FAULT_0 = 32, /* Peripheral group 0 fault detection. */
831 CY_SYSFAULT_GROUP_FAULT_1 = 33, /* Peripheral group 1 fault detection. See GROUP_FAULT_0 description. */
832 CY_SYSFAULT_GROUP_FAULT_2 = 34, /* Peripheral group 2 fault detection. See GROUP_FAULT_0 description. */
833 CY_SYSFAULT_GROUP_FAULT_3 = 35, /* Peripheral group 3 fault detection. See GROUP_FAULT_0 description. */
834 CY_SYSFAULT_GROUP_FAULT_4 = 36, /* Peripheral group 4 fault detection. See GROUP_FAULT_0 description. */
835 CY_SYSFAULT_GROUP_FAULT_5 = 37, /* Peripheral group 5 fault detection. See GROUP_FAULT_0 description. */
836 CY_SYSFAULT_GROUP_FAULT_6 = 38, /* Peripheral group 6 fault detection. See GROUP_FAULT_0 description. */
837 CY_SYSFAULT_GROUP_FAULT_7 = 39, /* Peripheral group 7 fault detection. See GROUP_FAULT_0 description. */
838 CY_SYSFAULT_GROUP_FAULT_8 = 40, /* Peripheral group 8 fault detection. See GROUP_FAULT_0 description. */
839 CY_SYSFAULT_GROUP_FAULT_9 = 41, /* Peripheral group 9 fault detection. See GROUP_FAULT_0 description. */
840 CY_SYSFAULT_GROUP_FAULT_10 = 42, /* Peripheral group 10 fault detection. See GROUP_FAULT_0 description. */
841 CY_SYSFAULT_GROUP_FAULT_11 = 43, /* Peripheral group 11 fault detection. See GROUP_FAULT_0 description. */
842 CY_SYSFAULT_GROUP_FAULT_12 = 44, /* Peripheral group 12 fault detection. See GROUP_FAULT_0 description. */
843 CY_SYSFAULT_GROUP_FAULT_13 = 45, /* Peripheral group 13 fault detection. See GROUP_FAULT_0 description. */
844 CY_SYSFAULT_GROUP_FAULT_14 = 46, /* Peripheral group 14 fault detection. See GROUP_FAULT_0 description. */
845 CY_SYSFAULT_GROUP_FAULT_15 = 47, /* Peripheral group 15 fault detection. See GROUP_FAULT_0 description. */
846 CY_SYSFAULT_FLASHC_MAIN_BUS_ERROR = 48, /* Flash controller, main interface, bus error: */
847 CY_SYSFAULT_FLASHC_MAIN_C_ECC = 49, /* Flash controller, main interface, correctable ECC error: */
848 CY_SYSFAULT_FLASHC_MAIN_NC_ECC = 50, /* Flash controller, main interface, non-correctable ECC error. See FLASHC_MAIN_C_ECC description. */
849 CY_SYSFAULT_FLASHC_WORK_BUS_ERROR = 51, /* Flash controller, work interface, bus error. See FLASHC_MAIN_BUS_ERROR description. */
850 CY_SYSFAULT_FLASHC_WORK_C_ECC = 52, /* Flash controller, work interface, correctable ECC error: */
851 CY_SYSFAULT_FLASHC_WORK_NC_ECC = 53, /* Flash controller, work interface, non-correctable ECC error. See FLASHC_WORK_C_ECC description. */
852 CY_SYSFAULT_FLASHC_CM0_CA_C_ECC = 54, /* Flash controller, CM0+ cache, correctable ECC error: */
853 CY_SYSFAULT_FLASHC_CM0_CA_NC_ECC = 55, /* Flash controller, CM0+ cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description. */
854 CY_SYSFAULT_FLASHC_CM4_CA_C_ECC = 56, /* Flash controller, CM4 cache, correctable ECC error. See FLASHC_CM0_CA_C_ECC description. */
855 CY_SYSFAULT_FLASHC_CM4_CA_NC_ECC = 57, /* Flash controller, CM4 cache, non-correctable ECC error. See FLASHC_CM0_CA_C_ECC description.. */
856 CY_SYSFAULT_RAMC0_C_ECC = 58, /* System SRAM 0 correctable ECC error: */
857 CY_SYSFAULT_RAMC0_NC_ECC = 59, /* System SRAM 0 non-correctable ECC error. See RAMC0_C_ECC description. */
858 CY_SYSFAULT_RAMC1_C_ECC = 60, /* System SRAM 1 correctable ECC error. See RAMC0_C_ECC description. */
859 CY_SYSFAULT_RAMC1_NC_ECC = 61, /* System SRAM 1 non-correctable ECC error. See RAMC0_C_ECC description. */
860 CY_SYSFAULT_RAMC2_C_ECC = 62, /* System SRAM 2 correctable ECC error. See RAMC0_C_ECC description. */
861 CY_SYSFAULT_RAMC2_NC_ECC = 63, /* System SRAM 2 non-correctable ECC error. See RAMC0_C_ECC description. */
862 CY_SYSFAULT_CRYPTO_C_ECC = 64, /* Cryptography SRAM correctable ECC error. */
863 CY_SYSFAULT_CRYPTO_NC_ECC = 65, /* Cryptography SRAM non-correctable ECC error. See CRYPTO_C_ECC description. */
864 CY_SYSFAULT_DW0_C_ECC = 70, /* DataWire 0 SRAM 1 correctable ECC error: */
865 CY_SYSFAULT_DW0_NC_ECC = 71, /* DataWire 0 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. */
866 CY_SYSFAULT_DW1_C_ECC = 72, /* DataWire 1 SRAM 1 correctable ECC error. See DW0_C_ECC description. */
867 CY_SYSFAULT_DW1_NC_ECC = 73, /* DataWire 1 SRAM 1 non-correctable ECC error. See DW0_C_ECC description. */
868 CY_SYSFAULT_FM_SRAM_C_ECC = 74, /* eCT Flash SRAM (for embedded operations) correctable ECC error: */
869 CY_SYSFAULT_FM_SRAM_NC_ECC = 75, /* eCT Flash SRAM non-correctable ECC error: See FM_SRAM_C_ECC description. */
870 CY_SYSFAULT_CAN0_C_ECC = 80, /* CAN controller 0 MRAM correctable ECC error: */
871 CY_SYSFAULT_CAN0_NC_ECC = 81, /* CAN controller 0 MRAM non-correctable ECC error: */
872 CY_SYSFAULT_CAN1_C_ECC = 82, /* CAN controller 1 MRAM correctable ECC error. See CAN0_C_ECC description. */
873 CY_SYSFAULT_CAN1_NC_ECC = 83, /* CAN controller 1 MRAM non-correctable ECC error. See CAN0_NC_ECC description. */
874 CY_SYSFAULT_CAN2_C_ECC = 84, /* CAN controller 2 MRAM correctable ECC error. See CAN0_C_ECC description.. */
875 CY_SYSFAULT_CAN2_NC_ECC = 85, /* CAN controller 2 MRAM non-correctable ECC error. See CAN0_NC_ECC description. */
876 CY_SYSFAULT_SRSS_CSV = 90, /* SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. */
877 CY_SYSFAULT_SRSS_SSV = 91, /* SRSS Clock SuperVisor (CSV) violation detected. Multiple CSV can detect a violation at the same time. */
878 CY_SYSFAULT_SRSS_MCWDT0 = 92, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #0 violation detected. Multiple counters can detect a violation at the same time. */
879 CY_SYSFAULT_SRSS_MCWDT1 = 93, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #1 violation detected. See SRSS_MCWDT0 description. */
880 CY_SYSFAULT_SRSS_MCWDT2 = 94, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #2 violation detected. See SRSS_MCWDT0 description. */
881 CY_SYSFAULT_SRSS_MCWDT3 = 95, /* SRSS Multi-Counter Watch Dog Timer (MCWDT) #3 violation detected. See SRSS_MCWDT0 description. */
882 CY_SYSFAULT_NO_FAULT = 96
883 } cy_en_SysFault_source_t;
884
885 /*******************************************************************************
886 * PROFILE
887 *******************************************************************************/
888
889
890 #define CY_EP_MONITOR_COUNT ((uint32_t)(cy_device->epMonitorNr))
891 #define CY_EP_CNT_NR (8UL)
892 #define PROFILE_CTL (((PROFILE_Type*) PROFILE_BASE)->CTL)
893 #define PROFILE_STATUS (((PROFILE_Type*) PROFILE_BASE)->STATUS)
894 #define PROFILE_CMD (((PROFILE_Type*) PROFILE_BASE)->CMD)
895 #define PROFILE_INTR (((PROFILE_Type*) PROFILE_BASE)->INTR)
896 #define PROFILE_INTR_MASK (((PROFILE_Type*) PROFILE_BASE)->INTR_MASK)
897 #define PROFILE_INTR_MASKED (((PROFILE_Type*) PROFILE_BASE)->INTR_MASKED)
898 #define PROFILE_CNT_STRUCT (((PROFILE_Type*) PROFILE_BASE)->CNT_STRUCT)
899
900 /*******************************************************************************
901 * SRSS
902 *******************************************************************************/
903
904 #define CY_SRSS_NUM_PLL400M 0
905 #define CY_SRSS_PLL400M_PRESENT 0
906 #if defined (CY_DEVICE_BOY2)
907 #define CY_SRSS_DPLL_LP_PRESENT SRSS_NUM_DPLL250
908 #define SRSS_NUM_DPLL_LP SRSS_NUM_DPLL250
909 #define SRSS_PLL_250M_0_PATH_NUM (1UL)
910 #define SRSS_PLL_250M_1_PATH_NUM (2UL)
911 #define CY_SYSCLK_HF_MAX_FREQ(hfNum) (240000000U)
912 #define CY_MXS40SSRSS_VER_1_2 1UL
913 #define SRSS_DPLL_LP_FRAC_BIT_COUNT (24ULL)
914 #define SRSS_CLK_ROOT_SELECT_ROOT_DIV SRSS_CLK_ROOT_SELECT_ROOT_DIV_INT
915 #define PWRMODE_PWR_SELECT (((PWRMODE_Type *) PWRMODE)->CLK_SELECT)
916 #define SRSS_CLK_DPLL_LP_CONFIG(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG)
917 #define SRSS_CLK_DPLL_LP_CONFIG2(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG2)
918 #define SRSS_CLK_DPLL_LP_CONFIG3(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG3)
919 #define SRSS_CLK_DPLL_LP_CONFIG4(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG4)
920 #define SRSS_CLK_DPLL_LP_CONFIG5(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG5)
921 #define SRSS_CLK_DPLL_LP_CONFIG6(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG6)
922 #define SRSS_CLK_DPLL_LP_CONFIG7(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG7)
923 #define SRSS_CLK_DPLL_LP_STATUS(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].STATUS)
924 #define SRSS_TRIM_RAM_CTL (((SRSS_Type*) SRSS)->RAM_TRIM_STRUCT.TRIM_RAM_CTL)
925 #define SRSS_TRIM_ROM_CTL (((SRSS_Type*) SRSS)->RAM_TRIM_STRUCT.TRIM_ROM_CTL)
926 #define SRSS_PWR_TRIM_PWRSYS_CTL (*(volatile uint32_t *) 0x422020E0U)
927 #define SRSS_PWR_TRIM_WAKE_CTL (*(volatile uint32_t *) 0x422020E8U)
928 /* SRSS.PWR_TRIM_PWRSYS_CTL */
929 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL
930 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL
931 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL
932 #define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL
933 /* SRSS.PWR_TRIM_WAKE_CTL */
934 #define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
935 #define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
936
937 #else
938 #define CY_SRSS_DPLL_LP_PRESENT 0
939 #define CY_MXS40SSRSS_VER_1_2 0UL
940 #endif
941 #define CY_SRSS_NUM_CLKPATH SRSS_NUM_CLKPATH
942 #define CY_SRSS_NUM_PLL SRSS_NUM_TOTAL_PLL
943 #define CY_SRSS_NUM_HFROOT SRSS_NUM_HFROOT
944 #define CY_SRSS_ECO_PRESENT SRSS_ECO_PRESENT
945 #define CY_SRSS_FLL_PRESENT SRSS_FLL_PRESENT
946 #define CY_SRSS_PLL_PRESENT SRSS_NUM_TOTAL_PLL
947 #define CY_SRSS_ALTHF_PRESENT SRSS_ALTHF_PRESENT
948
949 #if defined (CY_IP_MXS28SRSS)
950 #define CY_SRSS_IHO_PRESENT 0
951 #define CY_SRSS_MFO_PRESENT 0
952 #endif
953
954 #if defined (CY_IP_MXS40SSRSS)
955 #define CY_SRSS_IHO_PRESENT 1
956 #define CY_SRSS_MFO_PRESENT 1
957 #define CY_SRSS_PILO_PRESENT SRSS_S40S_PILO_PRESENT
958 #define CY_SRSS_ILO_PRESENT 1
959 #define CY_SRSS_IMO_PRESENT 1
960 #endif
961
962
963 /** HF PATH # used for PERI PCLK */
964 #define CY_SYSCLK_CLK_PERI_HF_PATH_NUM 1U
965
966 /** HF PATH # used for Core */
967 #define CY_SYSCLK_CLK_CORE_HF_PATH_NUM 0U
968
969 /** FLL Max Frequency */
970 #define CY_SYSCLK_FLL_MAX_OUTPUT_FREQ (96000000UL)
971
972
973
974 /* HF PATH # Max Allowed Frequencies */
975 #define CY_SYSCLK_MAX_FREQ_HF0 96000000U
976 #define CY_SYSCLK_MAX_FREQ_HF1 96000000U
977 #define CY_SYSCLK_MAX_FREQ_HF2 48000000U
978 #define CY_SYSCLK_MAX_FREQ_HF3 24000000U
979
980
981 #if defined (CY_DEVICE_CYW20829)
982 #define CY_SYSCLK_HF_MAX_FREQ(hfNum) (((hfNum) == 0U) ? (CY_SYSCLK_MAX_FREQ_HF0) : \
983 (((hfNum) == 1U) ? (CY_SYSCLK_MAX_FREQ_HF1) : \
984 (((hfNum) == 2U) ? (CY_SYSCLK_MAX_FREQ_HF2) : \
985 (((hfNum) == 3U) ? (CY_SYSCLK_MAX_FREQ_HF3) : \
986 (0U)))))
987 #endif
988
989 /* Technology Independant Register set */
990 #define SRSS_CLK_DSI_SELECT (((SRSS_Type *) SRSS)->CLK_DSI_SELECT)
991 #define SRSS_CLK_OUTPUT_FAST (((SRSS_Type *) SRSS)->CLK_OUTPUT_FAST)
992 #define SRSS_CLK_OUTPUT_SLOW (((SRSS_Type *) SRSS)->CLK_OUTPUT_SLOW)
993 #define SRSS_CLK_CAL_CNT1 (((SRSS_Type *) SRSS)->CLK_CAL_CNT1)
994 #define SRSS_CLK_CAL_CNT2 (((SRSS_Type *) SRSS)->CLK_CAL_CNT2)
995 #define SRSS_SRSS_INTR (((SRSS_Type *) SRSS)->SRSS_INTR)
996 #define SRSS_SRSS_INTR_SET (((SRSS_Type *) SRSS)->SRSS_INTR_SET)
997 #define SRSS_SRSS_INTR_MASK (((SRSS_Type *) SRSS)->SRSS_INTR_MASK)
998 #define SRSS_SRSS_INTR_MASKED (((SRSS_Type *) SRSS)->SRSS_INTR_MASKED)
999 #define SRSS_SRSS_AINTR (((SRSS_Type *) SRSS)->SRSS_AINTR)
1000 #define SRSS_SRSS_AINTR_SET (((SRSS_Type *) SRSS)->SRSS_AINTR_SET)
1001 #define SRSS_SRSS_AINTR_MASK (((SRSS_Type *) SRSS)->SRSS_AINTR_MASK)
1002 #define SRSS_SRSS_AINTR_MASKED (((SRSS_Type *) SRSS)->SRSS_AINTR_MASKED)
1003 #define SRSS_PWR_CTL (((SRSS_Type *) SRSS)->PWR_CTL)
1004 #define SRSS_PWR_CTL2 (((SRSS_Type *) SRSS)->PWR_CTL2)
1005 #define SRSS_PWR_HIBERNATE (((SRSS_Type *) SRSS)->PWR_HIBERNATE)
1006 #define SRSS_PWR_CTL3 (((SRSS_Type *) SRSS)->PWR_CTL3)
1007 #define SRSS_PWR_STATUS (((SRSS_Type *) SRSS)->PWR_STATUS)
1008 #define SRSS_PWR_HIB_DATA (((SRSS_Type *) SRSS)->PWR_HIB_DATA)
1009 #define SRSS_CLK_PATH_SELECT (((SRSS_Type *) SRSS)->CLK_PATH_SELECT)
1010 #define SRSS_CLK_ROOT_SELECT (((SRSS_Type *) SRSS)->CLK_ROOT_SELECT)
1011 #define SRSS_CLK_DIRECT_SELECT (((SRSS_Type *) SRSS)->CLK_DIRECT_SELECT)
1012 #define SRSS_CLK_ECO_STATUS (((SRSS_Type *) SRSS)->CLK_ECO_STATUS)
1013 #define SRSS_CLK_ILO_CONFIG (((SRSS_Type *) SRSS)->CLK_ILO_CONFIG)
1014 #define SRSS_CLK_TRIM_ILO_CTL (((SRSS_Type *) SRSS)->CLK_TRIM_ILO_CTL)
1015 #define SRSS_CLK_PILO_CONFIG (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG)
1016 #define SRSS_CLK_ECO_CONFIG (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG)
1017 #define SRSS_CLK_ECO_CONFIG2 (((SRSS_Type *) SRSS)->CLK_ECO_CONFIG2)
1018 #define SRSS_CLK_MFO_CONFIG (((SRSS_Type *) SRSS)->CLK_MFO_CONFIG)
1019 #define SRSS_CLK_IHO_CONFIG (((SRSS_Type *) SRSS)->CLK_IHO_CONFIG)
1020 #define SRSS_CLK_ALTHF_CTL (((SRSS_Type *) SRSS)->CLK_ALTHF_CTL)
1021
1022 #if defined (CY_IP_MXS28SRSS)
1023 #define SRSS_CLK_ILO_CONFIG2 (((SRSS_Type *) SRSS)->CLK_ILO_CONFIG2)
1024 #define SRSS_CLK_PILO_CONFIG2 (((SRSS_Type *) SRSS)->CLK_PILO_CONFIG2)
1025 #endif
1026 #define SRSS_CSV_HF (((SRSS_Type *) SRSS)->CSV_HF)
1027 #define SRSS_CLK_SELECT (((SRSS_Type *) SRSS)->CLK_SELECT)
1028 #define SRSS_CLK_TIMER_CTL (((SRSS_Type *) SRSS)->CLK_TIMER_CTL)
1029 #define SRSS_CLK_IMO_CONFIG (((SRSS_Type *) SRSS)->CLK_IMO_CONFIG)
1030 #define SRSS_CLK_ECO_PRESCALE (((SRSS_Type *) SRSS)->CLK_ECO_PRESCALE)
1031 #define SRSS_CLK_MF_SELECT (((SRSS_Type *) SRSS)->CLK_MF_SELECT)
1032 #define SRSS_CSV_REF_SEL (((SRSS_Type *) SRSS)->CSV_REF_SEL)
1033 #define SRSS_CSV_REF (((SRSS_Type *) SRSS)->CSV_REF)
1034 #define SRSS_CSV_LF (((SRSS_Type *) SRSS)->CSV_LF)
1035 #define SRSS_CSV_ILO (((SRSS_Type *) SRSS)->CSV_ILO)
1036 #define SRSS_RES_CAUSE (((SRSS_Type *) SRSS)->RES_CAUSE)
1037 #define SRSS_RES_CAUSE2 (((SRSS_Type *) SRSS)->RES_CAUSE2)
1038 #define SRSS_RES_CAUSE_EXTEND (((SRSS_Type *) SRSS)->RES_CAUSE_EXTEND)
1039 #define SRSS_PWR_CBUCK_CTL (((SRSS_Type *) SRSS)->PWR_CBUCK_CTL)
1040 #define SRSS_PWR_CBUCK_CTL2 (((SRSS_Type *) SRSS)->PWR_CBUCK_CTL2)
1041 #define SRSS_PWR_CBUCK_CTL3 (((SRSS_Type *) SRSS)->PWR_CBUCK_CTL3)
1042 #define SRSS_PWR_CBUCK_STATUS (((SRSS_Type *) SRSS)->PWR_CBUCK_STATUS)
1043 #define SRSS_PWR_SDR0_CTL (((SRSS_Type *) SRSS)->PWR_SDR0_CTL)
1044 #define SRSS_PWR_SDR1_CTL (((SRSS_Type *) SRSS)->PWR_SDR1_CTL)
1045 #define SRSS_PWR_HVLDO0_CTL (((SRSS_Type *) SRSS)->PWR_HVLDO0_CTL)
1046 #define SRSS_CLK_LP_PLL (((SRSS_Type *) SRSS)->CLK_LP_PLL)
1047 #define SRSS_CLK_IHO (((SRSS_Type *) SRSS)->CLK_IHO)
1048 #define SRSS_TST_XRES_SECURE (((SRSS_Type *) SRSS)->TST_XRES_SECURE)
1049 #define SRSS_RES_PXRES_CTL (((SRSS_Type *) SRSS)->RES_PXRES_CTL)
1050 #define SRSS_WDT_CTL (((SRSS_Type *) SRSS)->WDT_CTL)
1051 #define SRSS_WDT_CNT (((SRSS_Type *) SRSS)->WDT_CNT)
1052 #define SRSS_WDT_MATCH (((SRSS_Type *) SRSS)->WDT_MATCH)
1053 #if defined (CY_IP_MXS40SSRSS)
1054 #define SRSS_WDT_MATCH2 (((SRSS_Type *) SRSS)->WDT_MATCH2)
1055 #endif
1056
1057 #if defined (CY_IP_MXS28SRSS)
1058 #define SRSS_CLK_LP_PLL_CONFIG(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG)
1059 #define SRSS_CLK_LP_PLL_CONFIG2(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG2)
1060 #define SRSS_CLK_LP_PLL_CONFIG3(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG3)
1061 #define SRSS_CLK_LP_PLL_CONFIG4(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG4)
1062 #define SRSS_CLK_LP_PLL_CONFIG5(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG5)
1063 #define SRSS_CLK_LP_PLL_STATUS(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.STATUS)
1064 #endif
1065
1066 #if defined (CY_IP_MXS40SSRSS)
1067 #define SRSS_CLK_FLL_CONFIG (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG)
1068 #define SRSS_CLK_FLL_CONFIG2 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG2)
1069 #define SRSS_CLK_FLL_CONFIG3 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG3)
1070 #define SRSS_CLK_FLL_CONFIG4 (((SRSS_Type *) SRSS)->CLK_FLL_CONFIG4)
1071 #define SRSS_CLK_FLL_STATUS (((SRSS_Type *) SRSS)->CLK_FLL_STATUS)
1072
1073 #define SRSS_PWR_LVD_CTL (((SRSS_Type *) SRSS)->PWR_LVD_CTL)
1074 #define SRSS_PWR_LVD_STATUS (((SRSS_Type *) SRSS)->PWR_LVD_STATUS)
1075
1076 #define SRSS_PWR_HIB_WAKE_CTL (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL)
1077 #define SRSS_PWR_HIB_WAKE_CTL2 (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CTL2)
1078 #define SRSS_PWR_HIB_WAKE_CAUSE (((SRSS_Type *) SRSS)->PWR_HIB_WAKE_CAUSE)
1079 #define SRSS_RES_SOFT_CTL (((SRSS_Type *) SRSS)->RES_SOFT_CTL)
1080 #endif
1081
1082 #if defined (CY_DEVICE_CYW20829)
1083 #define SRSS_TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x40201104U)
1084 #define SRSS_TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x40201108U)
1085 #else
1086 #define SRSS_TST_DDFT_FAST_CTL_REG (*(volatile uint32_t *) 0x42201104U)
1087 #define SRSS_TST_DDFT_SLOW_CTL_REG (*(volatile uint32_t *) 0x42201108U)
1088 #endif
1089
1090 #define SRSS_TST_DDFT_SLOW_CTL_MASK (0x00001F1EU)
1091 #define SRSS_TST_DDFT_FAST_CTL_MASK (62U)
1092
1093 #if defined (CY_IP_MXS40SSRSS)
1094 /* PPU configurations for DEEPSLEEP */
1095 #define CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE PPU_V1_MODE_FULL_RET
1096 #define CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_MODE PPU_V1_MODE_FULL_RET
1097 #define CY_SYSTEM_SRAM_PPU_DEEPSLEEP_MODE PPU_V1_MODE_MEM_RET
1098
1099 /* PPU configurations for DEEPSLEEP-RAM */
1100 #define CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE PPU_V1_MODE_MEM_RET
1101 #define CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_RAM_MODE PPU_V1_MODE_OFF
1102 #define CY_SYSTEM_SRAM_PPU_DEEPSLEEP_RAM_MODE PPU_V1_MODE_MEM_RET
1103
1104 /* PPU configurations for DEEPSLEEP-OFF */
1105 #define CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE PPU_V1_MODE_OFF
1106 #define CY_SYSTEM_CPUSS_PPU_DEEPSLEEP_OFF_MODE PPU_V1_MODE_OFF
1107 #define CY_SYSTEM_SRAM_PPU_DEEPSLEEP_OFF_MODE PPU_V1_MODE_OFF
1108
1109 /* System DEEPSLEEP Mode = (PPU_MAIN Mode)*/
1110 #define CY_SYSTEM_DEEPSLEEP_PPU_MODES ((uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_MODE)
1111 #define CY_SYSTEM_DEEPSLEEP_RAM_PPU_MODES ((uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_RAM_MODE)
1112 #define CY_SYSTEM_DEEPSLEEP_OFF_PPU_MODES ((uint32_t)CY_SYSTEM_MAIN_PPU_DEEPSLEEP_OFF_MODE)
1113 #endif
1114
1115 #define SRSS_CSV_HF_CSV_REF_CTL(hf) (((SRSS_Type *) SRSS)->CSV_HF_STRUCT.CSV[hf].REF_CTL)
1116 #define SRSS_CSV_HF_CSV_REF_LIMIT(hf) (((SRSS_Type *) SRSS)->CSV_HF_STRUCT.CSV[hf].REF_LIMIT)
1117 #define SRSS_CSV_HF_CSV_MON_CTL(hf) (((SRSS_Type *) SRSS)->CSV_HF_STRUCT.CSV[hf].MON_CTL)
1118 #define CSV_HF_CSV_REF_CTL_CSV_STARTUP CSV_HF_CSV_REF_CTL_STARTUP
1119 #define CSV_HF_CSV_REF_LIMIT_CSV_LOWER CSV_HF_CSV_REF_LIMIT_LOWER
1120 #define CSV_HF_CSV_REF_LIMIT_CSV_UPPER CSV_HF_CSV_REF_LIMIT_UPPER
1121 #define CSV_HF_CSV_MON_CTL_CSV_PERIOD CSV_HF_CSV_MON_CTL_PERIOD
1122
1123 #define SRSS_CSV_LF_CSV_REF_CTL (((SRSS_Type *) SRSS)->CSV_LF_STRUCT.CSV.REF_CTL)
1124 #define SRSS_CSV_LF_CSV_REF_LIMIT (((SRSS_Type *) SRSS)->CSV_LF_STRUCT.CSV.REF_LIMIT)
1125 #define SRSS_CSV_LF_CSV_MON_CTL (((SRSS_Type *) SRSS)->CSV_LF_STRUCT.CSV.MON_CTL)
1126 #define CSV_LF_CSV_REF_CTL_CSV_STARTUP CSV_LF_CSV_REF_CTL_STARTUP
1127 #define CSV_LF_CSV_REF_LIMIT_CSV_LOWER CSV_LF_CSV_REF_LIMIT_LOWER
1128 #define CSV_LF_CSV_REF_LIMIT_CSV_UPPER CSV_LF_CSV_REF_LIMIT_UPPER
1129 #define CSV_LF_CSV_MON_CTL_CSV_PERIOD CSV_LF_CSV_MON_CTL_PERIOD
1130
1131 /*******************************************************************************
1132 * PERI
1133 *******************************************************************************/
1134 /*******************************************************************************
1135 * PERI PCLK
1136 *******************************************************************************/
1137
1138 #define PERI_INSTANCE_COUNT (1U)
1139
1140 #ifndef PERI0_PCLK_GROUP_NR
1141 #define PERI0_PCLK_GROUP_NR PERI_PCLK_GROUP_NR
1142 #endif
1143
1144 #ifndef PERI1_PCLK_GROUP_NR
1145 #define PERI1_PCLK_GROUP_NR (0U)
1146 #endif
1147
1148
1149 #ifndef PERI_PCLK0_BASE
1150 #define PERI_PCLK0_BASE PERI_PCLK_BASE
1151 #endif
1152
1153 #ifndef PERI_PCLK1_BASE
1154 #define PERI_PCLK1_BASE 0U
1155 #endif
1156
1157 #if (PERI_INSTANCE_COUNT == 1U)
1158 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT
1159 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT
1160 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT
1161 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT
1162 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT
1163 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT
1164 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT
1165 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1166
1167
1168 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT
1169 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT
1170 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT
1171 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT
1172 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT
1173 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT
1174 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT
1175 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1176
1177
1178 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT
1179 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT
1180 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT
1181 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT
1182 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT
1183 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT
1184 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT
1185 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1186
1187 #define PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT
1188 #define PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT
1189 #define PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT
1190 #define PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT
1191 #define PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT
1192 #define PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT
1193 #define PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT PERI_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT
1194 #define PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1195
1196 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 0U
1197 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 0U
1198 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT 0U
1199 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT 0U
1200 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT 0U
1201 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT 0U
1202 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT 0U
1203 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT 0U
1204
1205 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 0U
1206 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 0U
1207 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT 0U
1208 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT 0U
1209 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT 0U
1210 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT 0U
1211 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT 0U
1212 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT 0U
1213
1214
1215 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT 0U
1216 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT 0U
1217 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT 0U
1218 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT 0U
1219 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT 0U
1220 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT 0U
1221 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT 0U
1222 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT 0U
1223
1224 #define PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 0U
1225 #define PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 0U
1226 #define PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT 0U
1227 #define PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT 0U
1228 #define PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT 0U
1229 #define PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT 0U
1230 #define PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT 0U
1231 #define PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT 0U
1232
1233 #endif
1234
1235 #define PERI_PCLK_PERI_NUM_Msk (0x000000FFU)
1236 #define PERI_PCLK_GR_NUM_Msk (0x0000FF00U)
1237 #define PERI_PCLK_GR_NUM_Pos (8U)
1238 #define PERI_PCLK_PERIPHERAL_GROUP_NUM (1UL << PERI_PCLK_GR_NUM_Pos)
1239 #define PERI_PCLK_INST_NUM_Msk (0x00FF0000U)
1240 #define PERI_PCLK_INST_NUM_Pos (16U)
1241
1242 #define PERI_PCLK_GR_NUM(instNum) (((instNum) == 0U)? PERI0_PCLK_GROUP_NR : PERI1_PCLK_GROUP_NR)
1243
1244 #define PERI_PCLK1_OFFSET (PERI_PCLK1_BASE - PERI_PCLK0_BASE)
1245 #define PERI_PCLK_REG_BASE(instNum) ((PERI_PCLK_Type*)(PERI_PCLK0_BASE + ((instNum) * PERI_PCLK1_OFFSET)))
1246
1247 #define PERI_DIV_8_CTL(instNum, grNum, divNum) ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_8_CTL[divNum]
1248 #define PERI_DIV_16_CTL(instNum, grNum, divNum) ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_CTL[divNum]
1249 #define PERI_DIV_16_5_CTL(instNum, grNum, divNum) ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_16_5_CTL[divNum]
1250 #define PERI_DIV_24_5_CTL(instNum, grNum, divNum) ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_24_5_CTL[divNum]
1251 #define PERI_CLOCK_CTL(instNum, grNum, periNum) ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL[periNum]
1252 #define PERI_DIV_CMD(instNum, grNum) ((PERI_PCLK_GR_Type*) &PERI_PCLK_REG_BASE(instNum)->GR[grNum])->DIV_CMD
1253
1254 #define PERI_PCLK_GR_DIV_8_NR(instNum, grNum) (((instNum) == 0U) ? \
1255 (((grNum) <= 3U) ? \
1256 ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) | \
1257 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U) | \
1258 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U) | \
1259 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1260 : \
1261 ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) | \
1262 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U) | \
1263 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U) | \
1264 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1265 : \
1266 (((grNum) <= 3U) ? \
1267 ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT) | \
1268 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT) << 8U) | \
1269 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_8_VECT) << 16U) | \
1270 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_8_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1271 : \
1272 ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_8_VECT)) | \
1273 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_8_VECT) << 8U) | \
1274 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_8_VECT) << 16U) | \
1275 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_8_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1276
1277 #define PERI_PCLK_GR_DIV_16_NR(instNum, grNum) (((instNum) == 0U) ? \
1278 (((grNum) <= 3U) ? \
1279 ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) | \
1280 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U) | \
1281 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U) | \
1282 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1283 : \
1284 ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) | \
1285 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U) | \
1286 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U) | \
1287 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1288 : \
1289 (((grNum) <= 3U) ? \
1290 ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) | \
1291 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT) << 8U) | \
1292 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_VECT) << 16U) | \
1293 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1294 : \
1295 ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_VECT)) | \
1296 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_VECT) << 8U) | \
1297 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_VECT) << 16U) | \
1298 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1299
1300 #define PERI_PCLK_GR_DIV_16_5_NR(instNum, grNum) (((instNum) == 0U) ? \
1301 (((grNum) <= 3U) ? \
1302 ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) | \
1303 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U) | \
1304 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U) | \
1305 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1306 : \
1307 ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) | \
1308 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U) | \
1309 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U) | \
1310 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1311 : \
1312 (((grNum) <= 3U) ? \
1313 ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_5_VECT) | \
1314 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_5_VECT) << 8U) | \
1315 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_16_5_VECT) << 16U) | \
1316 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_16_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1317 : \
1318 ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_16_5_VECT)) | \
1319 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_16_5_VECT) << 8U) | \
1320 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_16_5_VECT) << 16U) | \
1321 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_16_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1322
1323 #define PERI_PCLK_GR_DIV_24_5_NR(instNum, grNum) (((instNum) == 0U) ? \
1324 (((grNum) <= 3U) ? \
1325 ((uint32_t)(((((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT) | \
1326 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U) | \
1327 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U) | \
1328 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1329 : \
1330 ((uint32_t)(((((PERI0_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) | \
1331 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U) | \
1332 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U) | \
1333 (((uint32_t)PERI0_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))) \
1334 : \
1335 (((grNum) <= 3U) ? \
1336 ((uint32_t)(((((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT) | \
1337 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT) << 8U) | \
1338 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR2_GR_DIV_24_5_VECT) << 16U) | \
1339 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR3_GR_DIV_24_5_VECT) << 24U)) >> ((grNum) * 8UL)) & 0xFFUL)) \
1340 : \
1341 ((uint32_t)(((((PERI1_PERI_PCLK_PCLK_GROUP_NR4_GR_DIV_24_5_VECT)) | \
1342 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR5_GR_DIV_24_5_VECT) << 8U) | \
1343 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR6_GR_DIV_24_5_VECT) << 16U) | \
1344 (((uint32_t)PERI1_PERI_PCLK_PCLK_GROUP_NR7_GR_DIV_24_5_VECT) << 24U)) >> (((uint32_t)(grNum) - 4UL) * 8UL)) & 0xFFUL))))
1345
1346 /* PERI_PCLK_GR.DIV_CMD */
1347 #define CY_PERI_DIV_CMD_DIV_SEL_Pos PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1348 #define CY_PERI_DIV_CMD_DIV_SEL_Msk PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1349 #define CY_PERI_DIV_CMD_TYPE_SEL_Pos PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1350 #define CY_PERI_DIV_CMD_TYPE_SEL_Msk PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1351 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Pos PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1352 #define CY_PERI_DIV_CMD_PA_DIV_SEL_Msk PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1353 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Pos PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1354 #define CY_PERI_DIV_CMD_PA_TYPE_SEL_Msk PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1355 #define CY_PERI_DIV_CMD_DISABLE_Pos PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1356 #define CY_PERI_DIV_CMD_DISABLE_Msk PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1357 #define CY_PERI_DIV_CMD_ENABLE_Pos PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1358 #define CY_PERI_DIV_CMD_ENABLE_Msk PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1359
1360
1361 #define PERI_DIV_CMD_DIV_SEL_Pos PERI_PCLK_GR_DIV_CMD_DIV_SEL_Pos
1362 #define PERI_DIV_CMD_DIV_SEL_Msk PERI_PCLK_GR_DIV_CMD_DIV_SEL_Msk
1363 #define PERI_DIV_CMD_TYPE_SEL_Pos PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Pos
1364 #define PERI_DIV_CMD_TYPE_SEL_Msk PERI_PCLK_GR_DIV_CMD_TYPE_SEL_Msk
1365 #define PERI_DIV_CMD_PA_DIV_SEL_Pos PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Pos
1366 #define PERI_DIV_CMD_PA_DIV_SEL_Msk PERI_PCLK_GR_DIV_CMD_PA_DIV_SEL_Msk
1367 #define PERI_DIV_CMD_PA_TYPE_SEL_Pos PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Pos
1368 #define PERI_DIV_CMD_PA_TYPE_SEL_Msk PERI_PCLK_GR_DIV_CMD_PA_TYPE_SEL_Msk
1369 #define PERI_DIV_CMD_DISABLE_Pos PERI_PCLK_GR_DIV_CMD_DISABLE_Pos
1370 #define PERI_DIV_CMD_DISABLE_Msk PERI_PCLK_GR_DIV_CMD_DISABLE_Msk
1371 #define PERI_DIV_CMD_ENABLE_Pos PERI_PCLK_GR_DIV_CMD_ENABLE_Pos
1372 #define PERI_DIV_CMD_ENABLE_Msk PERI_PCLK_GR_DIV_CMD_ENABLE_Msk
1373
1374 /* PERI_PCLK_GR.CLOCK_CTL */
1375 #define CY_PERI_CLOCK_CTL_DIV_SEL_Pos PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Pos
1376 #define CY_PERI_CLOCK_CTL_DIV_SEL_Msk PERI_PCLK_GR_CLOCK_CTL_DIV_SEL_Msk
1377 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Pos PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Pos
1378 #define CY_PERI_CLOCK_CTL_TYPE_SEL_Msk PERI_PCLK_GR_CLOCK_CTL_TYPE_SEL_Msk
1379 /* PERI.DIV_8_CTL */
1380 #define PERI_DIV_8_CTL_EN_Pos PERI_PCLK_GR_DIV_8_CTL_EN_Pos
1381 #define PERI_DIV_8_CTL_EN_Msk PERI_PCLK_GR_DIV_8_CTL_EN_Msk
1382 #define PERI_DIV_8_CTL_INT8_DIV_Pos PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Pos
1383 #define PERI_DIV_8_CTL_INT8_DIV_Msk PERI_PCLK_GR_DIV_8_CTL_INT8_DIV_Msk
1384 /* PERI.DIV_16_CTL */
1385 #define PERI_DIV_16_CTL_EN_Pos PERI_PCLK_GR_DIV_16_CTL_EN_Pos
1386 #define PERI_DIV_16_CTL_EN_Msk PERI_PCLK_GR_DIV_16_CTL_EN_Msk
1387 #define PERI_DIV_16_CTL_INT16_DIV_Pos PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Pos
1388 #define PERI_DIV_16_CTL_INT16_DIV_Msk PERI_PCLK_GR_DIV_16_CTL_INT16_DIV_Msk
1389 /* PERI.DIV_16_5_CTL */
1390 #define PERI_DIV_16_5_CTL_EN_Pos PERI_PCLK_GR_DIV_16_5_CTL_EN_Pos
1391 #define PERI_DIV_16_5_CTL_EN_Msk PERI_PCLK_GR_DIV_16_5_CTL_EN_Msk
1392 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Pos
1393 #define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk PERI_PCLK_GR_DIV_16_5_CTL_FRAC5_DIV_Msk
1394 #define PERI_DIV_16_5_CTL_INT16_DIV_Pos PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Pos
1395 #define PERI_DIV_16_5_CTL_INT16_DIV_Msk PERI_PCLK_GR_DIV_16_5_CTL_INT16_DIV_Msk
1396 /* PERI.DIV_24_5_CTL */
1397 #define PERI_DIV_24_5_CTL_EN_Pos PERI_PCLK_GR_DIV_24_5_CTL_EN_Pos
1398 #define PERI_DIV_24_5_CTL_EN_Msk PERI_PCLK_GR_DIV_24_5_CTL_EN_Msk
1399 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Pos
1400 #define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk PERI_PCLK_GR_DIV_24_5_CTL_FRAC5_DIV_Msk
1401 #define PERI_DIV_24_5_CTL_INT24_DIV_Pos PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Pos
1402 #define PERI_DIV_24_5_CTL_INT24_DIV_Msk PERI_PCLK_GR_DIV_24_5_CTL_INT24_DIV_Msk
1403
1404 /*******************************************************************************
1405 * PERI-GROUP
1406 *******************************************************************************/
1407 #if defined (CY_DEVICE_BOY2)
1408 #define CY_PERI_GROUP_NR 6
1409 #else
1410 #define CY_PERI_GROUP_NR 4
1411 #define CY_PERI_BLESS_GROUP_NR 3
1412 #endif /* CY_DEVICE_BOY2 */
1413
1414 #ifndef PERI0_BASE
1415 #define PERI0_BASE PERI_BASE
1416 #endif
1417
1418 #ifndef PERI1_BASE
1419 #define PERI1_BASE 0U
1420 #endif
1421
1422
1423 #define PERI_GR_OFFSET (PERI1_BASE - PERI0_BASE)
1424 #define PERI_GR_REG_BASE(instNum) ((PERI_Type*)(PERI0_BASE + ((instNum) * PERI_GR_OFFSET)))
1425
1426 #define PERI_GR_INST_NUM_Msk (0x0000FF00U)
1427 #define PERI_GR_INST_NUM_Pos (8U)
1428
1429
1430 #define PERI_GR_CLOCK_CTL(instNum, grNum) ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->CLOCK_CTL
1431 #define PERI_GR_SL_CTL(instNum, grNum) ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL
1432 #define PERI_GR_SL_CTL2(instNum, grNum) ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL2
1433 #define PERI_GR_SL_CTL3(instNum, grNum) ((PERI_GR_Type*) &PERI_GR_REG_BASE(instNum)->GR[grNum])->SL_CTL3
1434
1435 /*******************************************************************************
1436 * PERI-TR
1437 *******************************************************************************/
1438
1439 #define PERI_TR_CMD (((PERI_Type*) (PERI_BASE))->TR_CMD)
1440 #define PERI_TR_GR_TR_CTL(group, trCtl) (*(volatile uint32_t*) ((uint32_t)PERI_BASE+ (uint32_t)offsetof(PERI_Type,TR_GR) + \
1441 ((group) * (uint32_t)sizeof(PERI_TR_GR_Type)) + \
1442 ((trCtl) * (uint32_t)sizeof(uint32_t))))
1443
1444 #if defined (CY_IP_MXSPERI)
1445 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1446 #define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1447 #define CY_PERI_TR_CTL_SEL_Msk PERI_TR_GR_TR_CTL_TR_SEL_Msk
1448 #define CY_PERI_TR_CTL_SEL_Pos PERI_TR_GR_TR_CTL_TR_SEL_Pos
1449 #define PERI_V2_TR_CMD_OUT_SEL_Msk PERI_TR_CMD_OUT_SEL_Msk
1450 #define PERI_V2_TR_CMD_OUT_SEL_Pos PERI_TR_CMD_OUT_SEL_Pos
1451 #define PERI_V2_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1452 #define PERI_V2_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1453 #define CY_PERI_TR_CMD_GROUP_SEL_Msk PERI_TR_CMD_GROUP_SEL_Msk
1454 #define CY_PERI_TR_CMD_GROUP_SEL_Pos PERI_TR_CMD_GROUP_SEL_Pos
1455 #define CY_PERI_TR_CTL_SEL PERI_TR_GR_TR_CTL_TR_SEL
1456 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk PERI_TR_GR_TR_CTL_TR_INV_Msk
1457 #define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos PERI_TR_GR_TR_CTL_TR_INV_Pos
1458 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk PERI_TR_GR_TR_CTL_TR_EDGE_Msk
1459 #define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos PERI_TR_GR_TR_CTL_TR_EDGE_Pos
1460 #define PERI_V2_TR_CMD_TR_EDGE_Msk PERI_TR_CMD_TR_EDGE_Msk
1461 #define PERI_V2_TR_CMD_TR_EDGE_Pos PERI_TR_CMD_TR_EDGE_Pos
1462 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk PERI_TR_1TO1_GR_TR_CTL_TR_INV_Msk
1463 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos PERI_TR_1TO1_GR_TR_CTL_TR_INV_Pos
1464 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Msk
1465 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos PERI_TR_1TO1_GR_TR_CTL_TR_EDGE_Pos
1466 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Msk
1467 #define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos PERI_TR_1TO1_GR_TR_CTL_TR_SEL_Pos
1468 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Msk
1469 #define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos PERI_TR_GR_TR_CTL_DBG_FREEZE_EN_Pos
1470 #define CY_PERI_V1 0U
1471 #define PERI_TR_CMD_COUNT_Pos 0UL
1472 #define PERI_TR_CMD_COUNT_Msk 0UL
1473 #endif /* CY_IP_MXSPERI */
1474
1475 /* CLK_HF* to PERI PCLK Group Mapping */
1476 #define PERI0_PCLK_GR_NUM_0_CLK_HF_NUM (0U)
1477 #define PERI0_PCLK_GR_NUM_1_CLK_HF_NUM (1U)
1478 #define PERI0_PCLK_GR_NUM_2_CLK_HF_NUM (0U)
1479 #define PERI0_PCLK_GR_NUM_3_CLK_HF_NUM (1U)
1480 #define PERI0_PCLK_GR_NUM_4_CLK_HF_NUM (2U)
1481 #define PERI0_PCLK_GR_NUM_5_CLK_HF_NUM (3U)
1482 #if defined (CY_DEVICE_BOY2)
1483 #define PERI0_PCLK_GR_NUM_6_CLK_HF_NUM (4U)
1484 #else
1485 #define PERI0_PCLK_GR_NUM_6_CLK_HF_NUM (1U)
1486 #endif
1487
1488
1489 #if defined (CY_IP_MXS40SSRSS)
1490 #define CY_SYSPM_BOOTROM_ENTRYPOINT_ADDR ((uint32_t)(&BACKUP_BREG_SET1[0])) /* Boot ROM will check this address for locating the entry point after Warm Boot */
1491 #define CY_SYSPM_BOOTROM_DSRAM_DBG_ENABLE_MASK 0x00000001U
1492 #endif
1493 #if defined (CY_DEVICE_CYW20829)
1494 #define ENABLE_MEM_VOLTAGE_TRIMS
1495 #endif
1496
1497
1498 /*******************************************************************************
1499 * MXCM33
1500 *******************************************************************************/
1501 #define MXCM33_CM33_NMI_CTL(nmi) (((volatile uint32_t *) (MXCM33->CM33_NMI_CTL))[(nmi)])
1502
1503 /*******************************************************************************
1504 * MCWDT
1505 *******************************************************************************/
1506
1507 #define MCWDT_CNTLOW(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CNTLOW)
1508 #define MCWDT_CNTHIGH(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CNTHIGH)
1509 #define MCWDT_MATCH(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_MATCH)
1510 #define MCWDT_CONFIG(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CONFIG)
1511 #define MCWDT_CTL(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_CTL)
1512 #define MCWDT_INTR(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR)
1513 #define MCWDT_INTR_SET(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_SET)
1514 #define MCWDT_INTR_MASK(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_MASK)
1515 #define MCWDT_INTR_MASKED(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_INTR_MASKED)
1516 #define MCWDT_LOCK(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_LOCK)
1517 #define MCWDT_LOWER_LIMIT(base) (((MCWDT_STRUCT_Type *)(base))->MCWDT_LOWER_LIMIT)
1518
1519 #if defined (CY_DEVICE_BOY2)
1520 /*******************************************************************************
1521 * SFLASH
1522 *******************************************************************************/
1523 #define SFLASH_CPUSS_TRIM_ROM_CTL_LP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_LP)
1524 #define SFLASH_CPUSS_TRIM_RAM_CTL_LP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_LP)
1525 #define SFLASH_CPUSS_TRIM_ROM_CTL_ULP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_ULP)
1526 #define SFLASH_CPUSS_TRIM_RAM_CTL_ULP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_ULP)
1527 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_LP)
1528 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_LP)
1529 #define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_ROM_CTL_HALF_ULP)
1530 #define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP (((SFLASH_Type *) SFLASH)->CPUSS_TRIM_RAM_CTL_HALF_ULP)
1531
1532 #define SFLASH_LDO_0P9V_TRIM (((SFLASH_Type *) SFLASH)->LDO_0P9V_TRIM)
1533 #define SFLASH_LDO_1P0V_TRIM (((SFLASH_Type *) SFLASH)->LDO_1P0V_TRIM)
1534 #define SFLASH_LDO_1P1V_TRIM (((SFLASH_Type *) SFLASH)->LDO_1P1V_TRIM)
1535 #define SFLASH_LDO_1P2V_TRIM (((SFLASH_Type *) SFLASH)->LDO_1P2V_TRIM)
1536 #define SFLASH_PWR_TRIM_WAKE_CTL (((SFLASH_Type *) SFLASH)->PWR_TRIM_WAKE_CTL)
1537
1538 #define SFLASH_DIE_YEAR (((SFLASH_Type *) SFLASH)->DIE_YEAR)
1539 #define SFLASH_DIE_MINOR (((SFLASH_Type *) SFLASH)->DIE_MINOR)
1540 #define SFLASH_DIE_SORT (((SFLASH_Type *) SFLASH)->DIE_SORT)
1541 #define SFLASH_DIE_Y (((SFLASH_Type *) SFLASH)->DIE_Y)
1542 #define SFLASH_DIE_X (((SFLASH_Type *) SFLASH)->DIE_X)
1543 #define SFLASH_DIE_WAFER (((SFLASH_Type *) SFLASH)->DIE_WAFER)
1544 #define SFLASH_DIE_LOT(val) (((SFLASH_Type *) SFLASH)->DIE_LOT[(val)])
1545
1546 #define SFLASH_SAR_CALOFFST_0_N40C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_0_N40C)
1547 #define SFLASH_SAR_CALOFFST_1_N40C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_1_N40C)
1548 #define SFLASH_SAR_CALOFFST_2_N40C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_2_N40C)
1549 #define SFLASH_SAR_CALOFFST_3_N40C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_3_N40C)
1550 #define SFLASH_SAR_CALOFFST_0_125C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_0_125C)
1551 #define SFLASH_SAR_CALOFFST_1_125C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_1_125C)
1552 #define SFLASH_SAR_CALOFFST_2_125C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_2_125C)
1553 #define SFLASH_SAR_CALOFFST_3_125C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_3_125C)
1554 #define SFLASH_SAR_CALOFFST_0_25C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_0_25C)
1555 #define SFLASH_SAR_CALOFFST_1_25C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_1_25C)
1556 #define SFLASH_SAR_CALOFFST_2_25C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_2_25C)
1557 #define SFLASH_SAR_CALOFFST_3_25C (((SFLASH_Type *) SFLASH)->SAR_CALOFFST_3_25C)
1558 #define SFLASH_SAR_CALREFPT (((SFLASH_Type *) SFLASH)->SAR_CALREFPT)
1559 #define SFLASH_SAR_TEMP_COEF_A (((SFLASH_Type *) SFLASH)->SAR_TEMP_COEF_A)
1560 #define SFLASH_SAR_TEMP_COEF_B (((SFLASH_Type *) SFLASH)->SAR_TEMP_COEF_B)
1561 #define SFLASH_SAR_TEMP_COEF_C (((SFLASH_Type *) SFLASH)->SAR_TEMP_COEF_C)
1562 #define SFLASH_SAR_TEMP_COEF_D (((SFLASH_Type *) SFLASH)->SAR_TEMP_COEF_D)
1563 #define SFLASH_SAR_CAL_LIN_TABLE(val) (((SFLASH_Type *) SFLASH)->SAR_CAL_LIN_TABLE[(val)])
1564 #define SFLASH_SAR_CALGAINC (((SFLASH_Type *) SFLASH)->SAR_CALGAINC)
1565 #define SFLASH_SAR_CALGAINF (((SFLASH_Type *) SFLASH)->SAR_CALGAINF)
1566 #define SFLASH_SAR_INFRA_TRIM_TABLE (((SFLASH_Type *) SFLASH)->SAR_INFRA_TRIM_TABLE)
1567 #endif
1568
1569 /*******************************************************************************
1570 * CPUSS
1571 *******************************************************************************/
1572 #define CPUSS_SYSTICK_NS_CTL (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_NS_CTL)
1573 #define CPUSS_SYSTICK_S_CTL (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_S_CTL)
1574 #if defined (CY_DEVICE_CYW20829)
1575 #define CPUSS_TRIM_RAM_CTL (((CPUSS_Type*) CPUSS_BASE)->TRIM_RAM_CTL)
1576 #define CPUSS_TRIM_ROM_CTL (((CPUSS_Type*) CPUSS_BASE)->TRIM_ROM_CTL)
1577 #endif
1578 #define CPUSS_PRODUCT_ID (((CPUSS_Type*) CPUSS_BASE)->PRODUCT_ID)
1579
1580
1581 /* ARM core registers */
1582 #define SYSTICK_CTRL (((SysTick_Type *)SysTick)->CTRL)
1583 #define SYSTICK_LOAD (((SysTick_Type *)SysTick)->LOAD)
1584 #define SYSTICK_VAL (((SysTick_Type *)SysTick)->VAL)
1585 #define SYSTICK_NS_CTRL (((SysTick_Type *)SysTick_NS)->CTRL)
1586 #define SYSTICK_NS_LOAD (((SysTick_Type *)SysTick_NS)->LOAD)
1587 #define SYSTICK_NS_VAL (((SysTick_Type *)SysTick_NS)->VAL)
1588 #define SCB_SCR (((SCB_Type *)SCB)->SCR)
1589
1590 #if defined (CY_DEVICE_CYW20829)
1591 #define CY_UNIQE_DEVICE_ID_PRESENT_SFLASH 0u
1592 #else
1593 #define CY_UNIQE_DEVICE_ID_PRESENT_SFLASH 1u
1594 #endif
1595
1596
1597 /*******************************************************************************
1598 * LPCOMP
1599 *******************************************************************************/
1600
1601 #define LPCOMP_CMP0_CTRL(base) (((LPCOMP_Type *)(base))->CMP0_CTRL)
1602 #define LPCOMP_CMP1_CTRL(base) (((LPCOMP_Type *)(base))->CMP1_CTRL)
1603 #define LPCOMP_CMP0_SW_CLEAR(base) (((LPCOMP_Type *)(base))->CMP0_SW_CLEAR)
1604 #define LPCOMP_CMP1_SW_CLEAR(base) (((LPCOMP_Type *)(base))->CMP1_SW_CLEAR)
1605 #define LPCOMP_CMP0_SW(base) (((LPCOMP_Type *)(base))->CMP0_SW)
1606 #define LPCOMP_CMP1_SW(base) (((LPCOMP_Type *)(base))->CMP1_SW)
1607 #define LPCOMP_STATUS(base) (((LPCOMP_Type *)(base))->STATUS)
1608 #define LPCOMP_CONFIG(base) (((LPCOMP_Type *)(base))->CONFIG)
1609 #define LPCOMP_INTR(base) (((LPCOMP_Type *)(base))->INTR)
1610 #define LPCOMP_INTR_SET(base) (((LPCOMP_Type *)(base))->INTR_SET)
1611 #define LPCOMP_INTR_MASK(base) (((LPCOMP_Type *)(base))->INTR_MASK)
1612 #define LPCOMP_INTR_MASKED(base) (((LPCOMP_Type *)(base))->INTR_MASKED)
1613
1614
1615 /*******************************************************************************
1616 * TCPWM
1617 *******************************************************************************/
1618
1619 #if defined CY_IP_MXS40TCPWM
1620 /* CY_IP_MXS40TCPWM is nothing but the CY_IP_MXTCPWM version 3. In BOY-II it is called CY_IP_MXS40TCPWM */
1621 #define CY_IP_MXTCPWM 1u
1622 #define CY_IP_MXTCPWM_VERSION 3u
1623 #endif /* defined CY_IP_MXS40TCPWM */
1624
1625 #define TCPWM_CTRL_SET(base) (((TCPWM_Type *)(base))->CTRL_SET)
1626 #define TCPWM_CTRL_CLR(base) (((TCPWM_Type *)(base))->CTRL_CLR)
1627 #define TCPWM_CMD_START(base) (((TCPWM_Type *)(base))->CMD_START)
1628 #define TCPWM_CMD_RELOAD(base) (((TCPWM_Type *)(base))->CMD_RELOAD)
1629 #define TCPWM_CMD_STOP(base) (((TCPWM_Type *)(base))->CMD_STOP)
1630 #define TCPWM_CMD_CAPTURE(base) (((TCPWM_Type *)(base))->CMD_CAPTURE)
1631
1632 #define TCPWM_CNT_CTRL(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].CTRL)
1633 #define TCPWM_CNT_CC(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].CC)
1634 #define TCPWM_CNT_CC_BUFF(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].CC_BUFF)
1635 #define TCPWM_CNT_COUNTER(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].COUNTER)
1636 #define TCPWM_CNT_PERIOD(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD)
1637 #define TCPWM_CNT_PERIOD_BUFF(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].PERIOD_BUFF)
1638 #define TCPWM_CNT_STATUS(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].STATUS)
1639 #define TCPWM_CNT_INTR(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].INTR)
1640 #define TCPWM_CNT_INTR_SET(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].INTR_SET)
1641 #define TCPWM_CNT_INTR_MASK(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASK)
1642 #define TCPWM_CNT_INTR_MASKED(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].INTR_MASKED)
1643 #define TCPWM_CNT_TR_CTRL0(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL0)
1644 #define TCPWM_CNT_TR_CTRL1(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL1)
1645 #define TCPWM_CNT_TR_CTRL2(base, cntNum) (((TCPWM_Type *)(base))->CNT[cntNum].TR_CTRL2)
1646
1647 #if defined (CY_DEVICE_CYW20829)
1648 #define TCPWM_GRP_CC1_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT | TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT << 1)
1649 #define TCPWM_GRP_AMC_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT | TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT << 1)
1650 #define TCPWM_GRP_SMC_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT | TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT << 1)
1651 #else
1652 #define TCPWM_GRP_CC1_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT | TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT << 1 | TCPWM_GRP_NR2_CNT_GRP_CC1_PRESENT << 2)
1653 #define TCPWM_GRP_AMC_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT | TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT << 1 | TCPWM_GRP_NR2_CNT_GRP_AMC_PRESENT << 2)
1654 #define TCPWM_GRP_SMC_PRESENT_STATUS (TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT | TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT << 1 | TCPWM_GRP_NR2_CNT_GRP_SMC_PRESENT << 2)
1655 #endif
1656
1657 #define TCPWM_GRP_CC1(base, grp) ((bool)((TCPWM_GRP_CC1_PRESENT_STATUS >> (grp)) & 0x01U))
1658 #define TCPWM_GRP_AMC(base, grp) ((bool)((TCPWM_GRP_AMC_PRESENT_STATUS >> (grp)) & 0x01U))
1659 #define TCPWM_GRP_SMC(base, grp) ((bool)((TCPWM_GRP_SMC_PRESENT_STATUS >> (grp)) & 0x01U))
1660
1661 #define TCPWM_GRP_CNT_GET_GRP(cntNum) ((cntNum )/ 256U)
1662
1663 #define TCPWM_GRP_CNT_CTRL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CTRL)
1664 #define TCPWM_GRP_CNT_STATUS(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].STATUS)
1665 #define TCPWM_GRP_CNT_COUNTER(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].COUNTER)
1666 #define TCPWM_GRP_CNT_CC0(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0)
1667 #define TCPWM_GRP_CNT_CC0_BUFF(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC0_BUFF)
1668 #define TCPWM_GRP_CNT_CC1(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1)
1669 #define TCPWM_GRP_CNT_CC1_BUFF(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].CC1_BUFF)
1670 #define TCPWM_GRP_CNT_PERIOD(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD)
1671 #define TCPWM_GRP_CNT_PERIOD_BUFF(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PERIOD_BUFF)
1672 #define TCPWM_GRP_CNT_LINE_SEL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL)
1673 #define TCPWM_GRP_CNT_LINE_SEL_BUFF(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LINE_SEL_BUFF)
1674 #define TCPWM_GRP_CNT_DT(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT)
1675 #define TCPWM_GRP_CNT_TR_CMD(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_CMD)
1676 #define TCPWM_GRP_CNT_TR_IN_SEL0(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL0)
1677 #define TCPWM_GRP_CNT_TR_IN_SEL1(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_SEL1)
1678 #define TCPWM_GRP_CNT_TR_IN_EDGE_SEL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_IN_EDGE_SEL)
1679 #define TCPWM_GRP_CNT_TR_PWM_CTRL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_PWM_CTRL)
1680 #define TCPWM_GRP_CNT_TR_OUT_SEL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].TR_OUT_SEL)
1681 #define TCPWM_GRP_CNT_INTR(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR)
1682 #define TCPWM_GRP_CNT_INTR_SET(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_SET)
1683 #define TCPWM_GRP_CNT_INTR_MASK(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASK)
1684 #define TCPWM_GRP_CNT_INTR_MASKED(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].INTR_MASKED)
1685
1686 #if (CY_IP_MXTCPWM_VERSION >= 2U)
1687 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Pos
1688 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC0_Msk
1689 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Pos
1690 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_CC1_Msk
1691 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos
1692 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk
1693 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Pos
1694 #define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk TCPWM_GRP_CNT_CTRL_AUTO_RELOAD_LINE_SEL_Msk
1695 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Pos
1696 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_UP_EN_Msk
1697 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Pos
1698 #define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC0_MATCH_DOWN_EN_Msk
1699 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Pos
1700 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_UP_EN_Msk
1701 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Pos
1702 #define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk TCPWM_GRP_CNT_CTRL_CC1_MATCH_DOWN_EN_Msk
1703 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Pos
1704 #define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_IMM_KILL_Msk
1705 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Pos
1706 #define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_STOP_ON_KILL_Msk
1707 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Pos
1708 #define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk TCPWM_GRP_CNT_CTRL_PWM_SYNC_KILL_Msk
1709 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Pos
1710 #define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk TCPWM_GRP_CNT_CTRL_PWM_DISABLE_MODE_Msk
1711 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Pos
1712 #define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk TCPWM_GRP_CNT_CTRL_UP_DOWN_MODE_Msk
1713 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos TCPWM_GRP_CNT_CTRL_ONE_SHOT_Pos
1714 #define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk TCPWM_GRP_CNT_CTRL_ONE_SHOT_Msk
1715 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Pos
1716 #define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk TCPWM_GRP_CNT_CTRL_QUAD_ENCODING_MODE_Msk
1717 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos TCPWM_GRP_CNT_CTRL_MODE_Pos
1718 #define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk TCPWM_GRP_CNT_CTRL_MODE_Msk
1719 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Pos
1720 #define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk TCPWM_GRP_CNT_CTRL_DBG_FREEZE_EN_Msk
1721 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos TCPWM_GRP_CNT_CTRL_ENABLED_Pos
1722 #define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk TCPWM_GRP_CNT_CTRL_ENABLED_Msk
1723 /* TCPWM_GRP_CNT.STATUS */
1724 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos TCPWM_GRP_CNT_STATUS_DOWN_Pos
1725 #define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk TCPWM_GRP_CNT_STATUS_DOWN_Msk
1726 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Pos
1727 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE0_Msk
1728 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos TCPWM_GRP_CNT_STATUS_TR_COUNT_Pos
1729 #define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk TCPWM_GRP_CNT_STATUS_TR_COUNT_Msk
1730 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos TCPWM_GRP_CNT_STATUS_TR_RELOAD_Pos
1731 #define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk TCPWM_GRP_CNT_STATUS_TR_RELOAD_Msk
1732 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos TCPWM_GRP_CNT_STATUS_TR_STOP_Pos
1733 #define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk TCPWM_GRP_CNT_STATUS_TR_STOP_Msk
1734 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos TCPWM_GRP_CNT_STATUS_TR_START_Pos
1735 #define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk TCPWM_GRP_CNT_STATUS_TR_START_Msk
1736 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Pos
1737 #define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk TCPWM_GRP_CNT_STATUS_TR_CAPTURE1_Msk
1738 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos TCPWM_GRP_CNT_STATUS_LINE_OUT_Pos
1739 #define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk TCPWM_GRP_CNT_STATUS_LINE_OUT_Msk
1740 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Pos
1741 #define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_STATUS_LINE_COMPL_OUT_Msk
1742 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos TCPWM_GRP_CNT_STATUS_RUNNING_Pos
1743 #define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk TCPWM_GRP_CNT_STATUS_RUNNING_Msk
1744 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos TCPWM_GRP_CNT_STATUS_DT_CNT_L_Pos
1745 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk TCPWM_GRP_CNT_STATUS_DT_CNT_L_Msk
1746 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos TCPWM_GRP_CNT_STATUS_DT_CNT_H_Pos
1747 #define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk TCPWM_GRP_CNT_STATUS_DT_CNT_H_Msk
1748 /* TCPWM_GRP_CNT.COUNTER */
1749 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos TCPWM_GRP_CNT_COUNTER_COUNTER_Pos
1750 #define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk TCPWM_GRP_CNT_COUNTER_COUNTER_Msk
1751 /* TCPWM_GRP_CNT.CC0 */
1752 #define TCPWM_GRP_CNT_V2_CC0_CC_Pos TCPWM_GRP_CNT_CC0_CC_Pos
1753 #define TCPWM_GRP_CNT_V2_CC0_CC_Msk TCPWM_GRP_CNT_CC0_CC_Msk
1754 /* TCPWM_GRP_CNT.CC0_BUFF */
1755 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos TCPWM_GRP_CNT_CC0_BUFF_CC_Pos
1756 #define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk TCPWM_GRP_CNT_CC0_BUFF_CC_Msk
1757 /* TCPWM_GRP_CNT.CC1 */
1758 #define TCPWM_GRP_CNT_V2_CC1_CC_Pos TCPWM_GRP_CNT_CC1_CC_Pos
1759 #define TCPWM_GRP_CNT_V2_CC1_CC_Msk TCPWM_GRP_CNT_CC1_CC_Msk
1760 /* TCPWM_GRP_CNT.CC1_BUFF */
1761 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos TCPWM_GRP_CNT_CC1_BUFF_CC_Pos
1762 #define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk TCPWM_GRP_CNT_CC1_BUFF_CC_Msk
1763 /* TCPWM_GRP_CNT.PERIOD */
1764 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos TCPWM_GRP_CNT_PERIOD_PERIOD_Pos
1765 #define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk TCPWM_GRP_CNT_PERIOD_PERIOD_Msk
1766 /* TCPWM_GRP_CNT.PERIOD_BUFF */
1767 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Pos
1768 #define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk TCPWM_GRP_CNT_PERIOD_BUFF_PERIOD_Msk
1769 /* TCPWM_GRP_CNT.LINE_SEL */
1770 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Pos
1771 #define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_OUT_SEL_Msk
1772 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Pos
1773 #define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_COMPL_OUT_SEL_Msk
1774 /* TCPWM_GRP_CNT.LINE_SEL_BUFF */
1775 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Pos
1776 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_OUT_SEL_Msk
1777 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos
1778 #define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk TCPWM_GRP_CNT_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk
1779 /* TCPWM_GRP_CNT.DT */
1780 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Pos
1781 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk TCPWM_GRP_CNT_DT_DT_LINE_OUT_L_Msk
1782 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Pos
1783 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk TCPWM_GRP_CNT_DT_DT_LINE_OUT_H_Msk
1784 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Pos
1785 #define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk TCPWM_GRP_CNT_DT_DT_LINE_COMPL_OUT_Msk
1786 /* TCPWM_GRP_CNT.TR_CMD */
1787 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Pos
1788 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk TCPWM_GRP_CNT_TR_CMD_CAPTURE0_Msk
1789 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos TCPWM_GRP_CNT_TR_CMD_RELOAD_Pos
1790 #define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk TCPWM_GRP_CNT_TR_CMD_RELOAD_Msk
1791 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos TCPWM_GRP_CNT_TR_CMD_STOP_Pos
1792 #define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk TCPWM_GRP_CNT_TR_CMD_STOP_Msk
1793 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos TCPWM_GRP_CNT_TR_CMD_START_Pos
1794 #define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk TCPWM_GRP_CNT_TR_CMD_START_Msk
1795 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Pos
1796 #define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk TCPWM_GRP_CNT_TR_CMD_CAPTURE1_Msk
1797 /* TCPWM_GRP_CNT.TR_IN_SEL0 */
1798 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Pos
1799 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_CAPTURE0_SEL_Msk
1800 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Pos
1801 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_COUNT_SEL_Msk
1802 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Pos
1803 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_RELOAD_SEL_Msk
1804 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Pos
1805 #define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL0_STOP_SEL_Msk
1806 /* TCPWM_GRP_CNT.TR_IN_SEL1 */
1807 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Pos
1808 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_START_SEL_Msk
1809 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Pos
1810 #define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk TCPWM_GRP_CNT_TR_IN_SEL1_CAPTURE1_SEL_Msk
1811 /* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */
1812 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos
1813 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk
1814 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Pos
1815 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_COUNT_EDGE_Msk
1816 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos
1817 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk
1818 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Pos
1819 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_STOP_EDGE_Msk
1820 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Pos
1821 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_START_EDGE_Msk
1822 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos
1823 #define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk TCPWM_GRP_CNT_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk
1824 /* TCPWM_GRP_CNT.TR_PWM_CTRL */
1825 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Pos
1826 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC0_MATCH_MODE_Msk
1827 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Pos
1828 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_OVERFLOW_MODE_Msk
1829 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Pos
1830 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_UNDERFLOW_MODE_Msk
1831 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Pos
1832 #define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk TCPWM_GRP_CNT_TR_PWM_CTRL_CC1_MATCH_MODE_Msk
1833 /* TCPWM_GRP_CNT.TR_OUT_SEL */
1834 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Pos
1835 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk TCPWM_GRP_CNT_TR_OUT_SEL_OUT0_Msk
1836 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Pos
1837 #define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk TCPWM_GRP_CNT_TR_OUT_SEL_OUT1_Msk
1838 /* TCPWM_GRP_CNT.INTR */
1839 #define TCPWM_GRP_CNT_V2_INTR_TC_Pos TCPWM_GRP_CNT_INTR_TC_Pos
1840 #define TCPWM_GRP_CNT_V2_INTR_TC_Msk TCPWM_GRP_CNT_INTR_TC_Msk
1841 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_CC0_MATCH_Pos
1842 #define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_CC0_MATCH_Msk
1843 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_CC1_MATCH_Pos
1844 #define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_CC1_MATCH_Msk
1845 /* TCPWM_GRP_CNT.INTR_SET */
1846 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos TCPWM_GRP_CNT_INTR_SET_TC_Pos
1847 #define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk TCPWM_GRP_CNT_INTR_SET_TC_Msk
1848 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Pos
1849 #define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC0_MATCH_Msk
1850 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Pos
1851 #define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_SET_CC1_MATCH_Msk
1852 /* TCPWM_GRP_CNT.INTR_MASK */
1853 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos TCPWM_GRP_CNT_INTR_MASK_TC_Pos
1854 #define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk TCPWM_GRP_CNT_INTR_MASK_TC_Msk
1855 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Pos
1856 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC0_MATCH_Msk
1857 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Pos
1858 #define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASK_CC1_MATCH_Msk
1859 /* TCPWM_GRP_CNT.INTR_MASKED */
1860 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos TCPWM_GRP_CNT_INTR_MASKED_TC_Pos
1861 #define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk TCPWM_GRP_CNT_INTR_MASKED_TC_Msk
1862 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Pos
1863 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC0_MATCH_Msk
1864 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Pos
1865 #define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk TCPWM_GRP_CNT_INTR_MASKED_CC1_MATCH_Msk
1866
1867 /* For backward compatibility, we set TCPWM_CNT_STATUS_RUNNING_Pos with TCPWM_GRP_CNT_V2_STATUS_RUNNING
1868 we need to define this for version 2 only. */
1869 #define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
1870 #endif
1871
1872 #if (CY_IP_MXTCPWM_VERSION >= 3U)
1873 #define TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED_Pos TCPWM_GRP_CNT_CTRL_SWAP_ENABLE_Pos
1874 #define TCPWM_GRP_CNT_V3_CTRL_SWAP_ENABLED_Msk TCPWM_GRP_CNT_CTRL_SWAP_ENABLE_Msk
1875 #define TCPWM_GRP_CNT_V3_CTRL_DITHEREN_Pos TCPWM_GRP_CNT_CTRL_DITHEREN_Pos
1876 #define TCPWM_GRP_CNT_V3_CTRL_DITHEREN_Msk TCPWM_GRP_CNT_CTRL_DITHEREN_Msk
1877
1878 #define TCPWM_GRP_CNT_V3_LFSR_PLFSR_Pos TCPWM_GRP_CNT_LFSR_PLFSR_Pos
1879 #define TCPWM_GRP_CNT_V3_LFSR_PLFSR_Msk TCPWM_GRP_CNT_LFSR_PLFSR_Msk
1880 #define TCPWM_GRP_CNT_V3_LFSR_DLFSR_Pos TCPWM_GRP_CNT_LFSR_DLFSR_Pos
1881 #define TCPWM_GRP_CNT_V3_LFSR_DLFSR_Msk TCPWM_GRP_CNT_LFSR_DLFSR_Msk
1882 #define TCPWM_GRP_CNT_V3_LFSR_LIMITER_Pos TCPWM_GRP_CNT_LFSR_LIMITER_Pos
1883 #define TCPWM_GRP_CNT_V3_LFSR_LIMITER_Msk TCPWM_GRP_CNT_LFSR_LIMITER_Msk
1884
1885 #define TCPWM_GRP_CNT_V3_ONE_GF_GF_DEPTH_Pos TCPWM_GRP_CNT_ONE_GF_GF_DEPTH_Pos
1886 #define TCPWM_GRP_CNT_V3_ONE_GF_GF_DEPTH_Msk TCPWM_GRP_CNT_ONE_GF_GF_DEPTH_Msk
1887 #define TCPWM_GRP_CNT_V3_ONE_GF_GFPS_DIV_Pos TCPWM_GRP_CNT_ONE_GF_GFPS_DIV_Pos
1888 #define TCPWM_GRP_CNT_V3_ONE_GF_GFPS_DIV_Msk TCPWM_GRP_CNT_ONE_GF_GFPS_DIV_Msk
1889
1890 #define GRP0_DITHERING TCPWM_GRP_NR0_CNT_GRP_DITHERING_PRESENT
1891 #define GRP1_DITHERING TCPWM_GRP_NR1_CNT_GRP_DITHERING_PRESENT
1892 #define GRP2_DITHERING TCPWM_GRP_NR2_CNT_GRP_DITHERING_PRESENT
1893 #define TCPWM_GRP_DITHERING_PRESENT(grp) (((grp) == 0U)? GRP0_DITHERING : (((grp) == 1U)? GRP1_DITHERING : GRP2_DITHERING))
1894
1895 #define GRP0_HRPWM TCPWM_GRP_NR0_CNT_GRP_HRPWM_PRESENT
1896 #define GRP1_HRPWM TCPWM_GRP_NR1_CNT_GRP_HRPWM_PRESENT
1897 #define GRP2_HRPWM TCPWM_GRP_NR2_CNT_GRP_HRPWM_PRESENT
1898 #define TCPWM_GRP_HRPWM_PRESENT(grp) (((grp) == 0U)? GRP0_HRPWM : (((grp) == 1U)? GRP1_HRPWM : GRP2_HRPWM))
1899
1900 #define GRP0_DATA_IN_CC_PRESENT TCPWM_GRP_NR0_CNT_GRP_DATA_IN_CC_PRESENT
1901 #define GRP1_DATA_IN_CC_PRESENT TCPWM_GRP_NR1_CNT_GRP_DATA_IN_CC_PRESENT
1902 #define GRP2_DATA_IN_CC_PRESENT TCPWM_GRP_NR2_CNT_GRP_DATA_IN_CC_PRESENT
1903 #define TCPWM_DATA_IN_CC_PRESENT(grp) (((grp) == 0U)? GRP0_DATA_IN_CC_PRESENT : (((grp) == 1U)? GRP1_DATA_IN_CC_PRESENT : GRP2_DATA_IN_CC_PRESENT))
1904
1905 #define TCPWM_GRP_CNT_LFSR(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].LFSR)
1906 #define TCPWM_GRP_CNT_ONE_GF(base, grp, cntNum, onetoone_gf) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].ONE_GF[onetoone_gf])
1907 #define TCPWM_GF_FOR_GROUP_TRIGGER(base, gfNum) (((TCPWM_Type *)(base))->TR_ALL_GF.ALL_GF[((gfNum) % 254U)])
1908 #define TCPWM_GRP_CNT_HRPWM_CTRL(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].HRPWM_CTRL)
1909 #define TCPWM_GRP_CNT_DT_BUFF(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].DT_BUFF)
1910 #define TCPWM_GRP_CNT_PS(base, grp, cntNum) (((TCPWM_Type *)(base))->GRP[grp].CNT[((cntNum) % 256U)].PS)
1911 /* MOTIF */
1912
1913 #define TCPWM_MOTIF_PCONF(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PCONF)
1914 #define TCPWM_MOTIF_PSUS(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PSUS)
1915 #define TCPWM_MOTIF_PRUNS(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PRUNS)
1916 #define TCPWM_MOTIF_PRUN(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PRUN)
1917 #define TCPWM_MOTIF_MDR(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MDR)
1918 #define TCPWM_MOTIF_HIST(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HIST)
1919 #define TCPWM_MOTIF_HMEC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HMEC)
1920 #define TCPWM_MOTIF_HALP(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HALP)
1921 #define TCPWM_MOTIF_HALPS(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HALPS)
1922 #define TCPWM_MOTIF_HOSC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->HOSC)
1923 #define TCPWM_MOTIF_MCM(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCM)
1924 #define TCPWM_MOTIF_MCSM(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM)
1925 #define TCPWM_MOTIF_MCMS(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMS)
1926 #define TCPWM_MOTIF_MCMC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMC)
1927 #define TCPWM_MOTIF_MCMF(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMF)
1928 #define TCPWM_MOTIF_MCPF(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCPF)
1929 #define TCPWM_MOTIF_MOSC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MOSC)
1930 #define TCPWM_MOTIF_QDC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->QDC)
1931 #define TCPWM_MOTIF_QOSC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->QOSC)
1932 #define TCPWM_MOTIF_MCMEC(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCMEC)
1933 #define TCPWM_MOTIF_PFLG(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PFLG)
1934 #define TCPWM_MOTIF_PFLGE(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PFLGE)
1935 #define TCPWM_MOTIF_SPFLG(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->SPFLG)
1936 #define TCPWM_MOTIF_RPFLG(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->RPFLG)
1937 #define TCPWM_MOTIF_MCSM1(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM1)
1938 #define TCPWM_MOTIF_MCSM2(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM2)
1939 #define TCPWM_MOTIF_MCSM3(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM3)
1940 #define TCPWM_MOTIF_MCSM4(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM4)
1941 #define TCPWM_MOTIF_MCSM5(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->MCSM5)
1942 #define TCPWM_MOTIF_CLUT(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->CLUT)
1943 #define TCPWM_MOTIF_SLUT(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->SLUT)
1944 #define TCPWM_MOTIF_PDBG(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PDBG)
1945 #define TCPWM_MOTIF_PLP0S(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PLP0S)
1946 #define TCPWM_MOTIF_PLP1S(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PLP1S)
1947 #define TCPWM_MOTIF_PLP2S(base) (((TCPWM_MOTIF_GRP_MOTIF_Type *)(base))->PLP2S)
1948
1949 #ifndef TCPWM_TR_ONE_CNT_NR
1950 #define TCPWM_TR_ONE_CNT_NR TCPWM_CNT_TR_ONE_CNT_NR
1951 #endif
1952 #endif /* CY_IP_MXTCPWM_VERSION >= 3U */
1953 /*******************************************************************************
1954 * TDM
1955 *******************************************************************************/
1956
1957 #define TDM_STRUCT_Type TDM_TDM_STRUCT_Type
1958 #define TDM_TX_STRUCT_Type TDM_TDM_STRUCT_TDM_TX_STRUCT_Type
1959 #define TDM_RX_STRUCT_Type TDM_TDM_STRUCT_TDM_RX_STRUCT_Type
1960 #define TDM_STRUCT0 TDM0_TDM_STRUCT0
1961 #define TDM_STRUCT1 TDM0_TDM_STRUCT1
1962 #define TDM_STRUCT0_TX TDM0_TDM_STRUCT0_TDM_TX_STRUCT
1963 #define TDM_STRUCT1_TX TDM0_TDM_STRUCT1_TDM_TX_STRUCT
1964 #define TDM_STRUCT0_RX TDM0_TDM_STRUCT0_TDM_RX_STRUCT
1965 #define TDM_STRUCT1_RX TDM0_TDM_STRUCT1_TDM_RX_STRUCT
1966 #define TDM_STRUCT_TX_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_CTL)
1967 #define TDM_STRUCT_TX_IF_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_IF_CTL)
1968 #define TDM_STRUCT_TX_CH_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_CH_CTL)
1969 #define TDM_STRUCT_TX_TEST_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_TEST_CTL)
1970 #define TDM_STRUCT_TX_ROUTE_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_ROUTE_CTL)
1971 #define TDM_STRUCT_TX_FIFO_CTL(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_CTL)
1972 #define TDM_STRUCT_TX_FIFO_STATUS(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_STATUS)
1973 #define TDM_STRUCT_TX_FIFO_WR(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->TX_FIFO_WR)
1974 #define TDM_STRUCT_TX_INTR_TX(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX)
1975 #define TDM_STRUCT_TX_INTR_TX_SET(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_SET)
1976 #define TDM_STRUCT_TX_INTR_TX_MASK(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_MASK)
1977 #define TDM_STRUCT_TX_INTR_TX_MASKED(base) (((TDM_TDM_STRUCT_TDM_TX_STRUCT_Type *)(base))->INTR_TX_MASKED)
1978
1979 #define TDM_STRUCT_RX_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_CTL)
1980 #define TDM_STRUCT_RX_IF_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_IF_CTL)
1981 #define TDM_STRUCT_RX_CH_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_CH_CTL)
1982 #define TDM_STRUCT_RX_TEST_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_TEST_CTL)
1983 #define TDM_STRUCT_RX_ROUTE_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_ROUTE_CTL)
1984 #define TDM_STRUCT_RX_FIFO_CTL(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_CTL)
1985 #define TDM_STRUCT_RX_FIFO_STATUS(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_STATUS)
1986 #define TDM_STRUCT_RX_FIFO_RD(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_RD)
1987 #define TDM_STRUCT_RX_FIFO_RD_SILENT(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->RX_FIFO_RD_SILENT)
1988 #define TDM_STRUCT_RX_INTR_RX(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX)
1989 #define TDM_STRUCT_RX_INTR_RX_SET(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_SET)
1990 #define TDM_STRUCT_RX_INTR_RX_MASK(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_MASK)
1991 #define TDM_STRUCT_RX_INTR_RX_MASKED(base) (((TDM_TDM_STRUCT_TDM_RX_STRUCT_Type *)(base))->INTR_RX_MASKED)
1992
1993
1994 /*******************************************************************************
1995 * PDM
1996 *******************************************************************************/
1997
1998 #define PDM_PCM_CTL(base) (((PDM_Type*)(base))->CTL)
1999 #define PDM_PCM_CTL_CLR(base) (((PDM_Type*)(base))->CTL_CLR)
2000 #define PDM_PCM_CTL_SET(base) (((PDM_Type*)(base))->CTL_SET)
2001 #define PDM_PCM_CLOCK_CTL(base) (((PDM_Type*)(base))->CLOCK_CTL)
2002 #define PDM_PCM_ROUTE_CTL(base) (((PDM_Type*)(base))->ROUTE_CTL)
2003 #define PDM_PCM_TEST_CTL(base) (((PDM_Type*)(base))->TEST_CTL)
2004 #define PDM_PCM_FIR0_COEFF0(base) (((PDM_Type*)(base))->FIR0_COEFF0)
2005 #define PDM_PCM_FIR0_COEFF1(base) (((PDM_Type*)(base))->FIR0_COEFF1)
2006 #define PDM_PCM_FIR0_COEFF2(base) (((PDM_Type*)(base))->FIR0_COEFF2)
2007 #define PDM_PCM_FIR0_COEFF3(base) (((PDM_Type*)(base))->FIR0_COEFF3)
2008 #define PDM_PCM_FIR0_COEFF4(base) (((PDM_Type*)(base))->FIR0_COEFF4)
2009 #define PDM_PCM_FIR0_COEFF5(base) (((PDM_Type*)(base))->FIR0_COEFF5)
2010 #define PDM_PCM_FIR0_COEFF6(base) (((PDM_Type*)(base))->FIR0_COEFF6)
2011 #define PDM_PCM_FIR0_COEFF7(base) (((PDM_Type*)(base))->FIR0_COEFF7)
2012
2013 #define PDM_PCM_FIR1_COEFF0(base) (((PDM_Type*)(base))->FIR1_COEFF0)
2014 #define PDM_PCM_FIR1_COEFF1(base) (((PDM_Type*)(base))->FIR1_COEFF1)
2015 #define PDM_PCM_FIR1_COEFF2(base) (((PDM_Type*)(base))->FIR1_COEFF2)
2016 #define PDM_PCM_FIR1_COEFF3(base) (((PDM_Type*)(base))->FIR1_COEFF3)
2017 #define PDM_PCM_FIR1_COEFF4(base) (((PDM_Type*)(base))->FIR1_COEFF4)
2018 #define PDM_PCM_FIR1_COEFF5(base) (((PDM_Type*)(base))->FIR1_COEFF5)
2019 #define PDM_PCM_FIR1_COEFF6(base) (((PDM_Type*)(base))->FIR1_COEFF6)
2020 #define PDM_PCM_FIR1_COEFF7(base) (((PDM_Type*)(base))->FIR1_COEFF7)
2021 #define PDM_PCM_FIR1_COEFF8(base) (((PDM_Type*)(base))->FIR1_COEFF8)
2022 #define PDM_PCM_FIR1_COEFF9(base) (((PDM_Type*)(base))->FIR1_COEFF9)
2023 #define PDM_PCM_FIR1_COEFF10(base) (((PDM_Type*)(base))->FIR1_COEFF10)
2024 #define PDM_PCM_FIR1_COEFF11(base) (((PDM_Type*)(base))->FIR1_COEFF11)
2025 #define PDM_PCM_FIR1_COEFF12(base) (((PDM_Type*)(base))->FIR1_COEFF12)
2026 #define PDM_PCM_FIR1_COEFF13(base) (((PDM_Type*)(base))->FIR1_COEFF13)
2027
2028
2029 #define PDM_PCM_CH_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].CTL)
2030 #define PDM_PCM_CH_IF_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].IF_CTL)
2031 #define PDM_PCM_CH_CIC_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].CIC_CTL)
2032 #define PDM_PCM_CH_FIR0_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].FIR0_CTL)
2033 #define PDM_PCM_CH_FIR1_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].FIR1_CTL)
2034 #define PDM_PCM_CH_DC_BLOCK_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].DC_BLOCK_CTL)
2035 #define PDM_PCM_INTR_RX_MASK(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX_MASK)
2036 #define PDM_PCM_INTR_RX_MASKED(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX_MASKED)
2037 #define PDM_PCM_INTR_RX(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX)
2038 #define PDM_PCM_INTR_RX_SET(base, chnum) (((PDM_Type*)(base))->CH[chnum].INTR_RX_SET)
2039 #define PDM_PCM_RX_FIFO_STATUS(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_STATUS)
2040 #define PDM_PCM_RX_FIFO_CTL(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_CTL)
2041 #define PDM_PCM_RX_FIFO_RD(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_RD)
2042 #define PDM_PCM_RX_FIFO_RD_SILENT(base, chnum) (((PDM_Type*)(base))->CH[chnum].RX_FIFO_RD_SILENT)
2043
2044
2045 /*******************************************************************************
2046 * BACKUP
2047 *******************************************************************************/
2048
2049 #if defined (CY_IP_MXS28SRSS)
2050 #define BACKUP_RTC_RW (((BACKUP_Type *) BACKUP)->RTC_RW)
2051 #define BACKUP_CAL_CTL (((BACKUP_Type *) BACKUP)->CAL_CTL)
2052 #define BACKUP_STATUS (((BACKUP_Type *) BACKUP)->STATUS)
2053 #define BACKUP_RTC_TIME (((BACKUP_Type *) BACKUP)->RTC_TIME)
2054 #define BACKUP_RTC_DATE (((BACKUP_Type *) BACKUP)->RTC_DATE)
2055 #define BACKUP_ALM1_TIME (((BACKUP_Type *) BACKUP)->ALM1_TIME)
2056 #define BACKUP_ALM1_DATE (((BACKUP_Type *) BACKUP)->ALM1_DATE)
2057 #define BACKUP_ALM2_TIME (((BACKUP_Type *) BACKUP)->ALM2_TIME)
2058 #define BACKUP_ALM2_DATE (((BACKUP_Type *) BACKUP)->ALM2_DATE)
2059 #define BACKUP_INTR (((BACKUP_Type *) BACKUP)->INTR)
2060 #define BACKUP_INTR_SET (((BACKUP_Type *) BACKUP)->INTR_SET)
2061 #define BACKUP_INTR_MASK (((BACKUP_Type *) BACKUP)->INTR_MASK)
2062 #define BACKUP_INTR_MASKED (((BACKUP_Type *) BACKUP)->INTR_MASKED)
2063 #define BACKUP_RESET (((BACKUP_Type *) BACKUP)->RESET)
2064 #define BACKUP_CTL (((BACKUP_Type *) BACKUP)->CTL)
2065 #define BACKUP_WCO_CTL (((BACKUP_Type *) BACKUP)->WCO_CTL)
2066 #define BACKUP_WCO_STATUS (((BACKUP_Type *) BACKUP)->WCO_STATUS)
2067 #define BACKUP_LFWL_CTL (((BACKUP_Type *) BACKUP)->LFWL_CTL)
2068 #define BACKUP_BREG (((BACKUP_Type *) BACKUP)->BREG)
2069 #endif
2070
2071 #if defined (CY_IP_MXS40SSRSS)
2072 #define BACKUP_CTL (((BACKUP_Type *) BACKUP)->CTL)
2073 #define BACKUP_RTC_RW (((BACKUP_Type *) BACKUP)->RTC_RW)
2074 #define BACKUP_CAL_CTL (((BACKUP_Type *) BACKUP)->CAL_CTL)
2075 #define BACKUP_STATUS (((BACKUP_Type *) BACKUP)->STATUS)
2076 #define BACKUP_RTC_TIME (((BACKUP_Type *) BACKUP)->RTC_TIME)
2077 #define BACKUP_RTC_DATE (((BACKUP_Type *) BACKUP)->RTC_DATE)
2078 #define BACKUP_ALM1_TIME (((BACKUP_Type *) BACKUP)->ALM1_TIME)
2079 #define BACKUP_ALM1_DATE (((BACKUP_Type *) BACKUP)->ALM1_DATE)
2080 #define BACKUP_ALM2_TIME (((BACKUP_Type *) BACKUP)->ALM2_TIME)
2081 #define BACKUP_ALM2_DATE (((BACKUP_Type *) BACKUP)->ALM2_DATE)
2082 #define BACKUP_INTR (((BACKUP_Type *) BACKUP)->INTR)
2083 #define BACKUP_INTR_SET (((BACKUP_Type *) BACKUP)->INTR_SET)
2084 #define BACKUP_INTR_MASK (((BACKUP_Type *) BACKUP)->INTR_MASK)
2085 #define BACKUP_INTR_MASKED (((BACKUP_Type *) BACKUP)->INTR_MASKED)
2086 #define BACKUP_PMIC_CTL (((BACKUP_Type *) BACKUP)->PMIC_CTL)
2087 #define BACKUP_RESET (((BACKUP_Type *) BACKUP)->RESET)
2088 #define BACKUP_LPECO_CTL (((BACKUP_Type *) BACKUP)->LPECO_CTL)
2089 #define BACKUP_LPECO_PRESCALE (((BACKUP_Type *) BACKUP)->LPECO_PRESCALE)
2090 #define BACKUP_LPECO_STATUS (((BACKUP_Type *) BACKUP)->LPECO_STATUS)
2091 #define BACKUP_WCO_STATUS (((BACKUP_Type *) BACKUP)->WCO_STATUS)
2092 #define BACKUP_BREG_SET0 (((BACKUP_Type *) BACKUP)->BREG_SET0)
2093 #define BACKUP_BREG_SET1 (((BACKUP_Type *) BACKUP)->BREG_SET1)
2094 #define BACKUP_BREG_SET2 (((BACKUP_Type *) BACKUP)->BREG_SET2)
2095 #define BACKUP_BREG_SET3 (((BACKUP_Type *) BACKUP)->BREG_SET3)
2096
2097
2098 #define CY_SRSS_BACKUP_NUM_BREG (SRSS_BACKUP_NUM_BREG0 + SRSS_BACKUP_NUM_BREG1 + SRSS_BACKUP_NUM_BREG2 + SRSS_BACKUP_NUM_BREG3)
2099 #define CY_SRSS_BACKUP_BREG0_START_POS (0UL)
2100 #define CY_SRSS_BACKUP_BREG1_START_POS (SRSS_BACKUP_NUM_BREG0)
2101 #define CY_SRSS_BACKUP_BREG2_START_POS (SRSS_BACKUP_NUM_BREG0 + SRSS_BACKUP_NUM_BREG1)
2102 #define CY_SRSS_BACKUP_BREG3_START_POS (SRSS_BACKUP_NUM_BREG0 + SRSS_BACKUP_NUM_BREG1 + SRSS_BACKUP_NUM_BREG2)
2103
2104 #endif
2105
2106
2107 /*******************************************************************************
2108 * CANFD
2109 *******************************************************************************/
2110
2111 #define CANFD_CTL(base) (((CANFD_Type *)(base))->CTL)
2112 #define CANFD_STATUS(base) (((CANFD_Type *)(base))->STATUS)
2113 #define CANFD_NBTP(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NBTP)
2114 #define CANFD_IR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IR)
2115 #define CANFD_IE(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.IE)
2116 #define CANFD_ILS(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILS)
2117 #define CANFD_ILE(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.ILE)
2118 #define CANFD_CCCR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CCCR)
2119 #define CANFD_SIDFC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.SIDFC)
2120 #define CANFD_XIDFC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDFC)
2121 #define CANFD_XIDAM(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.XIDAM)
2122 #define CANFD_RXESC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXESC)
2123 #define CANFD_RXF0C(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0C)
2124 #define CANFD_RXF1C(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1C)
2125 #define CANFD_RXFTOP_CTL(base, chan) (((CANFD_Type *)(base))->CH[chan].RXFTOP_CTL)
2126 #define CANFD_RXBC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXBC)
2127 #define CANFD_TXESC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXESC)
2128 #define CANFD_TXEFC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXEFC)
2129 #define CANFD_TXBC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBC)
2130 #define CANFD_DBTP(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.DBTP)
2131 #define CANFD_TDCR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TDCR)
2132 #define CANFD_GFC(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.GFC)
2133 #define CANFD_TXBRP(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBRP)
2134 #define CANFD_TXBAR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBAR)
2135 #define CANFD_TXBCR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCR)
2136 #define CANFD_TXBTO(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTO)
2137 #define CANFD_TXBCF(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCF)
2138 #define CANFD_TXBTIE(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBTIE)
2139 #define CANFD_TXBCIE(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TXBCIE)
2140 #define CANFD_NDAT1(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT1)
2141 #define CANFD_NDAT2(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.NDAT2)
2142 #define CANFD_RXF0S(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0S)
2143 #define CANFD_RXFTOP0_DATA(base, chan) (((CANFD_Type *)(base))->CH[chan].RXFTOP0_DATA)
2144 #define CANFD_RXFTOP1_DATA(base, chan) (((CANFD_Type *)(base))->CH[chan].RXFTOP1_DATA)
2145 #define CANFD_RXF0A(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF0A)
2146 #define CANFD_RXF1S(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1S)
2147 #define CANFD_RXF1A(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.RXF1A)
2148 #define CANFD_PSR(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.PSR)
2149 #define CANFD_TEST(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.TEST)
2150 #define CANFD_CREL(base, chan) (((CANFD_Type *)(base))->CH[chan].M_TTCAN.CREL)
2151
2152 #define CY_CANFD_CHANNELS_NUM (0x1UL)
2153
2154 /*******************************************************************************
2155 * MXOTPC
2156 *******************************************************************************/
2157 #define CY_MXOTPC_BASE (uint32_t)GET_ALIAS_ADDRESS(MXOTPC)
2158
2159 #define MXOTPC_CTL (((MXOTPC_Type *) CY_MXOTPC_BASE)->CTL)
2160 #define MXOTPC_OTP_STATUS (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_STATUS)
2161 #define MXOTPC_OTP_CTL (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_CTL)
2162 #define MXOTPC_OTP_CMD (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_CMD)
2163 #define MXOTPC_LAYOUT (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT)
2164 #define MXOTPC_LAYOUT_EXT (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT)
2165 #define MXOTPC_OTP_PROGDATA (((MXOTPC_Type *) CY_MXOTPC_BASE)->OTP_PROGDATA)
2166 #define MXOTPC_FOUT_ECC_STATUS (((MXOTPC_Type *) CY_MXOTPC_BASE)->FOUT_ECC_STATUS)
2167 #define MXOTPC_ECC_STATUS (((MXOTPC_Type *) CY_MXOTPC_BASE)->ECC_STATUS)
2168 #define MXOTPC_CC312_ECC_STATUS (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_ECC_STATUS)
2169 #define MXOTPC_CC312_ERROR_LOG (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_ERROR_LOG)
2170 #define MXOTPC_CC312_CMD_SEL_LO (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_CMD_SEL_LO)
2171 #define MXOTPC_CC312_CMD_SEL_HI (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_CMD_SEL_HI)
2172 #define MXOTPC_LAYOUT_EXT1 (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT1)
2173 #define MXOTPC_LAYOUT_EXT2 (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT2)
2174 #define MXOTPC_LAYOUT_EXT3 (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT3)
2175 #define MXOTPC_LAYOUT_EXT4 (((MXOTPC_Type *) CY_MXOTPC_BASE)->LAYOUT_EXT4)
2176 #define MXOTPC_CPU_PROG_CMD (((MXOTPC_Type *) CY_MXOTPC_BASE)->CPU_PROG_CMD)
2177 #define MXOTPC_BOOTROW (((MXOTPC_Type *) CY_MXOTPC_BASE)->BOOTROW)
2178 #define MXOTPC_CC312_RGN_LOCK_CTL (((MXOTPC_Type *) CY_MXOTPC_BASE)->CC312_RGN_LOCK_CTL)
2179 #define MXOTPC_ERR_RESP_CTL (((MXOTPC_Type *) CY_MXOTPC_BASE)->ERR_RESP_CTL)
2180 #define MXOTPC_INTR_OTPC (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC)
2181 #define MXOTPC_INTR_OTPC_SET (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC_SET)
2182 #define MXOTPC_INTR_OTPC_MASK (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC_MASK)
2183 #define MXOTPC_INTR_OTPC_MASKED (((MXOTPC_Type *) CY_MXOTPC_BASE)->INTR_OTPC_MASKED)
2184 #define MXOTPC_CPU_ERROR_LOG (((MXOTPC_Type *) CY_MXOTPC_BASE)->CPU_ERROR_LOG)
2185
2186 #define MXOTPC_BOOT_ROW_FOUT_ECC_DED_STATUS_Msk 0x00070000UL
2187
2188 /*******************************************************************************
2189 * MXCONNBRIDGE
2190 *******************************************************************************/
2191
2192 #define MXCONNBRIDGE_CTL(base) (((MXCONNBRIDGE_Type *)(base))->CTL)
2193 #define MXCONNBRIDGE_INTR_STATUS(base) (((MXCONNBRIDGE_Type *)(base))->INTERRUPT_STATUS)
2194 #define MXCONNBRIDGE_INTR_MASK(base) (((MXCONNBRIDGE_Type *)(base))->INTERRUPT_MASK)
2195 #define MXCONNBRIDGE_RF_SWITCH_CTRL(base) (((MXCONNBRIDGE_Type *)(base))->RF_SWITCH_CTRL)
2196 #define MXCONNBRIDGE_GPIO_IN(base) (((MXCONNBRIDGE_Type *)(base))->GPIO_IN)
2197 #define MXCONNBRIDGE_GPIO_OUT(base) (((MXCONNBRIDGE_Type *)(base))->GPIO_OUT)
2198 #define MXCONNBRIDGE_DEV_WAKE(base) (((MXCONNBRIDGE_Type *)(base))->DEV_WAKE)
2199 #define MXCONNBRIDGE_AP_WLAN_CTL(base) (((MXCONNBRIDGE_Type *)(base))->AP_WLAN_CTL)
2200
2201 /*******************************************************************************
2202 * MXSDIODEV
2203 *******************************************************************************/
2204
2205 #define MXSDIO_CORECONTROL(base) (((MXSDIO_Type *)(base))->CORECONTROL)
2206 #define MXSDIO_CORESTATUS(base) (((MXSDIO_Type *)(base))->CORESTATUS)
2207 #define MXSDIO_BISTSTATUS(base) (((MXSDIO_Type *)(base))->BISTSTATUS)
2208 #define MXSDIO_INTSTATUS(base) (((MXSDIO_Type *)(base))->INTSTATUS)
2209 #define MXSDIO_INTHOSTMASK(base) (((MXSDIO_Type *)(base))->INTHOSTMASK)
2210 #define MXSDIO_INTSBMASK(base) (((MXSDIO_Type *)(base))->INTSBMASK)
2211 #define MXSDIO_SBINTSTATUS(base) (((MXSDIO_Type *)(base))->SBINTSTATUS)
2212 #define MXSDIO_SBINTMASK(base) (((MXSDIO_Type *)(base))->SBINTMASK)
2213 #define MXSDIO_SDIOFUNCINTMASK(base) (((MXSDIO_Type *)(base))->SDIOFUNCINTMASK)
2214 #define MXSDIO_TOSBMAILBOX(base) (((MXSDIO_Type *)(base))->TOSBMAILBOX)
2215 #define MXSDIO_TOHOSTMAILBOX(base) (((MXSDIO_Type *)(base))->TOHOSTMAILBOX)
2216 #define MXSDIO_TOSBMAILDATA(base) (((MXSDIO_Type *)(base))->TOSBMAILDATA)
2217 #define MXSDIO_TOHOSTMAILDATA(base) (((MXSDIO_Type *)(base))->TOHOSTMAILDATA)
2218 #define MXSDIO_SDIOACCESS(base) (((MXSDIO_Type *)(base))->SDIOACCESS)
2219 #define MXSDIO_UNUSEDINTFCTRL(base) (((MXSDIO_Type *)(base))->UNUSEDINTFCTRL)
2220 #define MXSDIO_INTRCVLAZY(base) (((MXSDIO_Type *)(base))->INTRCVLAZY)
2221 #define MXSDIO_CMD52RDCOUNT(base) (((MXSDIO_Type *)(base))->CMD52RDCOUNT)
2222 #define MXSDIO_CMD52WRCOUNT(base) (((MXSDIO_Type *)(base))->CMD52WRCOUNT)
2223 #define MXSDIO_CMD53RDCOUNT(base) (((MXSDIO_Type *)(base))->CMD53RDCOUNT)
2224 #define MXSDIO_CMD53WRCOUNT(base) (((MXSDIO_Type *)(base))->CMD53WRCOUNT)
2225 #define MXSDIO_ABORTCOUNT(base) (((MXSDIO_Type *)(base))->ABORTCOUNT)
2226 #define MXSDIO_CRCERRORCOUNT(base) (((MXSDIO_Type *)(base))->CRCERRORCOUNT)
2227 #define MXSDIO_RDOUTOFSYNCCOUNT(base) (((MXSDIO_Type *)(base))->RDOUTOFSYNCCOUNT)
2228 #define MXSDIO_WROUTOFSYNCCOUNT(base) (((MXSDIO_Type *)(base))->WROUTOFSYNCCOUNT)
2229 #define MXSDIO_WRITEBUSYCOUNT(base) (((MXSDIO_Type *)(base))->WRITEBUSYCOUNT)
2230 #define MXSDIO_READWAITCOUNT(base) (((MXSDIO_Type *)(base))->READWAITCOUNT)
2231 #define MXSDIO_RDTERMCOUNT(base) (((MXSDIO_Type *)(base))->RDTERMCOUNT)
2232 #define MXSDIO_WRTERMCOUNT(base) (((MXSDIO_Type *)(base))->WRTERMCOUNT)
2233 #define MXSDIO_CLOCKCTRLSTATUS(base) (((MXSDIO_Type *)(base))->CLOCKCTRLSTATUS)
2234 #define MXSDIO_WORKARND(base) (((MXSDIO_Type *)(base))->WORKARND)
2235 #define MXSDIO_PWRCTRL(base) (((MXSDIO_Type *)(base))->PWRCTRL)
2236 #define MXSDIO_XMTCONTROL(base) (((MXSDIO_Type *)(base))->XMTCONTROL)
2237 #define MXSDIO_XMTPTR(base) (((MXSDIO_Type *)(base))->XMTPTR)
2238 #define MXSDIO_XMTADDRESSLOW(base) (((MXSDIO_Type *)(base))->XMTADDRESSLOW)
2239 #define MXSDIO_XMTADDRESSHI(base) (((MXSDIO_Type *)(base))->XMTADDRESSHI)
2240 #define MXSDIO_XMTSTATUS0(base) (((MXSDIO_Type *)(base))->XMTSTATUS0)
2241 #define MXSDIO_XMTSTATUS1(base) (((MXSDIO_Type *)(base))->XMTSTATUS1)
2242 #define MXSDIO_RCVCONTROL(base) (((MXSDIO_Type *)(base))->RCVCONTROL)
2243 #define MXSDIO_RCVPTR(base) (((MXSDIO_Type *)(base))->RCVPTR)
2244 #define MXSDIO_RCVADDRESSLOW(base) (((MXSDIO_Type *)(base))->RCVADDRESSLOW)
2245 #define MXSDIO_RCVADDRESSHI(base) (((MXSDIO_Type *)(base))->RCVADDRESSHI)
2246 #define MXSDIO_RCVSTATUS0(base) (((MXSDIO_Type *)(base))->RCVSTATUS0)
2247 #define MXSDIO_RCVSTATUS1(base) (((MXSDIO_Type *)(base))->RCVSTATUS1)
2248 #define MXSDIO_FIFOADDRESS(base) (((MXSDIO_Type *)(base))->FIFOADDRESS)
2249 #define MXSDIO_FIFODATAL(base) (((MXSDIO_Type *)(base))->FIFODATAL)
2250 #define MXSDIO_FIFODATAH(base) (((MXSDIO_Type *)(base))->FIFODATAH)
2251 #define MXSDIO_SDIOCLKRESETCTRLREG(base) (((MXSDIO_Type *)(base))->SDIOCLKRESETCTRLREG)
2252 #define MXSDIO_OTPSTATUSSHADOWREG(base) (((MXSDIO_Type *)(base))->OTPSTATUSSHADOWREG)
2253 #define MXSDIO_OTPLAYOUTSHADOWREG(base) (((MXSDIO_Type *)(base))->OTPLAYOUTSHADOWREG)
2254 #define MXSDIO_OTPSHADOWREG1(base) (((MXSDIO_Type *)(base))->OTPSHADOWREG1)
2255 #define MXSDIO_OTPSHADOWREG2(base) (((MXSDIO_Type *)(base))->OTPSHADOWREG2)
2256 #define MXSDIO_OTPSHADOWREG3(base) (((MXSDIO_Type *)(base))->OTPSHADOWREG3)
2257
2258 /******************************************************************************
2259 * MXETH
2260 *******************************************************************************/
2261 #define ETH_CTL(base) (((ETH_Type*)(base))->CTL)
2262 #define ETH_TX_Q_PTR(base) (((ETH_Type*)(base))->TRANSMIT_Q_PTR)
2263 #define ETH_TX_Q1_PTR(base) (((ETH_Type*)(base))->TRANSMIT_Q1_PTR)
2264 #define ETH_TX_Q2_PTR(base) (((ETH_Type*)(base))->TRANSMIT_Q2_PTR)
2265 #define ETH_RX_Q_PTR(base) (((ETH_Type*)(base))->RECEIVE_Q_PTR)
2266 #define ETH_RX_Q1_PTR(base) (((ETH_Type*)(base))->RECEIVE_Q1_PTR)
2267 #define ETH_RX_Q2_PTR(base) (((ETH_Type*)(base))->RECEIVE_Q2_PTR)
2268
2269 /*******************************************************************************
2270 * PPU
2271 *******************************************************************************/
2272 #define CY_PPU_MAIN_BASE ((uint32_t)PWRMODE_PPU_MAIN)
2273 #define CY_PPU_CPUSS_BASE ((uint32_t)CPUSS_PPU_BASE)
2274 #define CY_PPU_SRAM_BASE ((uint32_t)RAMC_PPU0_BASE)
2275
2276 /*******************************************************************************
2277 * PDCM
2278 *******************************************************************************/
2279
2280 #define CY_PDCM_PD_SENSE(pd_id) (((PWRMODE_PD_Type*) &PWRMODE->PD[pd_id])->PD_SENSE)
2281 #define CY_PDCM_PD_SPT(pd_id) (((PWRMODE_PD_Type*) &PWRMODE->PD[pd_id])->PD_SPT)
2282
2283 /*******************************************************************************
2284 * IPC
2285 *******************************************************************************/
2286
2287 #define REG_IPC_STRUCT_ACQUIRE(base) (((IPC_STRUCT_Type*)(base))->ACQUIRE)
2288 #define REG_IPC_STRUCT_RELEASE(base) (((IPC_STRUCT_Type*)(base))->RELEASE)
2289 #define REG_IPC_STRUCT_NOTIFY(base) (((IPC_STRUCT_Type*)(base))->NOTIFY)
2290 #define REG_IPC_STRUCT_DATA(base) (((IPC_STRUCT_Type*)(base))->DATA0)
2291 #define REG_IPC_STRUCT_DATA1(base) (((IPC_STRUCT_Type*)(base))->DATA1)
2292 #define REG_IPC_STRUCT_LOCK_STATUS(base) (*(volatile uint32_t*)((uint32_t)(base) + offsetof(IPC_STRUCT_Type, LOCK_STATUS)))
2293
2294 #define REG_IPC_INTR_STRUCT_INTR(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR)
2295 #define REG_IPC_INTR_STRUCT_INTR_SET(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_SET)
2296 #define REG_IPC_INTR_STRUCT_INTR_MASK(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASK)
2297 #define REG_IPC_INTR_STRUCT_INTR_MASKED(base) (((IPC_INTR_STRUCT_Type*)(base))->INTR_MASKED)
2298
2299 #ifdef BTSS
2300 #define CY_IPC_STRUCT_PTR(ipcIndex) ((IPC_STRUCT_Type*)((void *)(((uint8_t*)&(BTSS_DATA_RAM_IPC->MXIPC_0_ACQUIRE)) + (sizeof(IPC_STRUCT_Type) * (ipcIndex)))))
2301 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex) ((IPC_INTR_STRUCT_Type *)((void*)(((uint8_t*)&(BTSS_DATA_RAM_IPC->MXIPC_INTR_0)) + (sizeof(IPC_INTR_STRUCT_Type) * (ipcIntrIndex)))))
2302 #else
2303 #define CY_IPC_STRUCT_PTR(ipcIndex) ((IPC_STRUCT_Type*)(IPC_BASE + (sizeof(IPC_STRUCT_Type) * (ipcIndex))))
2304 #define CY_IPC_INTR_STRUCT_PTR(ipcIntrIndex) (&(((IPC_Type *)IPC_BASE)->INTR_STRUCT[ipcIntrIndex]))
2305 #endif
2306
2307 #define CY_IPC_STRUCT_PTR_FOR_IP(ipcIndex, base) ((IPC_STRUCT_Type*)((uint32_t)(base) + (sizeof(IPC_STRUCT_Type) * (ipcIndex))))
2308 #define CY_IPC_INTR_STRUCT_PTR_FOR_IP(ipcIntrIndex, base) (&(((IPC_Type *)base)->INTR_STRUCT[ipcIntrIndex]))
2309
2310 #define CY_IPC_INSTANCES (1U)
2311 #define CY_IPC_CHANNELS ((uint32_t)CPUSS_IPC_NR)
2312 #define CY_IPC_INTERRUPTS ((uint32_t)CPUSS_IPC_IRQ_NR)
2313 #define CY_IPC_CHANNELS_PER_INSTANCE CY_IPC_CHANNELS
2314 #define CY_IPC_INTERRUPTS_PER_INSTANCE CY_IPC_INTERRUPTS
2315
2316 /* ipcChannel comprises of total number of channels present in all IPC IP instances */
2317 #define CY_IPC_PIPE_CHANNEL_NUMBER_WITHIN_INSTANCE(ipcChannel) (((ipcChannel)%CY_IPC_CHANNELS_PER_INSTANCE))
2318 #define CY_IPC_PIPE_INTR_NUMBER_WITHIN_INSTANCE(ipcIntr) (((ipcIntr)%CY_IPC_INTERRUPTS_PER_INSTANCE))
2319
2320 #define CY_IPC_CH_MASK(chIndex) (0x1u << chIndex)
2321 #define CY_IPC_INTR_MASK(intrIndex) (0x1u << intrIndex)
2322 #define CY_IPC_INTR_MUX(intrIndex) (cpuss_interrupts_ipc_dpslp_0_IRQn + intrIndex)
2323 #define cpuss_interrupts_ipc_0_IRQn cpuss_interrupts_ipc_dpslp_0_IRQn
2324 #define cpuss_interrupts_ipc_1_IRQn cpuss_interrupts_ipc_dpslp_1_IRQn
2325
2326 #if defined (CY_DEVICE_BOY2)
2327 /* Reserve Channels are Interrupts for CM33-S and Cm33-NS */
2328 #define CM33_S_IPC_CH_NUM (0x0u)
2329 #define CM33_S_IPC_CH_MASK (CY_IPC_CH_MASK(CM33_S_IPC_CH_NUM))
2330 #define CM33_S_IPC_INTR_NUM (0x0u)
2331 #define CM33_S_IPC_INTR_MASK (CY_IPC_INTR_MASK(CM33_S_IPC_INTR_NUM))
2332 #define CM33_S_IPC_INTR_MUX (CY_IPC_INTR_MUX(CM33_S_IPC_INTR_NUM))
2333
2334 /* user IPC channel */
2335 #define CY_IPC_CHAN_USER (CM33_S_IPC_CH_NUM + 1u)
2336 /* user IPC interrupt */
2337 #define CY_IPC_INTR_USER (CM33_S_IPC_INTR_NUM + 1u)
2338
2339 #endif
2340
2341 /*******************************************************************************
2342 * LIN
2343 *******************************************************************************/
2344 #if defined (CY_IP_MXLIN)
2345 #define LIN0_CH1 ((LIN_CH_Type*) &LIN0->CH[1])
2346 #define LIN0_CH2 ((LIN_CH_Type*) &LIN0->CH[2])
2347 #define LIN0_CH3 ((LIN_CH_Type*) &LIN0->CH[3])
2348 #define LIN0_CH4 ((LIN_CH_Type*) &LIN0->CH[4])
2349 #define LIN0_CH5 ((LIN_CH_Type*) &LIN0->CH[5])
2350 #define LIN0_CH6 ((LIN_CH_Type*) &LIN0->CH[6])
2351 #define LIN0_CH7 ((LIN_CH_Type*) &LIN0->CH[7])
2352 #define LIN0_CH8 ((LIN_CH_Type*) &LIN0->CH[8])
2353 #define LIN0_CH9 ((LIN_CH_Type*) &LIN0->CH[9])
2354 #define LIN0_CH10 ((LIN_CH_Type*) &LIN0->CH[10])
2355 #define LIN0_CH11 ((LIN_CH_Type*) &LIN0->CH[11])
2356 #define LIN0_CH12 ((LIN_CH_Type*) &LIN0->CH[12])
2357 #define LIN0_CH13 ((LIN_CH_Type*) &LIN0->CH[13])
2358 #define LIN0_CH14 ((LIN_CH_Type*) &LIN0->CH[14])
2359 #define LIN0_CH15 ((LIN_CH_Type*) &LIN0->CH[15])
2360 #define LIN0_CH16 ((LIN_CH_Type*) &LIN0->CH[16])
2361 #define LIN0_CH17 ((LIN_CH_Type*) &LIN0->CH[17])
2362 #define LIN0_CH18 ((LIN_CH_Type*) &LIN0->CH[18])
2363 #define LIN0_CH19 ((LIN_CH_Type*) &LIN0->CH[19])
2364 #define LIN0_CH20 ((LIN_CH_Type*) &LIN0->CH[20])
2365 #define LIN0_CH21 ((LIN_CH_Type*) &LIN0->CH[21])
2366 #define LIN0_CH22 ((LIN_CH_Type*) &LIN0->CH[22])
2367 #define LIN0_CH23 ((LIN_CH_Type*) &LIN0->CH[23])
2368 #define LIN0_CH24 ((LIN_CH_Type*) &LIN0->CH[24])
2369 #define LIN0_CH25 ((LIN_CH_Type*) &LIN0->CH[25])
2370 #define LIN0_CH26 ((LIN_CH_Type*) &LIN0->CH[26])
2371 #define LIN0_CH27 ((LIN_CH_Type*) &LIN0->CH[27])
2372 #define LIN0_CH28 ((LIN_CH_Type*) &LIN0->CH[28])
2373 #define LIN0_CH29 ((LIN_CH_Type*) &LIN0->CH[29])
2374 #define LIN0_CH30 ((LIN_CH_Type*) &LIN0->CH[30])
2375 #define LIN0_CH31 ((LIN_CH_Type*) &LIN0->CH[31])
2376
2377 #define LIN_CH_CTL0(base) (((LIN_CH_Type *)(base))->CTL0)
2378 #define LIN_CH_CTL1(base) (((LIN_CH_Type *)(base))->CTL1)
2379 #define LIN_CH_STATUS(base) (((LIN_CH_Type *)(base))->STATUS)
2380 #define LIN_CH_CMD(base) (((LIN_CH_Type *)(base))->CMD)
2381 #define LIN_CH_TX_RX_STATUS(base) (((LIN_CH_Type *)(base))->TX_RX_STATUS)
2382 #define LIN_CH_PID_CHECKSUM(base) (((LIN_CH_Type *)(base))->PID_CHECKSUM)
2383 #define LIN_CH_DATA0(base) (((LIN_CH_Type *)(base))->DATA0)
2384 #define LIN_CH_DATA1(base) (((LIN_CH_Type *)(base))->DATA1)
2385 #define LIN_CH_INTR(base) (((LIN_CH_Type *)(base))->INTR)
2386 #define LIN_CH_INTR_SET(base) (((LIN_CH_Type *)(base))->INTR_SET)
2387 #define LIN_CH_INTR_MASK(base) (((LIN_CH_Type *)(base))->INTR_MASK)
2388 #define LIN_CH_INTR_MASKED(base) (((LIN_CH_Type *)(base))->INTR_MASKED)
2389
2390 #define LIN_ERROR_CTL(base) (((LIN_Type *)(base))->ERROR_CTL)
2391 #define LIN_TEST_CTL(base) (((LIN_Type *)(base))->TEST_CTL)
2392 #endif /* CY_IP_MXLIN */
2393
2394 /*******************************************************************************
2395 * MXKEYSCAN
2396 *******************************************************************************/
2397 #if defined (CY_IP_MXKEYSCAN)
2398
2399 #define KEYSCAN_CTL(base) (((MXKEYSCAN_Type *)(base))->KEYSCAN_CTL)
2400 #define KEYSCAN_DEBOUNCE(base) (((MXKEYSCAN_Type *)(base))->DEBOUNCE)
2401 #define KEYSCAN_KEYFIFO_CNT(base) (((MXKEYSCAN_Type *)(base))->KEYFIFO_CNT)
2402 #define KEYSCAN_KEYFIFO(base) (((MXKEYSCAN_Type *)(base))->KEYFIFO)
2403 #define KEYSCAN_MIA_CTL(base) (((MXKEYSCAN_Type *)(base))->MIA_CTL)
2404 #define KEYSCAN_MIA_STATUS(base) (((MXKEYSCAN_Type *)(base))->MIA_STATUS)
2405 #define KEYSCAN_KSI_USED(base) (((MXKEYSCAN_Type *)(base))->KSI_USED)
2406 #define KEYSCAN_INTR(base) (((MXKEYSCAN_Type *)(base))->INTR)
2407 #define KEYSCAN_INTR_SET(base) (((MXKEYSCAN_Type *)(base))->INTR_SET)
2408 #define KEYSCAN_INTR_MASK(base) (((MXKEYSCAN_Type *)(base))->INTR_MASK)
2409 #define KEYSCAN_INTR_MASKED(base) (((MXKEYSCAN_Type *)(base))->INTR_MASKED)
2410
2411 #endif /* CY_IP_MXKEYSCAN */
2412
2413 #define MPC_Type RAMC_MPC_Type
2414 #ifdef CPUSS_PC_NR
2415 #define MPC_PC_NR CPUSS_PC_NR
2416 #else
2417 #define MPC_PC_NR RAMC0_MPC_PC_NR
2418 #endif
2419
2420 /*******************************************************************************
2421 * MS_CTL
2422 *******************************************************************************/
2423 #ifdef _CYIP_MS_CTL_2_1_V2_H_
2424
2425 #define MS_CTL_PC_CTL_VX(index) (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->MS[(index)].CTL)
2426 #define MS_CTL_PC_VAL_VX(index) (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->MS_PC[(index)].PC)
2427 #define MS_CTL_PC_READ_MIRROR_VX(index) (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->MS_PC[(index)].PC_READ_MIR)
2428 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_VX (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->CODE_MS0_MSC_ACG_CTL)
2429 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_VX (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->SYS_MS0_MSC_ACG_CTL)
2430 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_VX (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->SYS_MS1_MSC_ACG_CTL)
2431 #define MS_CTL_EXP_MS_MSC_ACG_CTL_VX (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->EXP_MS_MSC_ACG_CTL)
2432 #define MS_CTL_DMAC0_MSC_ACG_CTL_VX (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->DMAC0_MSC_ACG_CTL)
2433 #define MS_CTL_DMAC1_MSC_ACG_CTL_VX (((MS_CTL_2_1_Type*) MS_CTL_2_1_BASE)->DMAC1_MSC_ACG_CTL)
2434
2435 /* MS_CTL.CODE_MS0_MSC_ACG_CTL */
2436 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2437 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2438 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2439 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_2_1_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2440 /* MS_CTL.SYS_MS0_MSC_ACG_CTL */
2441 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2442 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2443 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2444 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_2_1_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2445 /* MS_CTL.SYS_MS1_MSC_ACG_CTL */
2446 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2447 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2448 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Pos
2449 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_2_1_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Msk
2450 /* MS_CTL.EXP_MS_MSC_ACG_CTL */
2451 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2452 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2453 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_SEC_RESP_Pos
2454 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_2_1_EXP_MS_MSC_ACG_CTL_SEC_RESP_Msk
2455 /* MS_CTL.DMAC0_MSC_ACG_CTL */
2456 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_2_1_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2457 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_2_1_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2458 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_2_1_DMAC0_MSC_ACG_CTL_SEC_RESP_Pos
2459 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_2_1_DMAC0_MSC_ACG_CTL_SEC_RESP_Msk
2460 /* MS_CTL.DMAC1_MSC_ACG_CTL */
2461 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_2_1_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2462 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_2_1_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2463 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_2_1_DMAC1_MSC_ACG_CTL_SEC_RESP_Pos
2464 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_2_1_DMAC1_MSC_ACG_CTL_SEC_RESP_Msk
2465
2466 #else
2467
2468 #define MS_CTL_PC_CTL_VX(index) (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->MS[(index)].CTL)
2469 #define MS_CTL_PC_VAL_VX(index) (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->MS_PC[(index)].PC)
2470 #define MS_CTL_PC_READ_MIRROR_VX(index) (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->MS_PC[(index)].PC_READ_MIR)
2471 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_VX (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->CODE_MS0_MSC_ACG_CTL)
2472 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_VX (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->SYS_MS0_MSC_ACG_CTL)
2473 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_VX (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->SYS_MS1_MSC_ACG_CTL)
2474 #define MS_CTL_EXP_MS_MSC_ACG_CTL_VX (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->EXP_MS_MSC_ACG_CTL)
2475 #define MS_CTL_DMAC0_MSC_ACG_CTL_VX (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->DMAC0_MSC_ACG_CTL)
2476 #define MS_CTL_DMAC1_MSC_ACG_CTL_VX (((MS_CTL_1_2_Type*) MS_CTL_1_2_BASE)->DMAC1_MSC_ACG_CTL)
2477
2478 /* MS_CTL.CODE_MS0_MSC_ACG_CTL */
2479 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2480 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2481 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2482 #define MS_CTL_CODE_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_1_2_CODE_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2483 /* MS_CTL.SYS_MS0_MSC_ACG_CTL */
2484 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2485 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2486 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Pos
2487 #define MS_CTL_SYS_MS0_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_1_2_SYS_MS0_MSC_ACG_CTL_SEC_RESP_Msk
2488 /* MS_CTL.SYS_MS1_MSC_ACG_CTL */
2489 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2490 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2491 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Pos
2492 #define MS_CTL_SYS_MS1_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_1_2_SYS_MS1_MSC_ACG_CTL_SEC_RESP_Msk
2493 /* MS_CTL.EXP_MS_MSC_ACG_CTL */
2494 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2495 #define MS_CTL_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2496 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_SEC_RESP_Pos
2497 #define MS_CTL_EXP_MS_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_1_2_EXP_MS_MSC_ACG_CTL_SEC_RESP_Msk
2498 /* MS_CTL.DMAC0_MSC_ACG_CTL */
2499 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_1_2_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2500 #define MS_CTL_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_1_2_DMAC0_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2501 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_1_2_DMAC0_MSC_ACG_CTL_SEC_RESP_Pos
2502 #define MS_CTL_DMAC0_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_1_2_DMAC0_MSC_ACG_CTL_SEC_RESP_Msk
2503 /* MS_CTL.DMAC1_MSC_ACG_CTL */
2504 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Pos MS_CTL_1_2_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Pos
2505 #define MS_CTL_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_VX_Msk MS_CTL_1_2_DMAC1_MSC_ACG_CTL_CFG_GATE_RESP_Msk
2506 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Pos MS_CTL_1_2_DMAC1_MSC_ACG_CTL_SEC_RESP_Pos
2507 #define MS_CTL_DMAC1_MSC_ACG_CTL_SEC_RESP_VX_Msk MS_CTL_1_2_DMAC1_MSC_ACG_CTL_SEC_RESP_Msk
2508
2509 #endif
2510
2511
2512 /*******************************************************************************
2513 * MXSRAMC
2514 *******************************************************************************/
2515 #define MXSRAMC_STATUS (((RAMC_Type *) RAMC0_BASE)->STATUS)
2516 #define MXSRAMC_PWR_MACRO_CTL (((RAMC_Type *) RAMC0_BASE)->PWR_MACRO_CTL)
2517 #define MXSRAMC_PWR_MACRO_CTL_LOCK (((RAMC_Type *) RAMC0_BASE)->PWR_MACRO_CTL_LOCK)
2518
2519
2520 #define MXSRAMC_PWR_MACRO_CTL_LOCK_CLR0 0X00000001U
2521 #define MXSRAMC_PWR_MACRO_CTL_LOCK_CLR1 0X00000002U
2522 #define MXSRAMC_PWR_MACRO_CTL_LOCK_SET01 0X00000003U
2523 #define CY_CPUSS_RAMC0_MACRO_NR CPUSS_RAMC0_MACRO_NR
2524
2525
2526 /*******************************************************************************
2527 * FLASHC
2528 *******************************************************************************/
2529
2530 #define FLASHC_FLASH_CTL (((FLASHC_Type *)(FLASHC))->FLASH_CTL)
2531 #define FLASHC_FLASH_ECC_INJ_EN (((FLASHC_Type *)(FLASHC))->ECC_INJ_EN)
2532 #define FLASHC_FLASH_ECC_INJ_CTL (((FLASHC_Type *)(FLASHC))->ECC_INJ_CTL)
2533
2534 /*******************************************************************************
2535 * PPC
2536 *******************************************************************************/
2537 #if defined (CY_DEVICE_BOY2)
2538 #define PPC_VALIDATE(ipInst, regionID) ((((ipInst) == PPC) && ((regionID) <= (uint32_t)PROT_MCPASS))? true : false)
2539 #else
2540 #define PPC_VALIDATE(ipInst, regionID) ((((ipInst) == PPC) && ((regionID) <= (uint32_t)PROT_BTSS_SECURE))? true : false)
2541 #endif /* CY_DEVICE_BOY2 */
2542
2543 #ifdef _CYIP_PPC_V2_H_
2544 #define PPC_Type PPC_PPC_Type
2545 #define PPC_CTL_RESP_CFG_Msk PPC_PPC_CTL_RESP_CFG_Msk
2546 #endif
2547
2548
2549 /*******************************************************************************
2550 * CORDIC
2551 *******************************************************************************/
2552 #if defined (CY_DEVICE_BOY2)
2553 typedef MXCORDIC_1_0_Type MXCORDIC_Type;
2554
2555 #define MXCORDIC MXCORDIC_1_0
2556
2557 /* MXCORDIC.CTL */
2558 #define MXCORDIC_CTL_ENABLED_Pos MXCORDIC_1_0_CTL_ENABLED_Pos
2559 #define MXCORDIC_CTL_ENABLED_Msk MXCORDIC_1_0_CTL_ENABLED_Msk
2560 /* MXCORDIC.ID */
2561 #define MXCORDIC_ID_MOD_REV_Pos MXCORDIC_1_0_ID_MOD_REV_Pos
2562 #define MXCORDIC_ID_MOD_REV_Msk MXCORDIC_1_0_ID_MOD_REV_Msk
2563 #define MXCORDIC_ID_MOD_TYPE_Pos MXCORDIC_1_0_ID_MOD_TYPE_Pos
2564 #define MXCORDIC_ID_MOD_TYPE_Msk MXCORDIC_1_0_ID_MOD_TYPE_Msk
2565 #define MXCORDIC_ID_MOD_NUMBER_Pos MXCORDIC_1_0_ID_MOD_NUMBER_Pos
2566 #define MXCORDIC_ID_MOD_NUMBER_Msk MXCORDIC_1_0_ID_MOD_NUMBER_Msk
2567 /* MXCORDIC.INTR */
2568 #define MXCORDIC_INTR_CDEOC_Pos MXCORDIC_1_0_INTR_CDEOC_Pos
2569 #define MXCORDIC_INTR_CDEOC_Msk MXCORDIC_1_0_INTR_CDEOC_Msk
2570 #define MXCORDIC_INTR_CDERR_Pos MXCORDIC_1_0_INTR_CDERR_Pos
2571 #define MXCORDIC_INTR_CDERR_Msk MXCORDIC_1_0_INTR_CDERR_Msk
2572 /* MXCORDIC.INTR_SET */
2573 #define MXCORDIC_INTR_SET_CDEOC_Pos MXCORDIC_1_0_INTR_SET_CDEOC_Pos
2574 #define MXCORDIC_INTR_SET_CDEOC_Msk MXCORDIC_1_0_INTR_SET_CDEOC_Msk
2575 #define MXCORDIC_INTR_SET_CDERR_Pos MXCORDIC_1_0_INTR_SET_CDERR_Pos
2576 #define MXCORDIC_INTR_SET_CDERR_Msk MXCORDIC_1_0_INTR_SET_CDERR_Msk
2577 /* MXCORDIC.INTR_MASK */
2578 #define MXCORDIC_INTR_MASK_CDEOC_Pos MXCORDIC_1_0_INTR_MASK_CDEOC_Pos
2579 #define MXCORDIC_INTR_MASK_CDEOC_Msk MXCORDIC_1_0_INTR_MASK_CDEOC_Msk
2580 #define MXCORDIC_INTR_MASK_CDERR_Pos MXCORDIC_1_0_INTR_MASK_CDERR_Pos
2581 #define MXCORDIC_INTR_MASK_CDERR_Msk MXCORDIC_1_0_INTR_MASK_CDERR_Msk
2582 /* MXCORDIC.INTR_MASKED */
2583 #define MXCORDIC_INTR_MASKED_CDEOC_Pos MXCORDIC_1_0_INTR_MASKED_CDEOC_Pos
2584 #define MXCORDIC_INTR_MASKED_CDEOC_Msk MXCORDIC_1_0_INTR_MASKED_CDEOC_Msk
2585 #define MXCORDIC_INTR_MASKED_CDERR_Pos MXCORDIC_1_0_INTR_MASKED_CDERR_Pos
2586 #define MXCORDIC_INTR_MASKED_CDERR_Msk MXCORDIC_1_0_INTR_MASKED_CDERR_Msk
2587 /* MXCORDIC.KEEP */
2588 #define MXCORDIC_KEEP_KEEPX_Pos MXCORDIC_1_0_KEEP_KEEPX_Pos
2589 #define MXCORDIC_KEEP_KEEPX_Msk MXCORDIC_1_0_KEEP_KEEPX_Msk
2590 #define MXCORDIC_KEEP_KEEPY_Pos MXCORDIC_1_0_KEEP_KEEPY_Pos
2591 #define MXCORDIC_KEEP_KEEPY_Msk MXCORDIC_1_0_KEEP_KEEPY_Msk
2592 #define MXCORDIC_KEEP_KEEPZ_Pos MXCORDIC_1_0_KEEP_KEEPZ_Pos
2593 #define MXCORDIC_KEEP_KEEPZ_Msk MXCORDIC_1_0_KEEP_KEEPZ_Msk
2594 /* MXCORDIC.CON */
2595 #define MXCORDIC_CON_MODE_Pos MXCORDIC_1_0_CON_MODE_Pos
2596 #define MXCORDIC_CON_MODE_Msk MXCORDIC_1_0_CON_MODE_Msk
2597 #define MXCORDIC_CON_ROTVEC_Pos MXCORDIC_1_0_CON_ROTVEC_Pos
2598 #define MXCORDIC_CON_ROTVEC_Msk MXCORDIC_1_0_CON_ROTVEC_Msk
2599 #define MXCORDIC_CON_ST_MODE_Pos MXCORDIC_1_0_CON_ST_MODE_Pos
2600 #define MXCORDIC_CON_ST_MODE_Msk MXCORDIC_1_0_CON_ST_MODE_Msk
2601 #define MXCORDIC_CON_X_USIGN_Pos MXCORDIC_1_0_CON_X_USIGN_Pos
2602 #define MXCORDIC_CON_X_USIGN_Msk MXCORDIC_1_0_CON_X_USIGN_Msk
2603 #define MXCORDIC_CON_MPS_Pos MXCORDIC_1_0_CON_MPS_Pos
2604 #define MXCORDIC_CON_MPS_Msk MXCORDIC_1_0_CON_MPS_Msk
2605 #define MXCORDIC_CON_N_ITER_Pos MXCORDIC_1_0_CON_N_ITER_Pos
2606 #define MXCORDIC_CON_N_ITER_Msk MXCORDIC_1_0_CON_N_ITER_Msk
2607 /* MXCORDIC.CORDX */
2608 #define MXCORDIC_CORDX_DATA_Pos MXCORDIC_1_0_CORDX_DATA_Pos
2609 #define MXCORDIC_CORDX_DATA_Msk MXCORDIC_1_0_CORDX_DATA_Msk
2610 /* MXCORDIC.CORDY */
2611 #define MXCORDIC_CORDY_DATA_Pos MXCORDIC_1_0_CORDY_DATA_Pos
2612 #define MXCORDIC_CORDY_DATA_Msk MXCORDIC_1_0_CORDY_DATA_Msk
2613 /* MXCORDIC.CORDZ */
2614 #define MXCORDIC_CORDZ_DATA_Pos MXCORDIC_1_0_CORDZ_DATA_Pos
2615 #define MXCORDIC_CORDZ_DATA_Msk MXCORDIC_1_0_CORDZ_DATA_Msk
2616 /* MXCORDIC.CORRX */
2617 #define MXCORDIC_CORRX_RESULT_Pos MXCORDIC_1_0_CORRX_RESULT_Pos
2618 #define MXCORDIC_CORRX_RESULT_Msk MXCORDIC_1_0_CORRX_RESULT_Msk
2619 /* MXCORDIC.CORRY */
2620 #define MXCORDIC_CORRY_RESULT_Pos MXCORDIC_1_0_CORRY_RESULT_Pos
2621 #define MXCORDIC_CORRY_RESULT_Msk MXCORDIC_1_0_CORRY_RESULT_Msk
2622 /* MXCORDIC.CORRZ */
2623 #define MXCORDIC_CORRZ_RESULT_Pos MXCORDIC_1_0_CORRZ_RESULT_Pos
2624 #define MXCORDIC_CORRZ_RESULT_Msk MXCORDIC_1_0_CORRZ_RESULT_Msk
2625 /* MXCORDIC.STAT */
2626 #define MXCORDIC_STAT_BSY_Pos MXCORDIC_1_0_STAT_BSY_Pos
2627 #define MXCORDIC_STAT_BSY_Msk MXCORDIC_1_0_STAT_BSY_Msk
2628 /* MXCORDIC.START_CMD */
2629 #define MXCORDIC_START_CMD_ST_Pos MXCORDIC_1_0_START_CMD_ST_Pos
2630 #define MXCORDIC_START_CMD_ST_Msk MXCORDIC_1_0_START_CMD_ST_Msk
2631
2632 #define MXCORDIC_CTL(base) (((MXCORDIC_Type *)(base))->CTL)
2633 #define MXCORDIC_INTR(base) (((MXCORDIC_Type *)(base))->INTR)
2634 #define MXCORDIC_INTR_SET(base) (((MXCORDIC_Type *)(base))->INTR_SET)
2635 #define MXCORDIC_INTR_MASK(base) (((MXCORDIC_Type *)(base))->INTR_MASK)
2636 #define MXCORDIC_INTR_MASKED(base) (((MXCORDIC_Type *)(base))->INTR_MASKED)
2637 #define MXCORDIC_KEEP(base) (((MXCORDIC_Type *)(base))->KEEP)
2638 #define MXCORDIC_CON(base) (((MXCORDIC_Type *)(base))->CON)
2639 #define MXCORDIC_CORDX(base) (((MXCORDIC_Type *)(base))->CORDX)
2640 #define MXCORDIC_CORDY(base) (((MXCORDIC_Type *)(base))->CORDY)
2641 #define MXCORDIC_CORDZ(base) (((MXCORDIC_Type *)(base))->CORDZ)
2642 #define MXCORDIC_CORRX(base) (((MXCORDIC_Type *)(base))->CORRX)
2643 #define MXCORDIC_CORRY(base) (((MXCORDIC_Type *)(base))->CORRY)
2644 #define MXCORDIC_CORRZ(base) (((MXCORDIC_Type *)(base))->CORRZ)
2645 #define MXCORDIC_STAT(base) (((MXCORDIC_Type *)(base))->STAT)
2646 #define MXCORDIC_START_CMD(base) (((MXCORDIC_Type *)(base))->START_CMD)
2647
2648 #endif
2649
2650
2651 /*******************************************************************************
2652 * MCPASS
2653 *******************************************************************************/
2654
2655 #ifdef CY_IP_MXS40MCPASS
2656 #define MCPASS_AC_CTRL(base) (((MCPASS_Type *)(base))->ACTRLR.CTRL)
2657 #define MCPASS_AC_BLOCK_STATUS(base) (((MCPASS_Type *)(base))->ACTRLR.BLOCK_STATUS)
2658 #define MCPASS_AC_STATUS(base) (((MCPASS_Type *)(base))->ACTRLR.STATUS)
2659 #define MCPASS_AC_CMD_RUN(base) (((MCPASS_Type *)(base))->ACTRLR.CMD_RUN)
2660 #define MCPASS_AC_CMD_STATE(base) (((MCPASS_Type *)(base))->ACTRLR.CMD_STATE)
2661 #define MCPASS_AC_CFG(base) (((MCPASS_Type *)(base))->ACTRLR.CFG)
2662 #define MCPASS_AC_CNTR_STATUS(base, cntIdx) (((MCPASS_Type *)(base))->ACTRLR.CNTR_STATUS[cntIdx])
2663 #define MCPASS_AC_TT_CFG0(base, rowIdx) (((MCPASS_ACTRLR_TTCFG_Type *)(&((MCPASS_Type *)base)->ACTRLR.TTCFG[rowIdx]))->TT_CFG0)
2664 #define MCPASS_AC_TT_CFG1(base, rowIdx) (((MCPASS_ACTRLR_TTCFG_Type *)(&((MCPASS_Type *)base)->ACTRLR.TTCFG[rowIdx]))->TT_CFG1)
2665 #define MCPASS_AC_TT_CFG2(base, rowIdx) (((MCPASS_ACTRLR_TTCFG_Type *)(&((MCPASS_Type *)base)->ACTRLR.TTCFG[rowIdx]))->TT_CFG2)
2666 #define MCPASS_AC_TT_CFG3(base, rowIdx) (((MCPASS_ACTRLR_TTCFG_Type *)(&((MCPASS_Type *)base)->ACTRLR.TTCFG[rowIdx]))->TT_CFG3)
2667 #define MCPASS_FIFO_INTR(base) (((MCPASS_Type *)(base))->MMIO.FIFO_INTR)
2668 #define MCPASS_FIFO_INTR_SET(base) (((MCPASS_Type *)(base))->MMIO.FIFO_INTR_SET)
2669 #define MCPASS_FIFO_INTR_MASK(base) (((MCPASS_Type *)(base))->MMIO.FIFO_INTR_MASK)
2670 #define MCPASS_FIFO_INTR_MASKED(base) (((MCPASS_Type *)(base))->MMIO.FIFO_INTR_MASKED)
2671 #define MCPASS_MMIO_INTR(base) (((MCPASS_Type *)(base))->MMIO.MCPASS_INTR)
2672 #define MCPASS_MMIO_INTR_SET(base) (((MCPASS_Type *)(base))->MMIO.MCPASS_INTR_SET)
2673 #define MCPASS_MMIO_INTR_MASK(base) (((MCPASS_Type *)(base))->MMIO.MCPASS_INTR_MASK)
2674 #define MCPASS_MMIO_TR_LEVEL_CFG(base) (((MCPASS_Type *)(base))->MMIO.TR_LEVEL_CFG)
2675 #define MCPASS_MMIO_TR_LEVEL_OUT(base, trigIdx) (((MCPASS_Type *)(base))->MMIO.TR_LEVEL_OUT[trigIdx])
2676 #define MCPASS_MMIO_TR_PULSE_OUT(base, trigIdx) (((MCPASS_Type *)(base))->MMIO.TR_PULSE_OUT[trigIdx])
2677 #define MCPASS_MMIO_INTR_MASKED(base) (((MCPASS_Type *)(base))->MMIO.MCPASS_INTR_MASKED)
2678 #define MCPASS_MMIO_FIFO_CFG(base) (((MCPASS_Type *)(base))->MMIO.FIFO.CFG)
2679 #define MCPASS_MMIO_FIFO_LEVEL(base, fifoIdx) (((MCPASS_Type *)(base))->MMIO.FIFO.LEVEL[fifoIdx])
2680 #define MCPASS_MMIO_FIFO_USED(base, fifoIdx) (((MCPASS_Type *)(base))->MMIO.FIFO.USED[fifoIdx])
2681 #define MCPASS_MMIO_FIFO_RD_DATA(base, fifoIdx) (((MCPASS_Type *)(base))->MMIO.FIFO.RD_DATA[fifoIdx])
2682 #define MCPASS_SAR_CALOFFST(base, idx) (((MCPASS_Type *)(base))->SARADC.CALOFFST[idx])
2683 #define MCPASS_SAR_CALLIN(base, idx) (((MCPASS_Type *)(base))->SARADC.CALLIN[idx])
2684 #define MCPASS_SAR_CALGAINC(base) (((MCPASS_Type *)(base))->SARADC.CALGAINC)
2685 #define MCPASS_SAR_CALGAINF(base) (((MCPASS_Type *)(base))->SARADC.CALGAINF)
2686 #define MCPASS_SAR_CTRL(base) (((MCPASS_Type *)(base))->SAR.CFG.CTRL)
2687 #define MCPASS_SAR_RESULT_INTR(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_INTR)
2688 #define MCPASS_SAR_RESULT_INTR_SET(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_INTR_SET)
2689 #define MCPASS_SAR_RESULT_INTR_MASK(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_INTR_MASK)
2690 #define MCPASS_SAR_RESULT_INTR_MASKED(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RESULT_INTR_MASKED)
2691 #define MCPASS_SAR_LIMIT_INTR(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RANGE_INTR)
2692 #define MCPASS_SAR_LIMIT_INTR_SET(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RANGE_INTR_SET)
2693 #define MCPASS_SAR_LIMIT_INTR_MASK(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RANGE_INTR_MASK)
2694 #define MCPASS_SAR_LIMIT_INTR_MASKED(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_RANGE_INTR_MASKED)
2695 #define MCPASS_SAR_GROUP_HOLD_VIOLATION(base) (((MCPASS_Type *)(base))->SAR.CFG.ENTRY_HOLD_VIOLATION)
2696 #define MCPASS_SAR_GROUP_HOLD_CNT(base) (((MCPASS_Type *)(base))->SAR.CFG.ENTRY_HOLD_CNT)
2697 #define MCPASS_SAR_LIMIT_STATUS(base) (((MCPASS_Type *)(base))->SAR.CFG.RANGE_STATUS)
2698 #define MCPASS_SAR_STATUS(base) (((MCPASS_Type *)(base))->SAR.CFG.SAR_STATUS)
2699 #define MCPASS_SAR_RESULT_STATUS(base) (((MCPASS_Type *)(base))->SAR.CFG.RESULT_UPDATED)
2700 #define MCPASS_SAR_RESULT_OVERFLOW(base) (((MCPASS_Type *)(base))->SAR.CFG.RESULT_OVERFLOW)
2701 #define MCPASS_SAR_RESULT_MASK(base) (((MCPASS_Type *)(base))->SAR.CFG.RESULT_MASK)
2702 #define MCPASS_SAR_CHAN_RESULT(base, chanIdx) (((MCPASS_Type *)(base))->SAR.CFG.CHAN_RESULT[chanIdx])
2703 #define MCPASS_SAR_CHAN_RESULT_PACKED(base, chanIdx) (((MCPASS_Type *)(base))->SAR.CFG.CHAN_RESULT_PACKED[chanIdx])
2704 #define MCPASS_SAR_FIR_RESULT(base, firIdx) (((MCPASS_Type *)(base))->SAR.CFG.FIR_RESULT[firIdx])
2705 #define MCPASS_SAR_LIMIT_CFG(base, limIdx) (((MCPASS_Type *)(base))->SAR.CFG.RANGE_CFG[limIdx])
2706 #define MCPASS_SAR_LIMIT_LOW(base, limIdx) (((MCPASS_Type *)(base))->SAR.CFG.RANGE_LOW[limIdx])
2707 #define MCPASS_SAR_LIMIT_HIGH(base, limIdx) (((MCPASS_Type *)(base))->SAR.CFG.RANGE_HIGH[limIdx])
2708 #define MCPASS_SAR_AROUTE_STATUS(base) (((MCPASS_Type *)(base))->SAR.CFG.AROUTE_STATUS)
2709 #define MCPASS_SAR_AROUTE_CTRL_MODE(base) (((MCPASS_Type *)(base))->SAR.CFG.AROUTE_CTRL_MODE)
2710 #define MCPASS_SAR_AROUTE_FW_CTRL(base) (((MCPASS_Type *)(base))->SAR.CFG.AROUTE_FW_CTRL)
2711 #define MCPASS_SAR_AROUTE_FW_CTRL_CLR(base) (((MCPASS_Type *)(base))->SAR.CFG.AROUTE_FW_CTRL_CLR)
2712 #define MCPASS_SAR_TEMPSENSE_CTRL(base) (((MCPASS_Type *)(base))->SAR.CFG.TEMPSENSE_CTRL)
2713 #define MCPASS_SAR_SAMP_EN(base) (((MCPASS_Type *)(base))->SAR.CFG.SAMP_EN)
2714 #define MCPASS_SAR_SAMP_GAIN(base) (((MCPASS_Type *)(base))->SAR.CFG.SAMP_GAIN)
2715 #define MCPASS_SAR_SAMPLE_TIME(base, timIdx) (((MCPASS_Type *)(base))->SAR.CFG.SAMPLE_TIME[timIdx])
2716 #define MCPASS_SAR_CHAN_CFG(base, chanIdx) (((MCPASS_Type *)(base))->SAR.CFG.CHAN_CFG[chanIdx])
2717 #define MCPASS_SAR_CHAN_COEFF(base, coefIdx) (((MCPASS_Type *)(base))->SAR.CFG.CHAN_COEFF[coefIdx])
2718 #define MCPASS_SAR_FIR_CFG(base, firIdx) (((MCPASS_Type *)(base))->SAR.CFG.FIR_CFG[firIdx])
2719 #define MCPASS_SAR_SEQ_GROUP(base, grpIdx) (((MCPASS_Type *)(base))->SAR.SEQ_ENTRY[grpIdx])
2720 #define MCPASS_SAR_FIR_COEFS(base, firIdx, coefIdx) (((MCPASS_Type *)(base))->SAR.FIR[firIdx].FIR_COEFS[coefIdx])
2721 #define MCPASS_CSG_SLICE_CMP_CFG(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].CMP_CFG)
2722 #define MCPASS_CSG_SLICE_DAC_CFG(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_CFG)
2723 #define MCPASS_CSG_SLICE_DAC_PARAM_SYNC(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_PARAM_SYNC)
2724 #define MCPASS_CSG_SLICE_DAC_MODE_START(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_MODE_START)
2725 #define MCPASS_CSG_SLICE_DAC_VAL_A(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_VAL_A)
2726 #define MCPASS_CSG_SLICE_DAC_VAL_B(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_VAL_B)
2727 #define MCPASS_CSG_SLICE_DAC_PERIOD(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_PERIOD)
2728 #define MCPASS_CSG_SLICE_DAC_VAL(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_VAL)
2729 #define MCPASS_CSG_SLICE_DAC_STATUS(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].DAC_STATUS)
2730 #define MCPASS_CSG_SLICE_CMP_STATUS(base, slcIdx) (((MCPASS_Type *)(base))->CSG.SLICE[slcIdx].CMP_STATUS)
2731 #define MCPASS_CSG_LUT_CFG(base, lutIdx, dataIdx) (((MCPASS_Type *)(base))->CSG.LUT_CFG[lutIdx].LUT_DATA[dataIdx])
2732 #define MCPASS_CSG_CTRL(base) (((MCPASS_Type *)(base))->CSG.CSG_CTRL)
2733 #define MCPASS_CSG_DAC_INTR(base) (((MCPASS_Type *)(base))->CSG.DAC_INTR)
2734 #define MCPASS_CSG_DAC_INTR_SET(base) (((MCPASS_Type *)(base))->CSG.DAC_INTR_SET)
2735 #define MCPASS_CSG_DAC_INTR_MASK(base) (((MCPASS_Type *)(base))->CSG.DAC_INTR_MASK)
2736 #define MCPASS_CSG_DAC_INTR_MASKED(base) (((MCPASS_Type *)(base))->CSG.DAC_INTR_MASKED)
2737 #define MCPASS_CSG_CMP_INTR(base) (((MCPASS_Type *)(base))->CSG.CMP_INTR)
2738 #define MCPASS_CSG_CMP_INTR_SET(base) (((MCPASS_Type *)(base))->CSG.CMP_INTR_SET)
2739 #define MCPASS_CSG_CMP_INTR_MASK(base) (((MCPASS_Type *)(base))->CSG.CMP_INTR_MASK)
2740 #define MCPASS_CSG_CMP_INTR_MASKED(base) (((MCPASS_Type *)(base))->CSG.CMP_INTR_MASKED)
2741
2742 #define MCPASS_SAR_GROUP_TR_COLLISION(base) (((MCPASS_Type *)(base))->SAR.CFG.ENTRY_TR_COLLISION)
2743 #define MCPASS_INFRA_TR_IN_SEL(base) (((MCPASS_Type *)(base))->INFRA.TR_IN_SEL)
2744 #define MCPASS_INFRA_HW_TR_MODE(base) (((MCPASS_Type *)(base))->INFRA.HW_TR_MODE)
2745 #define MCPASS_INFRA_FW_TR_PULSE(base) (((MCPASS_Type *)(base))->INFRA.FW_TR_PULSE)
2746 #define MCPASS_INFRA_FW_TR_LEVEL(base) (((MCPASS_Type *)(base))->INFRA.FW_TR_LEVEL)
2747 #define MCPASS_INFRA_CLOCK_STARTUP_DIV(base) (((MCPASS_Type *)(base))->INFRA.CLOCK_STARTUP_DIV)
2748 #define MCPASS_INFRA_STARTUP_CFG(base, cfg) (((MCPASS_Type *)(base))->INFRA.STARTUP_CFG[cfg])
2749 #define MCPASS_INFRA_AREF_CTRL(base) (((MCPASS_Type *)(base))->INFRA.AREFV2.AREF_CTRL)
2750 #define MCPASS_INFRA_VDDA_STATUS(base) (((MCPASS_Type *)(base))->INFRA.VDDA_STATUS)
2751
2752 #define CY_HPPASS_FIFO_RD_DATA_RESULT_Pos (0UL)
2753 #define CY_HPPASS_FIFO_RD_DATA_RESULT_Msk (0xFFFFUL)
2754
2755 #define CY_HPPASS_FIFO_RD_DATA_CHAN_ID_Pos (16UL)
2756 #define CY_HPPASS_FIFO_RD_DATA_CHAN_ID_Msk (0x1F0000UL)
2757 #endif
2758
2759 CY_MISRA_BLOCK_END('MISRA C-2012 Rule 8.6')
2760
2761 #endif /* CY_DEVICE_H_ */
2762
2763 /* [] END OF FILE */
2764
2765
