Home
last modified time | relevance | path

Searched refs:Cy_SysClk_PllIsEnabled (Results 1 – 9 of 9) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_utils_impl.c703 Cy_SysClk_PllIsEnabled(sources[i]->channel_num)) in _cyhal_utils_find_hf_source_n_divider()
708 Cy_SysClk_PllIsEnabled(sources[i]->channel_num)) in _cyhal_utils_find_hf_source_n_divider()
713 Cy_SysClk_PllIsEnabled(sources[i]->channel_num)) in _cyhal_utils_find_hf_source_n_divider()
Dcyhal_clock.c1590 return Cy_SysClk_PllIsEnabled(clock->channel + 1 + SRSS_NUM_PLL400M); in _cyhal_clock_is_enabled_pll()
1595 return Cy_SysClk_PllIsEnabled(clock->channel + 1 + SRSS_NUM_DPLL_LP); in _cyhal_clock_is_enabled_pll()
1598 return Cy_SysClk_PllIsEnabled(clock->channel + 1); in _cyhal_clock_is_enabled_pll()
1726 bool enabled = Cy_SysClk_PllIsEnabled(pll_idx); in _cyhal_clock_set_frequency_pll()
Dcyhal_usb_dev.c295 …if ( Cy_SysClk_PllIsEnabled(path) && (CY_SYSCLK_CLKPATH_IN_IMO == Cy_SysClk_ClkPathGetSource(path)… in _cyhal_usb_dev_hf_clock_setup()
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c1432 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) in Cy_PRA_ValidateAllPLL()
1446 if (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) in Cy_PRA_ValidateAllPLL()
2830 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1)) in Cy_PRA_SystemConfig()
2851 if((devConfig->pll0Enable) && (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_1))) in Cy_PRA_SystemConfig()
2874 if(Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2)) in Cy_PRA_SystemConfig()
2895 if((devConfig->pll1Enable) && (!Cy_SysClk_PllIsEnabled(CY_PRA_CLKPLL_2))) in Cy_PRA_SystemConfig()
Dcy_sysclk.c1776 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) in Cy_SysClk_PllIsEnabled() function
1919 else if (Cy_SysClk_PllIsEnabled(clkPath)) in Cy_SysClk_PllManualConfigure()
2555 if ((0UL == fllpll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllpll)) in Cy_SysClk_DeepSleepCallback()
2852 …enabled = (Cy_SysClk_PllIsEnabled(clkPath)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode… in Cy_SysClk_PllGetFrequency()
Dcy_syspm_v2.c318 if(Cy_SysClk_PllIsEnabled(1U)) in Cy_SysPm_SystemLpActiveEnter()
323 if(Cy_SysClk_PllIsEnabled(2U)) in Cy_SysPm_SystemLpActiveEnter()
Dcy_sysclk_v2.c3313 … if (clkPath < (CY_SRSS_NUM_PLL) && Cy_SysClk_PllIsEnabled(clkPath)) /* PLL? (always path 1...N)*/ in Cy_SysClk_ClkPathGetFrequency()
3327 else if ((clkPath != 0UL) && (clkPath <= (CY_SRSS_NUM_PLL)) && Cy_SysClk_PllIsEnabled(clkPath)) in Cy_SysClk_ClkPathGetFrequency()
3341 …else if ((clkPath > 0UL) && (clkPath <= CY_SRSS_NUM_PLL) && Cy_SysClk_PllIsEnabled(clkPath)) /* PL… in Cy_SysClk_ClkPathGetFrequency()
5455 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath) in Cy_SysClk_PllIsEnabled() function
Dcy_pra.c2954 if ((0UL == fllPll) ? Cy_SysClk_FllIsEnabled() : Cy_SysClk_PllIsEnabled(fllPll)) in Cy_PRA_ClkDSBeforeTransition()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2891 bool Cy_SysClk_PllIsEnabled(uint32_t clkPath);