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Searched refs:CY_SYSLIB_DIV_ROUNDUP (Results 1 – 10 of 10) sorted by relevance

/hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM4/
Dsystem_psoc6_cm4.c100 uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESH…
102 uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1…
251 cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); in SystemCoreClockUpdate()
252 cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); in SystemCoreClockUpdate()
/hal_infineon-latest/mtb-template-cat1/files/templates/cat1a/COMPONENT_MTB/COMPONENT_CM0P/
Dsystem_psoc6_cm0plus.c113 uint32_t cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1K_THRESH…
115 uint8_t cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(CY_CLK_SYSTEM_FREQ_HZ_DEFAULT, CY_DELAY_1…
257 cy_delayFreqMhz = (uint8_t)CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1M_THRESHOLD); in SystemCoreClockUpdate()
258 cy_delayFreqKhz = CY_SYSLIB_DIV_ROUNDUP(SystemCoreClock, CY_DELAY_1K_THRESHOLD); in SystemCoreClockUpdate()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_seglcd.h441 #define CY_SEGLCD_14SEG_FONTMAP_SIZE (CY_SYSLIB_DIV_ROUNDUP(CY_SEGLCD_14SEG, CY_SEGLCD_OCTET)…
442 #define CY_SEGLCD_16SEG_FONTMAP_SIZE (CY_SYSLIB_DIV_ROUNDUP(CY_SEGLCD_16SEG, CY_SEGLCD_OCTET)…
443 #define CY_SEGLCD_5X8DM_FONTMAP_SIZE (CY_SYSLIB_DIV_ROUNDUP(CY_SEGLCD_5X8DM, CY_SEGLCD_OCTET)…
Dcy_sysclk.h8325 #define CY_SYSCLK_DIV_ROUNDUP(a, b) (CY_SYSLIB_DIV_ROUNDUP((a),(b)))
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c1503 …config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (u… in Cy_SysClk_FllConfigure()
1507 …config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uin… in Cy_SysClk_FllConfigure()
1513 … config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); in Cy_SysClk_FllConfigure()
1586 uint32_t divval = CY_SYSLIB_DIV_ROUNDUP(inputFreq, 1000000UL); in Cy_SysClk_FllConfigure()
1587 … uint32_t altval = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)divval * fref, 6000000ULL) + 1UL; in Cy_SysClk_FllConfigure()
Dcy_seglcd.c780 …int32_t locIdx = _FLD2VAL(CY_SEGLCD_SYM_BYTE_IDX, i) + (locChar * CY_SYSLIB_DIV_ROUNDUP((uint32_t)… in Cy_SegLCD_WriteChar()
Dcy_sysclk_v2.c3477 …config.refDiv = wcoSource ? 19U : (uint16_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)inputFreq * 250ULL, (u… in Cy_SysClk_FllConfigure()
3481 …config.fllMult = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)ccoFreq * (uint64_t)config.refDiv, (uin… in Cy_SysClk_FllConfigure()
3487 … config.lockTolerance = (uint16_t)CY_SYSLIB_DIV_ROUNDUP(config.fllMult * 18939UL, 1000000UL); in Cy_SysClk_FllConfigure()
3556 uint32_t divval = CY_SYSLIB_DIV_ROUNDUP(inputFreq, 1000000UL); in Cy_SysClk_FllConfigure()
3557 … uint32_t altval = (uint32_t)CY_SYSLIB_DIV_ROUNDUP((uint64_t)divval * fref, 6000000ULL) + 1UL; in Cy_SysClk_FllConfigure()
/hal_infineon-latest/core-lib/include/
Dcy_utils.h447 #define CY_SYSLIB_DIV_ROUNDUP(a, b) ((((a) - 1U) / (b)) + 1U) macro
/hal_infineon-latest/core-lib/
DREADME.md38 …* `CY_SYSLIB_DIV_ROUNDUP`: Calculates a / b with rounding up if remainder != 0, both a and b must …
DRELEASE.md34 …* CY_SYSLIB_DIV_ROUNDUP: Calculates a / b with rounding up if remainder != 0, both a and b must be…