Searched refs:CY_SYSINT_INTRSRC_MASK (Results 1 – 3 of 3) sorted by relevance
157 … & CY_SYSINT_INTRSRC_MASK); /* Fetch bit 12-31 to get CPU IRQ value */ in Cy_IPC_Pipe_Init()237 … & CY_SYSINT_INTRSRC_MASK); /* Fetch bit 12-31 to get CPU IRQ value */ in Cy_IPC_Pipe_Init()326 …Type)(((uint32_t)epInterrupt->intrSrc >> CY_SYSINT_INTRSRC_MUXIRQ_SHIFT) & CY_SYSINT_INTRSRC_MASK); in Cy_IPC_Pipe_EndpointInit()412 …Type)(((uint32_t)epInterrupt->intrSrc >> CY_SYSINT_INTRSRC_MUXIRQ_SHIFT) & CY_SYSINT_INTRSRC_MASK); in Cy_IPC_Pipe_EndpointInitExt()
148 …n_intr_t devIntrSrc = (cy_en_intr_t)((uint32_t)config->intrSrc & CY_SYSINT_INTRSRC_MASK); /* Fetch… in Cy_SysInt_Init()186 …n_intr_t devIntrSrc = (cy_en_intr_t)((uint32_t)config->intrSrc & CY_SYSINT_INTRSRC_MASK); /* Fetch… in Cy_SysInt_Init()456 … cy_en_intr_t devIntrSrc = (cy_en_intr_t)((uint32_t) config->intrSrc & CY_SYSINT_INTRSRC_MASK); in Cy_SysInt_InitExtIRQ()
450 #define CY_SYSINT_INTRSRC_MASK (0xFFFFUL) /**< Bit 0-15 indicate system interrupt and bi… macro453 #define CY_SYSINT_INTRSRC_MASK (0x0FFFUL) /**< Bit 0-11 indicate system interrupt and bi… macro
