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Searched refs:CY_SYSCLK_FLLPLL_OUTPUT_INPUT (Results 1 – 6 of 6) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c1459 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_FllDisable()
1483 if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_FllConfigure()
1598 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_FllConfigure()
1706 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_FllEnable()
1820 …R_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_PllDisable()
1847 if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_PllConfigure()
1942 if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_PllManualConfigure()
2003 …if ((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT == (uint32_t)_FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, … in Cy_SysClk_PllEnable()
2013 …R_SET(SRSS_CLK_PLL_CONFIG[clkPath], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_PllEnable()
2563 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_DeepSleepCallback()
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Dcy_sysclk_v2.c3404 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_FllDisable()
3407 …for (; (((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT) != _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRS… in Cy_SysClk_FllDisable()
3457 if (outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_FllConfigure()
3568 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_FllConfigure()
3687 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_FllEnable()
3733 enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); in Cy_SysClk_FllGetFrequency()
3968 …ET(SRSS_CLK_PLL_400M_CONFIG(pllNum), CLK_PLL400M_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_SysClk_Pll400MDisable()
4004 if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_Pll400MConfigure()
4101 if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in Cy_SysClk_Pll400MManualConfigure()
4193 …if ((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT == (uint32_t)_FLD2VAL(CLK_PLL400M_CONFIG_BYPASS_SEL, S… in Cy_SysClk_Pll400MEnable()
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Dcy_pra_cfg.c691 … if ((devConfig->fllEnable) && (devConfig->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)) in Cy_PRA_GetInputSourceFreq()
709 …KPLL_1) && (devConfig->pll0Enable) && (devConfig->pll0OutputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)) in Cy_PRA_GetInputSourceFreq()
727 …KPLL_2) && (devConfig->pll1Enable) && (devConfig->pll1OutputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)) in Cy_PRA_GetInputSourceFreq()
Dcy_pra.c2962 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_PRA_ClkDSBeforeTransition()
2972 …(SRSS_CLK_PLL_CONFIG[fllPll - 1UL], SRSS_CLK_PLL_CONFIG_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_PRA_ClkDSBeforeTransition()
2983 …EG32_CLR_SET(SRSS_CLK_FLL_CONFIG3, SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, CY_SYSCLK_FLLPLL_OUTPUT_INPUT); in Cy_PRA_ClkDSBeforeTransition()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_usb_dev.c273 if (pll_config.outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT) in _cyhal_usb_dev_get_pll_freq()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2176 … CY_SYSCLK_FLLPLL_OUTPUT_INPUT = 2U, /**< Output FLL/PLL input source regardless of lock status */ enumerator