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Searched refs:CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_sysclk.h2175 CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 = 1U, /**< Same as AUTO */ enumerator
/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysclk.c2568 …((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_… in Cy_SysClk_DeepSleepCallback()
Dcy_pra.c2967 …((uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS_CLK_PLL_… in Cy_PRA_ClkDSBeforeTransition()