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Searched refs:CY_SRSS_NUM_CLKPATH (Results 1 – 7 of 7) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_pra_cfg.c679 if(clkPath >= CY_SRSS_NUM_CLKPATH) in Cy_PRA_GetInputSourceFreq()
926 if(clkPath >= CY_SRSS_NUM_CLKPATH) in Cy_PRA_GetInputSourceClock()
1592 if(clkPath >= CY_SRSS_NUM_CLKPATH) in Cy_PRA_ValidateClkPath()
1684 …if ((devConfig->path0Enable) && (CY_PRA_CLKPATH_0 < CY_SRSS_NUM_CLKPATH)) /* path_mux0 is enabled … in Cy_PRA_ValidateAllClkPathMux()
1691 …if ((devConfig->path1Enable) && (CY_PRA_CLKPATH_1 < CY_SRSS_NUM_CLKPATH)) /* path_mux1 is enabled … in Cy_PRA_ValidateAllClkPathMux()
1698 …if ((devConfig->path2Enable) && (CY_PRA_CLKPATH_2 < CY_SRSS_NUM_CLKPATH)) /* path_mux2 is enabled … in Cy_PRA_ValidateAllClkPathMux()
1705 …if ((devConfig->path3Enable) && (CY_PRA_CLKPATH_3 < CY_SRSS_NUM_CLKPATH)) /* path_mux3 is enabled … in Cy_PRA_ValidateAllClkPathMux()
1712 …if ((devConfig->path4Enable) && (CY_PRA_CLKPATH_4 < CY_SRSS_NUM_CLKPATH)) /* path_mux4 is enabled … in Cy_PRA_ValidateAllClkPathMux()
1719 …if ((devConfig->path5Enable) && (CY_PRA_CLKPATH_5 < CY_SRSS_NUM_CLKPATH))/* path_mux5 is enabled */ in Cy_PRA_ValidateAllClkPathMux()
2739 if ((devConfig->path3Enable) && (CY_PRA_CLKPATH_3 < CY_SRSS_NUM_CLKPATH)) in Cy_PRA_SystemConfig()
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Dcy_sysclk.c1295 if ((clkPath < CY_SRSS_NUM_CLKPATH) && in Cy_SysClk_ClkPathSetSource()
1326 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_ClkPathGetSource()
1340 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_ClkPathMuxGetFrequency()
1390 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_ClkPathGetFrequency()
2845 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_PllGetFrequency()
Dcy_sysclk_v2.c3181 if (clkPath < CY_SRSS_NUM_CLKPATH) in Cy_SysClk_ClkPathSetSource()
3199 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_ClkPathGetSource()
3212 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_ClkPathMuxGetFrequency()
3307 CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); in Cy_SysClk_ClkPathGetFrequency()
/hal_infineon-latest/bless/
Dcy_ble_hal_pvt.c653 for(i = 0U; i < CY_SRSS_NUM_CLKPATH; i++) in Cy_BLE_HAL_IsEcoCpuClockSrc()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h309 #define CY_SRSS_NUM_CLKPATH (SRSS_NUM_CLKPATH) macro
482 #define CY_SRSS_NUM_CLKPATH ((uint32_t)(cy_device->srssNumClkpath)) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h125 #define CY_SRSS_NUM_CLKPATH SRSS_NUM_CLKPATH macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h941 #define CY_SRSS_NUM_CLKPATH SRSS_NUM_CLKPATH macro