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Searched refs:CY_SCB_TX_INTR_LEVEL (Results 1 – 8 of 8) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_scb_spi.c710 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_SPI_Transfer()
724 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW); in Cy_SCB_SPI_Transfer()
881 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_SPI_Transfer_Buffer()
895 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW); in Cy_SCB_SPI_Transfer_Buffer()
1096 if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base))) in Cy_SCB_SPI_Interrupt()
1100 Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_SPI_Interrupt()
1270 …SCB_SetTxInterruptMask(base, (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL)); in HandleTransmit()
Dcy_scb_uart.c1142 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_UART_Transmit()
1404 if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base))) in Cy_SCB_UART_Interrupt()
1408 Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_UART_Interrupt()
1663 (Cy_SCB_GetTxInterruptMask(base) & (uint32_t) ~CY_SCB_TX_INTR_LEVEL))); in HandleDataTransmit()
Dcy_scb_ezi2c.c847 if (0UL != (CY_SCB_TX_INTR_LEVEL & Cy_SCB_GetTxInterruptStatusMasked(base))) in Cy_SCB_EZI2C_Interrupt()
851 Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_EZI2C_Interrupt()
966 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); in HandleAddress()
Dcy_scb_i2c.c1565 Cy_SCB_SetTxInterruptMask (base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_I2C_MasterWrite()
2280 Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_I2C_SlaveInterrupt()
2495 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); in SlaveHandleAddress()
2650 Cy_SCB_SetTxInterruptMask(base, CY_SCB_TX_INTR_LEVEL); in SlaveHandleDataTransmit()
2868 Cy_SCB_ClearTxInterrupt(base, CY_SCB_TX_INTR_LEVEL); in Cy_SCB_I2C_MasterInterrupt()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_scb_common.h527 #define CY_SCB_TX_INTR_LEVEL SCB_INTR_TX_TRIGGER_Msk macro
812 #define CY_SCB_TX_INTR_MASK (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_NOT_FULL | CY_SCB_TX_IN…
Dcy_scb_i2c.h1032 #define CY_SCB_I2C_SLAVE_INTR_TX (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UNDERFLOW)
Dcy_scb_uart.h923 #define CY_SCB_UART_TX_INTR (CY_SCB_TX_INTR_LEVEL | CY_SCB_TX_INTR_UART_NACK | CY_SCB_TX_INT…
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_uart.c304 …Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) & ~CY_SCB_TX_INTR_LEVEL); in _cyhal_uart_dma_handler_tx()