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Searched refs:CY_SCB_SPI_CPHA0_CPOL0 (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_scb_spi.h366 CY_SCB_SPI_CPHA0_CPOL0 = 0U, /**< Clock is active low, data is changed on first edge */ enumerator
902 #define CY_SCB_SPI_IS_SCLK_MODE_VALID(clkMode) ( (CY_SCB_SPI_CPHA0_CPOL0 == (clkMode)) || \
1571 retVal = (uint32_t) CY_SCB_SPI_CPHA0_CPOL0; in CY_SCB_SPI_GetSclkMode()
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_spi.c98 .sclkMode = CY_SCB_SPI_CPHA0_CPOL0,
413 return (CY_SCB_SPI_CPHA0_CPOL0); in _cyhal_convert_mode_sclk()