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Searched refs:CY_PDM_PCM_CLK_CTL_DEFAULT (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_pdm_pcm_v2.c306 PDM_PCM_CLOCK_CTL(base) = CY_PDM_PCM_CLK_CTL_DEFAULT; /* The default clock settings */ in Cy_PDM_PCM_DeInit()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_pdm_pcm_v2.h461 #define CY_PDM_PCM_CLK_CTL_DEFAULT (_VAL2FLD(PDM_CLOCK_CTL_CLOCK_DIV, PDM_CLOCK_CTL_CLOCK_DIV_DEFAU… macro