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Searched refs:CY_HSIOM_BASE (Results 1 – 5 of 5) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c264 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); in Cy_GPIO_Port_Init()
600 baseHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); in Cy_GPIO_Port_Deinit()
826 portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); in Cy_GPIO_SetHSIOM()
999 portAddrHSIOM = (HSIOM_PRT_V1_Type*)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); in Cy_GPIO_GetHSIOM()
Dcy_pra.c361 portAddrHSIOM = (volatile uint32_t *)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); in Cy_PRA_InitHsiomPort()
414 portAddrHSIOM = (volatile uint32_t *)(CY_HSIOM_BASE + (HSIOM_PRT_SECTION_SIZE * portNum)); in Cy_PRA_InitAdjHsiomPort()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h1462 #define CY_HSIOM_BASE ((uint32_t)(cy_device->hsiomBase)) macro
1467 #define HSIOM_AMUX_SPLIT_CTL(switchCtrl) (((HSIOM_Type *) CY_HSIOM_BASE)->AMUX_SPLIT_CTL[switchCt…
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h1995 #define CY_HSIOM_BASE ((uint32_t)HSIOM_BASE) macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1B/include/
Dcy_device.h576 #define CY_HSIOM_BASE ((uint32_t)HSIOM_BASE) macro