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Searched refs:CY_GPIO_HSIOM_OFFSET (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c844 …X(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
851 …X(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
855 …g = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
864 …g = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
866 … hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
907 …X(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
914 …X(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
918 …g = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
927 …g = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
930 … hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
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Dcy_pra.c370 …PRT_V1_Type, PORT_SEL0), 4U)].writeMask = (CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_PRA_InitHsiomPort()
375 …PRT_V1_Type, PORT_SEL1), 4U)].writeMask = (CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_PRA_InitHsiomPort()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_gpio.h453 #define CY_GPIO_HSIOM_OFFSET (3UL) /**< Offset for HSIOM */ macro