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Searched refs:CY_GPIO_HSIOM_MASK (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c844 …Y_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum <… in Cy_GPIO_SetHSIOM()
851 …RA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT0)) & ~(CY_GPIO_HSIOM_MASK << (pinNum <… in Cy_GPIO_SetHSIOM()
855 …tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OF… in Cy_GPIO_SetHSIOM()
864 …tempReg = HSIOM_PRT_PORT_SEL0(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OF… in Cy_GPIO_SetHSIOM()
866 … hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
907 …Y_PRA_GET_HSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum <… in Cy_GPIO_SetHSIOM()
914 …RA_GET_ADJHSIOM_REG_INDEX(base, CY_PRA_SUB_INDEX_HSIOM_PORT1)) & ~(CY_GPIO_HSIOM_MASK << (pinNum <… in Cy_GPIO_SetHSIOM()
918 …tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OF… in Cy_GPIO_SetHSIOM()
927 …tempReg = HSIOM_PRT_PORT_SEL1(portAddrHSIOM) & ~(CY_GPIO_HSIOM_MASK << (pinNum << CY_GPIO_HSIOM_OF… in Cy_GPIO_SetHSIOM()
930 … hsiomReg = tempReg | (((uint32_t)value & CY_GPIO_HSIOM_MASK) << (pinNum << CY_GPIO_HSIOM_OFFSET)); in Cy_GPIO_SetHSIOM()
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Dcy_pra.c370 …IV_ROUND(offsetof(HSIOM_PRT_V1_Type, PORT_SEL0), 4U)].writeMask = (CY_GPIO_HSIOM_MASK << (pinNum <… in Cy_PRA_InitHsiomPort()
375 …IV_ROUND(offsetof(HSIOM_PRT_V1_Type, PORT_SEL1), 4U)].writeMask = (CY_GPIO_HSIOM_MASK << (pinNum <… in Cy_PRA_InitHsiomPort()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_gpio.h403 #define CY_GPIO_HSIOM_MASK (0x1FUL) /**< HSIOM selection mask */ macro
511 #define CY_GPIO_IS_HSIOM_VALID(hsiom) (0U == ((hsiom) & (uint32_t)~CY_GPIO_HSIOM_MASK))