Searched refs:CY_BLE_ALIGN_TO_4 (Results 1 – 3 of 3) sorted by relevance
111 #define CY_BLE_ALIGN_TO_4(x) ((((x) & 3u) == 0u) ? (x) : (((x) - ((x) & 3u)) + 4… macro204 …#define CY_BLE_L2CAP_Q_HEAP (CY_BLE_ALIGN_TO_4(CY_BLE_L2CAP_Q_DEPTH_PER_CONN *…211 …#define CY_BLE_GATT_MTU_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4(CY_BLE_GATT_MTU + CY_BLE_MEM_EX…219 … (CY_BLE_ALIGN_TO_4(CY_BLE_GATT_MAX_ATTR_LEN + CY_BLE_MEM_EXT_SZ + \244 CY_BLE_ALIGN_TO_4(CY_BLE_GATT_PREPARE_LENGTH))267 #define CY_BLE_L2CAP_MTU_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4(CY_BLE_L2CAP_MTU + \269 …#define CY_BLE_L2CAP_MPS_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4(CY_BLE_L2CAP_MPS + CY_BLE_MEM_E…271 …#define CY_BLE_L2CAP_PSM_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4((CY_BLE_L2CAP_PSM_SIZE + CY_BLE…273 …#define CY_BLE_L2CAP_CBFC_PLUS_L2CAP_MEM_EXT (CY_BLE_ALIGN_TO_4((CY_BLE_L2CAP_CBFC_CHANNEL_SIZE…311 #define CY_BLE_LL_MAX_TX_PAYLOAD_BUFFER_SZ CY_BLE_ALIGN_TO_4(CY_BLE_LL_MAX_TX_PAYLOAD_SIZE)[all …]
70 #define CY_BLE_ALIGN_TO_4(x) ((((x) & 3u) == 0u) ? (x) : (((x) - ((x) & 3u)) + 4u)) macro
273 uint16_t dataBuffIdx0 = CY_BLE_ALIGN_TO_4(cy_ble_configPtr->params->mtuSize + in Cy_BLE_EnableHost()277 uint16_t dataBuffIdx1 = CY_BLE_ALIGN_TO_4(cy_ble_configPtr->params->l2capPsmCount * in Cy_BLE_EnableHost()281 uint16_t dataBuffIdx2 = CY_BLE_ALIGN_TO_4(cy_ble_configPtr->params->l2capChanCount * in Cy_BLE_EnableHost()285 uint16_t dataBuffIdx3 = CY_BLE_ALIGN_TO_4(cy_ble_configPtr->params->l2capMtuSize + in Cy_BLE_EnableHost()291 uint16_t dataBuffIdx4 = CY_BLE_ALIGN_TO_4((dbInxCount / 8u) + CY_BLE_MEM_EXT_SZ + in Cy_BLE_EnableHost()
