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Searched refs:CY_ASSERT_L3 (Results 1 – 25 of 59) sorted by relevance

123

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_ctb.c305 CY_ASSERT_L3(CY_CTB_DEEPSLEEP(config->deepSleep)); in Cy_CTB_Init()
308 CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa0Power)); in Cy_CTB_Init()
309 CY_ASSERT_L3(CY_CTB_OAMODE(config->oa0Mode)); in Cy_CTB_Init()
310 CY_ASSERT_L3(CY_CTB_OAPUMP(config->oa0Pump)); in Cy_CTB_Init()
311 CY_ASSERT_L3(CY_CTB_COMPEDGE(config->oa0CompEdge)); in Cy_CTB_Init()
312 CY_ASSERT_L3(CY_CTB_COMPLEVEL(config->oa0CompLevel)); in Cy_CTB_Init()
313 CY_ASSERT_L3(CY_CTB_COMPBYPASS(config->oa0CompBypass)); in Cy_CTB_Init()
314 CY_ASSERT_L3(CY_CTB_COMPHYST(config->oa0CompHyst)); in Cy_CTB_Init()
317 CY_ASSERT_L3(CY_CTB_OAPOWER(config->oa1Power)); in Cy_CTB_Init()
318 CY_ASSERT_L3(CY_CTB_OAMODE(config->oa1Mode)); in Cy_CTB_Init()
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Dcy_lpcomp.c98 CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); in Cy_LPComp_Init_Ext()
99 CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode)); in Cy_LPComp_Init_Ext()
100 CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis)); in Cy_LPComp_Init_Ext()
101 CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(config->power)); in Cy_LPComp_Init_Ext()
102 CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(config->intType)); in Cy_LPComp_Init_Ext()
168 CY_ASSERT_L3(CY_LPCOMP_IS_CHANNEL_VALID(channel)); in Cy_LPComp_Init()
169 CY_ASSERT_L3(CY_LPCOMP_IS_OUT_MODE_VALID(config->outputMode)); in Cy_LPComp_Init()
170 CY_ASSERT_L3(CY_LPCOMP_IS_HYSTERESIS_VALID(config->hysteresis)); in Cy_LPComp_Init()
171 CY_ASSERT_L3(CY_LPCOMP_IS_POWER_VALID(config->power)); in Cy_LPComp_Init()
172 CY_ASSERT_L3(CY_LPCOMP_IS_INTR_MODE_VALID(config->intType)); in Cy_LPComp_Init()
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Dcy_pdm_pcm.c59 CY_ASSERT_L3(CY_PDM_PCM_IS_CLK_DIV_VALID(config->clkDiv)); in Cy_PDM_PCM_Init()
60 CY_ASSERT_L3(CY_PDM_PCM_IS_CLK_DIV_VALID(config->mclkDiv)); in Cy_PDM_PCM_Init()
61 CY_ASSERT_L3(CY_PDM_PCM_IS_CKO_CLOCK_DIV_VALID(config->ckoDiv)); in Cy_PDM_PCM_Init()
62 CY_ASSERT_L3(CY_PDM_PCM_IS_SINC_RATE_VALID(config->sincDecRate)); in Cy_PDM_PCM_Init()
63 CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(config->gainRight)); in Cy_PDM_PCM_Init()
64 CY_ASSERT_L3(CY_PDM_PCM_IS_GAIN_VALID(config->gainLeft)); in Cy_PDM_PCM_Init()
65 CY_ASSERT_L3(CY_PDM_PCM_IS_STEP_SEL_VALID(config->softMuteFineGain)); in Cy_PDM_PCM_Init()
66 CY_ASSERT_L3(CY_PDM_PCM_IS_CH_SET_VALID(config->chanSelect)); in Cy_PDM_PCM_Init()
67 CY_ASSERT_L3(CY_PDM_PCM_IS_S_CYCLES_VALID(config->softMuteCycles)); in Cy_PDM_PCM_Init()
68 CY_ASSERT_L3(CY_PDM_PCM_IS_CKO_DELAY_VALID(config->ckoDelay)); in Cy_PDM_PCM_Init()
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Dcy_rtc.c124 CY_ASSERT_L3(CY_RTC_IS_SEC_VALID(dateTime->sec)); in Cy_RTC_SetDateAndTime()
125 CY_ASSERT_L3(CY_RTC_IS_MIN_VALID(dateTime->min)); in Cy_RTC_SetDateAndTime()
126 CY_ASSERT_L3(CY_RTC_IS_HOUR_VALID(dateTime->hour)); in Cy_RTC_SetDateAndTime()
127 CY_ASSERT_L3(CY_RTC_IS_DOW_VALID(dateTime->dayOfWeek)); in Cy_RTC_SetDateAndTime()
128 CY_ASSERT_L3(CY_RTC_IS_MONTH_VALID(dateTime->month)); in Cy_RTC_SetDateAndTime()
129 CY_ASSERT_L3(CY_RTC_IS_YEAR_SHORT_VALID(dateTime->year)); in Cy_RTC_SetDateAndTime()
130 CY_ASSERT_L3(CY_RTC_IS_DATE_VALID(dateTime->date, tmpDaysInMonth)); in Cy_RTC_SetDateAndTime()
131 …CY_ASSERT_L3(CY_RTC_IS_WEEK_DAY_VALID(dateTime->dayOfWeek, Cy_RTC_ConvertDayOfWeek(dateTime->date,… in Cy_RTC_SetDateAndTime()
251 CY_ASSERT_L3(CY_RTC_IS_ALARM_IDX_VALID(alarmIndex)); in Cy_RTC_SetAlarmDateAndTime()
253 CY_ASSERT_L3(CY_RTC_IS_SEC_VALID(alarmDateTime->sec)); in Cy_RTC_SetAlarmDateAndTime()
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Dcy_prot.c279 CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->userPermission)); in Cy_Prot_ConfigMpuStruct()
280 CY_ASSERT_L3(CY_PROT_IS_MPU_PERM_VALID(config->privPermission)); in Cy_Prot_ConfigMpuStruct()
281 CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize)); in Cy_Prot_ConfigMpuStruct()
416 CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->userPermission)); in Cy_Prot_ConfigSmpuMasterStruct()
417 CY_ASSERT_L3(CY_PROT_IS_SMPU_MS_PERM_VALID(config->privPermission)); in Cy_Prot_ConfigSmpuMasterStruct()
488 CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->userPermission)); in Cy_Prot_ConfigSmpuSlaveStruct()
489 CY_ASSERT_L3(CY_PROT_IS_SMPU_SL_PERM_VALID(config->privPermission)); in Cy_Prot_ConfigSmpuSlaveStruct()
490 CY_ASSERT_L3(CY_PROT_IS_REGION_SIZE_VALID(config->regionSize)); in Cy_Prot_ConfigSmpuSlaveStruct()
726 CY_ASSERT_L3(CY_PROT_IS_SMPU_REQ_MODE_VALID(reqMode)); in Cy_Prot_GetSmpuStruct()
973 CY_ASSERT_L3(CY_PROT_IS_PROG_MS_PERM_VALID(userPermission)); in Cy_Prot_ConfigPpuProgMasterAtt()
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Dcy_ctdac.c100 CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); in Cy_CTDAC_Init()
101 CY_ASSERT_L3(CY_CTDAC_FORMAT(config->formatMode)); in Cy_CTDAC_Init()
102 CY_ASSERT_L3(CY_CTDAC_UPDATE(config->updateMode)); in Cy_CTDAC_Init()
103 CY_ASSERT_L3(CY_CTDAC_DEGLITCH(config->deglitchMode)); in Cy_CTDAC_Init()
104 CY_ASSERT_L3(CY_CTDAC_OUTPUTMODE(config->outputMode)); in Cy_CTDAC_Init()
105 CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); in Cy_CTDAC_Init()
106 CY_ASSERT_L3(CY_CTDAC_DEEPSLEEP(config->deepSleep)); in Cy_CTDAC_Init()
313 CY_ASSERT_L3(CY_CTDAC_REFSOURCE(config->refSource)); in Cy_CTDAC_FastInit()
314 CY_ASSERT_L3(CY_CTDAC_OUTPUTBUFFER(config->outputBuffer)); in Cy_CTDAC_FastInit()
462 CY_ASSERT_L3(CY_CTDAC_FORMAT(formatMode)); in Cy_CTDAC_SetSignMode()
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Dcy_dmac.c69 CY_ASSERT_L3(CY_DMAC_IS_RETRIGGER_VALID(config->retrigger)); in Cy_DMAC_Descriptor_Init()
70 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->interruptType)); in Cy_DMAC_Descriptor_Init()
71 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerOutType)); in Cy_DMAC_Descriptor_Init()
72 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(config->triggerInType)); in Cy_DMAC_Descriptor_Init()
73 CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->srcTransferSize)); in Cy_DMAC_Descriptor_Init()
74 CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(config->dstTransferSize)); in Cy_DMAC_Descriptor_Init()
75 CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(config->channelState)); in Cy_DMAC_Descriptor_Init()
76 CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(config->dataSize)); in Cy_DMAC_Descriptor_Init()
77 CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(config->descriptorType)); in Cy_DMAC_Descriptor_Init()
461 CY_ASSERT_L3(CY_DMAC_IS_TYPE_VALID(descriptorType)); in Cy_DMAC_Descriptor_SetDescriptorType()
Dcy_sysanalog.c106 CY_ASSERT_L3(CY_SYSANALOG_DEEPSLEEP(config->deepSleep)); in Cy_SysAnalog_Init()
107 CY_ASSERT_L3(CY_SYSANALOG_VREF(config->vref)); in Cy_SysAnalog_Init()
108 CY_ASSERT_L3(CY_SYSANALOG_IZTAT(config->iztat)); in Cy_SysAnalog_Init()
158 CY_ASSERT_L3(IS_DSMODE_VALID(config->lpOscDsMode)); in Cy_SysAnalog_DeepSleepInit()
159 CY_ASSERT_L3(IS_SRC_VALID(config->dsClkSource)); in Cy_SysAnalog_DeepSleepInit()
160 CY_ASSERT_L3(IS_DIV_VALID(config->dsClkdivider)); in Cy_SysAnalog_DeepSleepInit()
161 CY_ASSERT_L3(IS_TMR_CLK_VALID(config->timerClock)); in Cy_SysAnalog_DeepSleepInit()
Dcy_dma.c113 CY_ASSERT_L3(CY_DMA_IS_RETRIG_VALID(config->retrigger)); in Cy_DMA_Descriptor_Init()
114 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->interruptType)); in Cy_DMA_Descriptor_Init()
115 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerOutType)); in Cy_DMA_Descriptor_Init()
116 CY_ASSERT_L3(CY_DMA_IS_TRIG_TYPE_VALID(config->triggerInType)); in Cy_DMA_Descriptor_Init()
117 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->srcTransferSize)); in Cy_DMA_Descriptor_Init()
118 CY_ASSERT_L3(CY_DMA_IS_XFER_SIZE_VALID(config->dstTransferSize)); in Cy_DMA_Descriptor_Init()
119 CY_ASSERT_L3(CY_DMA_IS_CHANNEL_STATE_VALID(config->channelState)); in Cy_DMA_Descriptor_Init()
120 CY_ASSERT_L3(CY_DMA_IS_DATA_SIZE_VALID(config->dataSize)); in Cy_DMA_Descriptor_Init()
121 CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(config->descriptorType)); in Cy_DMA_Descriptor_Init()
436 CY_ASSERT_L3(CY_DMA_IS_TYPE_VALID(descriptorType)); in Cy_DMA_Descriptor_SetDescriptorType()
Dcy_sysfault.c71 CY_ASSERT_L3(CY_SYSFAULT_IS_DATA_SET_VALID(dataSet)); in Cy_SysFault_GetFaultData()
79 CY_ASSERT_L3(CY_SYSFAULT_IS_FAULT_SET_VALID(pendingFault)); in Cy_SysFault_GetPendingFault()
104 CY_ASSERT_L3(0); in Cy_SysFault_GetPendingFault()
114 CY_ASSERT_L3(idx < CY_SYSFAULT_NO_FAULT); in Cy_SysFault_SetMaskByIdx()
138 CY_ASSERT_L3(0); in Cy_SysFault_SetMaskByIdx()
147 CY_ASSERT_L3(idx < CY_SYSFAULT_NO_FAULT); in Cy_SysFault_ClearMaskByIdx()
171 CY_ASSERT_L3(0); in Cy_SysFault_ClearMaskByIdx()
Dcy_i2s.c83 CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->txAlignment)); in Cy_I2S_Init()
84 CY_ASSERT_L3(CY_I2S_IS_OVHDATA_VALID(config->txOverheadValue)); in Cy_I2S_Init()
93 CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); in Cy_I2S_Init()
94 CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->txWordLength)); in Cy_I2S_Init()
102 CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->txWordLength)); in Cy_I2S_Init()
125 CY_ASSERT_L3(CY_I2S_IS_ALIGNMENT_VALID(config->rxAlignment)); in Cy_I2S_Init()
134 CY_ASSERT_L3(CY_I2S_IS_WSPULSE_VALID(wsPulseWidth)); in Cy_I2S_Init()
135 CY_ASSERT_L3(CY_I2S_IS_LEN_VALID(config->rxWordLength)); in Cy_I2S_Init()
143 CY_ASSERT_L3(CY_I2S_IS_CHAN_WORD_VALID(channelLength, config->rxWordLength)); in Cy_I2S_Init()
Dcy_axidmac.c50 CY_ASSERT_L3(CY_AXIDMAC_IS_RETRIGGER_VALID(config->retrigger)); in Cy_AXIDMAC_Descriptor_Init()
51 CY_ASSERT_L3(CY_AXIDMAC_IS_TRIG_TYPE_VALID(config->interruptType)); in Cy_AXIDMAC_Descriptor_Init()
52 CY_ASSERT_L3(CY_AXIDMAC_IS_TRIG_TYPE_VALID(config->triggerOutType)); in Cy_AXIDMAC_Descriptor_Init()
53 CY_ASSERT_L3(CY_AXIDMAC_IS_TRIG_TYPE_VALID(config->triggerInType)); in Cy_AXIDMAC_Descriptor_Init()
54 CY_ASSERT_L3(CY_AXIDMAC_IS_CHANNEL_STATE_VALID(config->channelState)); in Cy_AXIDMAC_Descriptor_Init()
55 CY_ASSERT_L3(CY_AXIDMAC_IS_TYPE_VALID(config->descriptorType)); in Cy_AXIDMAC_Descriptor_Init()
315 CY_ASSERT_L3(CY_AXIDMAC_IS_TYPE_VALID(descriptorType)); in Cy_AXIDMAC_Descriptor_SetDescriptorType()
Dcy_syspm_v2.c216 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterSleep()
567 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterDeepSleep()
568 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx)); in Cy_SysPm_CpuEnterDeepSleep()
659 CY_ASSERT_L3(CY_SYSPM_IS_DSRAM_CHECK_VALID(dsramCheck)); in Cy_SysPm_SetupDeepSleepRAM()
660 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx)); in Cy_SysPm_SetupDeepSleepRAM()
893 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode)); in Cy_SysPm_LdoSetMode()
1145 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_SetHibernateWakeupSource()
1216 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_ClearHibernateWakeupSource()
1846 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type)); in Cy_SysPm_ExecuteCallback()
1847 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode)); in Cy_SysPm_ExecuteCallback()
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Dcy_syspm_v4.c184 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterSleep()
638 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterDeepSleep()
639 CY_ASSERT_L3(CY_SYSPM_IS_DEEPSLEEP_MODE_VALID(cbDeepSleepRootIdx)); in Cy_SysPm_CpuEnterDeepSleep()
871 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode)); in Cy_SysPm_LdoSetMode()
929 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_SetHibernateWakeupSource()
1000 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_ClearHibernateWakeupSource()
1507 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type)); in Cy_SysPm_ExecuteCallback()
1508 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode)); in Cy_SysPm_ExecuteCallback()
1672 …CY_ASSERT_L3((socmemSramPwrMode == CY_SYSPM_SOCMEM_SRAM_ACTIVE_MODE_ON) || (socmemSramPwrMode == C… in Cy_SysPm_SetSOCMemPartActivePwrMode()
1673 CY_ASSERT_L3(socmemSramPartNum < CY_SOCMEM_PARTITION_NR); in Cy_SysPm_SetSOCMemPartActivePwrMode()
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Dcy_smif.c113 CY_ASSERT_L3(CY_SMIF_MODE_VALID(config->mode)); in Cy_SMIF_Init()
114 CY_ASSERT_L3(CY_SMIF_CLOCK_SEL_VALID(config->rxClockSel)); in Cy_SMIF_Init()
116 CY_ASSERT_L3(CY_SMIF_BLOCK_EVENT_VALID(config->blockEvent)); in Cy_SMIF_Init()
277 CY_ASSERT_L3(CY_SMIF_MODE_VALID(mode)); in Cy_SMIF_SetMode()
370 CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(slaveSelect)); in Cy_SMIF_SetDataSelect()
371 CY_ASSERT_L3(CY_SMIF_DATA_SEL_VALID(dataSelect)); in Cy_SMIF_SetDataSelect()
472 CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(cmdTxfrWidth)); in Cy_SMIF_TransmitCommand()
473 CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(paramTxfrWidth)); in Cy_SMIF_TransmitCommand()
474 CY_ASSERT_L3(CY_SMIF_SLAVE_SEL_VALID(slaveSelect)); in Cy_SMIF_TransmitCommand()
591 CY_ASSERT_L3(CY_SMIF_TXFR_WIDTH_VALID(transferWidth)); in Cy_SMIF_TransmitData()
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Dcy_sar.c115 CY_ASSERT_L3(IS_SAR_MASK_VALID(trigConfig->simultControl)); in Cy_SAR_CommonInit()
116 CY_ASSERT_L3(IS_SCAN_CNT_VALID(trigConfig->scanCount)); in Cy_SAR_CommonInit()
227 CY_ASSERT_L3(CY_SAR_RANGECOND(config->rangeCond)); in Cy_SAR_Init()
352 CY_ASSERT_L3(CY_SAR_IS_CLK_VALID(config->clock)); in Cy_SAR_Init()
634 CY_ASSERT_L3(CY_SAR_STARTCONVERT(startSelect)); in Cy_SAR_StartConvert()
706 CY_ASSERT_L3(CY_SAR_TRIGGER(mode)); in Cy_SAR_SetConvertMode()
749 CY_ASSERT_L3(CY_SAR_RETURN(retMode)); in Cy_SAR_IsEndConversion()
1428 CY_ASSERT_L3(CY_SAR_SWITCHSELECT(switchSelect)); in Cy_SAR_SetAnalogSwitch()
1430 CY_ASSERT_L3(CY_SAR_SWITCHSTATE(state)); in Cy_SAR_SetAnalogSwitch()
1475 CY_ASSERT_L3(CY_SAR_SWITCHSELECT(switchSelect)); in Cy_SAR_GetAnalogSwitch()
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Dcy_syspm.c406 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterSleep()
491 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterDeepSleep()
1032 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_SetHibernateWakeupSource()
1073 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_ClearHibernateWakeupSource()
1114 CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage)); in Cy_SysPm_BuckEnable()
1228 CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE1_VALID(voltage)); in Cy_SysPm_BuckSetVoltage1()
1316 CY_ASSERT_L3(CY_SYSPM_IS_BUCK_OUTPUT_VALID(output)); in Cy_SysPm_BuckIsOutputEnabled()
1380 CY_ASSERT_L3(CY_SYSPM_IS_BUCK_VOLTAGE2_VALID(voltage)); in Cy_SysPm_BuckSetVoltage2()
1405 CY_ASSERT_L3(CY_SYSPM_IS_LDO_VOLTAGE_VALID(voltage)); in Cy_SysPm_LdoSetVoltage()
1512 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode)); in Cy_SysPm_LdoSetMode()
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Dcy_canfd.c289 …CY_ASSERT_L3(CY_CANFD_IS_ACCEPT_MATCHING_VALID(config->globalFilterConfig->nonMatchingFramesStanda… in Cy_CANFD_Init()
290 …CY_ASSERT_L3(CY_CANFD_IS_ACCEPT_MATCHING_VALID(config->globalFilterConfig->nonMatchingFramesExtend… in Cy_CANFD_Init()
292 CY_ASSERT_L3(CY_CANFD_IS_BUF_DATA_SIZE_VALID(config->rxBufferDataSize, config->canFDMode)); in Cy_CANFD_Init()
293 CY_ASSERT_L3(CY_CANFD_IS_BUF_DATA_SIZE_VALID(config->rxFIFO1DataSize, config->canFDMode)); in Cy_CANFD_Init()
294 CY_ASSERT_L3(CY_CANFD_IS_BUF_DATA_SIZE_VALID(config->rxFIFO0DataSize, config->canFDMode)); in Cy_CANFD_Init()
295 CY_ASSERT_L3(CY_CANFD_IS_BUF_DATA_SIZE_VALID(config->txBufferDataSize, config->canFDMode)); in Cy_CANFD_Init()
297 CY_ASSERT_L3(CY_CANFD_IS_FIFO_MODE_VALID(config->rxFIFO0Config->mode)); in Cy_CANFD_Init()
298 CY_ASSERT_L3(CY_CANFD_IS_FIFO_MODE_VALID(config->rxFIFO1Config->mode)); in Cy_CANFD_Init()
908 CY_ASSERT_L3(CY_CANFD_IS_SFEC_VALID(filter->sfec)); in Cy_CANFD_SidFilterSetup()
909 CY_ASSERT_L3(CY_CANFD_IS_SFT_VALID(filter->sft)); in Cy_CANFD_SidFilterSetup()
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Dcy_syspm_v3.c129 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterSleep()
322 CY_ASSERT_L3(CY_SYSPM_IS_WAIT_FOR_VALID(waitFor)); in Cy_SysPm_CpuEnterDeepSleep()
527 CY_ASSERT_L3(CY_SYSPM_IS_LDO_MODE_VALID(mode)); in Cy_SysPm_LdoSetMode()
608 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_SetHibernateWakeupSource()
775 CY_ASSERT_L3(CY_SYSPM_IS_WAKE_UP_SOURCE_VALID(wakeupSource)); in Cy_SysPm_ClearHibernateWakeupSource()
1213 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_TYPE_VALID(type)); in Cy_SysPm_ExecuteCallback()
1214 CY_ASSERT_L3(CY_SYSPM_IS_CALLBACK_MODE_VALID(mode)); in Cy_SysPm_ExecuteCallback()
1406 CY_ASSERT_L3(CY_SYSPM_IS_VDDBACKUP_VALID(vddBackControl)); in Cy_SysPm_BackupSetSupply()
1448 CY_ASSERT_L3(CY_SYSPM_IS_SC_CHARGE_KEY_VALID(key)); in Cy_SysPm_BackupSuperCapCharge()
1465 CY_ASSERT_L3(CY_SYSPM_IS_WORD_INDEX_VALID(wordIndex)); in Cy_SysPm_BackupWordStore()
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Dcy_sysint.c46 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); in Cy_SysInt_SetNmiSource()
81 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); in Cy_SysInt_GetNmiSource()
113 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); in Cy_SysInt_Init()
149 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); in Cy_SysInt_Init()
187 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); in Cy_SysInt_Init()
457 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); in Cy_SysInt_InitExtIRQ()
495 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); in Cy_SysInt_InitIntIRQ()
Dcy_sysint_v2.c50 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); in Cy_SysInt_SetNmiSource()
66 CY_ASSERT_L3(CY_SYSINT_IS_NMI_NUM_VALID(nmiNum)); in Cy_SysInt_GetNmiSource()
86 CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority)); in Cy_SysInt_Init()
/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_lvd_ht.h276 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_Enable()
301 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_Disable()
333 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_SetThreshold()
334 CY_ASSERT_L3(CY_LVD_HT_CHECK_TRIPSEL(threshold)); in Cy_LVD_HT_SetThreshold()
362 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_GetStatus()
393 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_GetInterruptStatus()
419 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_ClearInterrupt()
447 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_SetInterrupt()
475 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_GetInterruptMask()
501 CY_ASSERT_L3(CY_LVD_HT_CHECK_LVD_SELECT(lvdNum)); in Cy_LVD_HT_SetInterruptMask()
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Dcy_mcwdt.h825 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_GetEnabledStatus()
972 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_SetMode()
973 CY_ASSERT_L3(CY_MCWDT_IS_MODE_VALID(mode)); in Cy_MCWDT_SetMode()
1006 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_GetMode()
1043 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_SetClearOnMatch()
1083 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_GetClearOnMatch()
1120 CY_ASSERT_L3(CY_MCWDT_IS_CASCADE_VALID(cascade)); in Cy_MCWDT_SetCascade()
1192 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_SetMatch()
1234 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_GetMatch()
1315 CY_ASSERT_L3(CY_MCWDT_IS_CNT_NUM_VALID(counter)); in Cy_MCWDT_GetCount()
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Dcy_ctb.h1208 CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask)); in Cy_CTB_EnableSarSeqCtrl()
1235 CY_ASSERT_L3(CY_CTB_SARSEQCTRL(switchMask)); in Cy_CTB_DisableSarSeqCtrl()
1274 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); in Cy_CTB_GetInterruptStatus()
1299 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); in Cy_CTB_ClearInterrupt()
1324 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); in Cy_CTB_SetInterrupt()
1352 CY_ASSERT_L3(CY_CTB_OPAMPNUM_ALL(compNum)); in Cy_CTB_SetInterruptMask()
1386 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); in Cy_CTB_GetInterruptMask()
1414 CY_ASSERT_L3(CY_CTB_OPAMPNUM(compNum)); in Cy_CTB_GetInterruptStatusMasked()
1444 CY_ASSERT_L3(CY_CTB_IPTAT(iptat)); in Cy_CTB_SetIptatLevel()
1495 CY_ASSERT_L3(CY_CTB_CLKPUMP(pumpClk)); in Cy_CTB_SetPumpClkSource()
Dcy_dmac.h747 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(interruptType)); in Cy_DMAC_Descriptor_SetInterruptType()
793 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(triggerInType)); in Cy_DMAC_Descriptor_SetTriggerInType()
839 CY_ASSERT_L3(CY_DMAC_IS_TRIG_TYPE_VALID(triggerOutType)); in Cy_DMAC_Descriptor_SetTriggerOutType()
885 CY_ASSERT_L3(CY_DMAC_IS_DATA_SIZE_VALID(dataSize)); in Cy_DMAC_Descriptor_SetDataSize()
930 CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(srcTransferSize)); in Cy_DMAC_Descriptor_SetSrcTransferSize()
976 CY_ASSERT_L3(CY_DMAC_IS_XFER_SIZE_VALID(dstTransferSize)); in Cy_DMAC_Descriptor_SetDstTransferSize()
1024 CY_ASSERT_L3(CY_DMAC_IS_RETRIGGER_VALID(retrigger)); in Cy_DMAC_Descriptor_SetRetrigger()
1093 CY_ASSERT_L3(CY_DMAC_IS_CHANNEL_STATE_VALID(channelState)); in Cy_DMAC_Descriptor_SetChannelState()

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