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Searched refs:CY_ASSERT_L2 (Results 1 – 25 of 54) sorted by relevance

123

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_gpio.c94 CY_ASSERT_L2(CY_GPIO_IS_PIN_VALID(pinNum)); in Cy_GPIO_Pin_Init()
95 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->outVal)); in Cy_GPIO_Pin_Init()
96 CY_ASSERT_L2(CY_GPIO_IS_DM_VALID(config->driveMode)); in Cy_GPIO_Pin_Init()
97 CY_ASSERT_L2(CY_GPIO_IS_HSIOM_VALID(config->hsiom)); in Cy_GPIO_Pin_Init()
98 CY_ASSERT_L2(CY_GPIO_IS_INT_EDGE_VALID(config->intEdge)); in Cy_GPIO_Pin_Init()
99 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->intMask)); in Cy_GPIO_Pin_Init()
100 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtrip)); in Cy_GPIO_Pin_Init()
102 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vregEn)); in Cy_GPIO_Pin_Init()
103 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->ibufMode)); in Cy_GPIO_Pin_Init()
104 CY_ASSERT_L2(CY_GPIO_IS_VALUE_VALID(config->vtripSel)); in Cy_GPIO_Pin_Init()
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Dcy_ephy.c56 CY_ASSERT_L2(phy != NULL); in Cy_EPHY_Init()
57 CY_ASSERT_L2(fnRead != NULL); in Cy_EPHY_Init()
58 CY_ASSERT_L2(fnWrite != NULL); in Cy_EPHY_Init()
91 CY_ASSERT_L2(phy->fnPhyRead != NULL); in Cy_EPHY_Discover()
92 CY_ASSERT_L2(phy->fnPhyWrite != NULL); in Cy_EPHY_Discover()
130 CY_ASSERT_L2(phy->fnPhyRead != NULL); in Cy_EPHY_Reset()
131 CY_ASSERT_L2(phy->fnPhyWrite != NULL); in Cy_EPHY_Reset()
182 CY_ASSERT_L2(phy->fnPhyRead != NULL); in Cy_EPHY_Configure()
183 CY_ASSERT_L2(phy->fnPhyWrite != NULL); in Cy_EPHY_Configure()
277 CY_ASSERT_L2(phy->fnPhyRead != NULL); in Cy_EPHY_GetLinkStatus()
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Dcy_tdm.c107 CY_ASSERT_L2(base); in Cy_AudioTDM_TX_Init()
108 CY_ASSERT_L2(config); in Cy_AudioTDM_TX_Init()
109 CY_ASSERT_L2(CY_TDM_IS_CLK_DIV_VALID(clockDiv)); in Cy_AudioTDM_TX_Init()
110 CY_ASSERT_L2(CY_TDM_IS_CHANNELS_VALID(channelNum)); in Cy_AudioTDM_TX_Init()
111 CY_ASSERT_L2(CY_TDM_IS_CHANNEL_SIZE_VALID(channelSIZE)); in Cy_AudioTDM_TX_Init()
112 CY_ASSERT_L2(CY_I2S_TDM_IS_INPUT_SIGNAL_MODE_VALID(config->signalInput)); in Cy_AudioTDM_TX_Init()
159 CY_ASSERT_L2(base); in Cy_AudioTDM_RX_Init()
160 CY_ASSERT_L2(config); in Cy_AudioTDM_RX_Init()
161 CY_ASSERT_L2(CY_TDM_IS_CLK_DIV_VALID(clockDiv)); in Cy_AudioTDM_RX_Init()
162 CY_ASSERT_L2(CY_TDM_IS_CHANNELS_VALID(channelNum)); in Cy_AudioTDM_RX_Init()
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Dcy_sar.c223 CY_ASSERT_L2(CY_SAR_CTRL(config->ctrl)); in Cy_SAR_Init()
224 CY_ASSERT_L2(CY_SAR_SAMPLE_CTRL(config->sampleCtrl)); in Cy_SAR_Init()
225 CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime01)); in Cy_SAR_Init()
226 CY_ASSERT_L2(CY_SAR_SAMPLE_TIME(config->sampleTime23)); in Cy_SAR_Init()
228 CY_ASSERT_L2(CY_SAR_INJMASK(config->chanEn)); in Cy_SAR_Init()
229 CY_ASSERT_L2(CY_SAR_INTRMASK(config->intrMask)); in Cy_SAR_Init()
230 CY_ASSERT_L2(CY_SAR_CHANMASK(config->satIntrMask)); in Cy_SAR_Init()
231 CY_ASSERT_L2(CY_SAR_CHANMASK(config->rangeIntrMask)); in Cy_SAR_Init()
251 CY_ASSERT_L2(CY_SAR_CHAN_CONFIG(config->chanConfig[chan])); in Cy_SAR_Init()
280 CY_ASSERT_L2(CY_SAR_SWITCHMASK(config->muxSwitch)); in Cy_SAR_Init()
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Dcy_canfd.c280 CY_ASSERT_L2(CY_CANFD_IS_CHANNEL_VALID(chan)); in Cy_CANFD_Init()
281 CY_ASSERT_L2(CY_CANFD_IS_NOM_PRESCALER_VALID(config->bitrate->prescaler)); in Cy_CANFD_Init()
282 CY_ASSERT_L2(CY_CANFD_IS_NOM_TIME_SEG_1_VALID(config->bitrate->timeSegment1)); in Cy_CANFD_Init()
283 CY_ASSERT_L2(CY_CANFD_IS_NOM_TIME_SEG_2_VALID(config->bitrate->timeSegment2)); in Cy_CANFD_Init()
284 CY_ASSERT_L2(CY_CANFD_IS_NOM_SYNC_JUMP_WIDTH_VALID(config->bitrate->syncJumpWidth)); in Cy_CANFD_Init()
286 CY_ASSERT_L2(CY_CANFD_IS_SID_FILTERS_VALID(config->sidFilterConfig->numberOfSIDFilters)); in Cy_CANFD_Init()
287 … CY_ASSERT_L2(CY_CANFD_IS_XID_FILTERS_VALID(config->extidFilterConfig->numberOfEXTIDFilters)); in Cy_CANFD_Init()
300 CY_ASSERT_L2(CY_CANFD_IS_FIFO_NUM_VALID(config->rxFIFO0Config->numberOfFIFOElements)); in Cy_CANFD_Init()
301 CY_ASSERT_L2(CY_CANFD_IS_FIFO_NUM_VALID(config->rxFIFO1Config->numberOfFIFOElements)); in Cy_CANFD_Init()
303 CY_ASSERT_L2(CY_CANFD_IS_WATERMARK_VALID(config->rxFIFO1Config->watermark)); in Cy_CANFD_Init()
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Dcy_dma.c146 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->srcXincrement)); in Cy_DMA_Descriptor_Init()
147 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->dstXincrement)); in Cy_DMA_Descriptor_Init()
148 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(config->xCount)); in Cy_DMA_Descriptor_Init()
161 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->srcXincrement)); in Cy_DMA_Descriptor_Init()
162 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->dstXincrement)); in Cy_DMA_Descriptor_Init()
163 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(config->xCount)); in Cy_DMA_Descriptor_Init()
164 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->srcYincrement)); in Cy_DMA_Descriptor_Init()
165 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->dstYincrement)); in Cy_DMA_Descriptor_Init()
166 CY_ASSERT_L2(CY_DMA_IS_LOOP_COUNT_VALID(config->yCount)); in Cy_DMA_Descriptor_Init()
188 CY_ASSERT_L2(CY_DMA_IS_LOOP_INCR_VALID(config->srcXincrement)); in Cy_DMA_Descriptor_Init()
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Dcy_pdm_pcm_v2.c65 CY_ASSERT_L2(CY_PDM_PCM_IS_WORD_SIZE_VALID(channel_config->wordSize)); in Cy_PDM_PCM_Channel_Init()
66 CY_ASSERT_L2(CY_PDM_PCM_IS_SIGNEXTENSION_VALID(channel_config->signExtension)); in Cy_PDM_PCM_Channel_Init()
67 CY_ASSERT_L2(CY_PDM_PCM_IS_TRIG_LEVEL(channel_config->rxFifoTriggerLevel)); in Cy_PDM_PCM_Channel_Init()
68 CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(channel_config->fir0_scale)); in Cy_PDM_PCM_Channel_Init()
69 CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(channel_config->fir1_scale)); in Cy_PDM_PCM_Channel_Init()
128 CY_ASSERT_L2(CY_PDM_PCM_IS_CLK_SEL_VALID(config->clksel)); in Cy_PDM_PCM_Init()
129 CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(config->halverate)); in Cy_PDM_PCM_Init()
130 CY_ASSERT_L2(CY_PDM_PCM_IS_ROUTE_VALID(config->route)); in Cy_PDM_PCM_Init()
242 CY_ASSERT_L2(CY_PDM_PCM_IS_CLK_SEL_VALID(config->clksel)); in Cy_PDM_PCM_test_Init()
243 CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(config->halverate)); in Cy_PDM_PCM_test_Init()
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Dcy_syspm_v2.c1363 CY_ASSERT_L2(false); in Cy_SysPm_GetHibernateWakeupCause()
1378 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage)); in Cy_SysPm_CoreBuckSetVoltage()
1396 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode)); in Cy_SysPm_CoreBuckSetMode()
1409 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_INRUSH_LIMIT_VALID(inrushLimit)); in Cy_SysPm_CoreBuckSetInrushLimit()
1422 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(config->voltageSel)); in Cy_SysPm_CoreBuckConfig()
1423 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(config->mode)); in Cy_SysPm_CoreBuckConfig()
1424 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_INRUSH_LIMIT_VALID(config->inRushLimitSel)); in Cy_SysPm_CoreBuckConfig()
1461 CY_ASSERT_L2(CY_SYSPM_IS_SDR_NUM_VALID(sdr)); in Cy_SysPm_SdrConfigure()
1462 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(config->coreBuckVoltSel)); in Cy_SysPm_SdrConfigure()
1463 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(config->coreBuckMode)); in Cy_SysPm_SdrConfigure()
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Dcy_dmac.c108 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcXincrement)); in Cy_DMAC_Descriptor_Init()
109 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstXincrement)); in Cy_DMAC_Descriptor_Init()
119 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->srcYincrement)); in Cy_DMAC_Descriptor_Init()
120 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(config->dstYincrement)); in Cy_DMAC_Descriptor_Init()
188 CY_ASSERT_L2(CY_DMAC_IS_PRIORITY_VALID(config->priority)); in Cy_DMAC_Channel_Init()
311 CY_ASSERT_L2(CY_DMAC_IS_SCATTER_COUNT_VALID(xCount)); in Cy_DMAC_Descriptor_SetXloopDataCount()
317 CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(xCount)); in Cy_DMAC_Descriptor_SetXloopDataCount()
Dcy_scb_uart.c118 CY_ASSERT_L2(CY_SCB_UART_IS_DATA_WIDTH_VALID (dataWidth)); in Cy_SCB_UART_SetDataWidth()
279 …CY_ASSERT_L2(CY_SCB_UART_IS_OVERSAMPLE_VALID (config->oversample, config->uartMode, config->irdaE… in Cy_SCB_UART_Init()
280 CY_ASSERT_L2(CY_SCB_UART_IS_DATA_WIDTH_VALID (config->dataWidth)); in Cy_SCB_UART_Init()
281 CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_VALID (config->receiverAddress)); in Cy_SCB_UART_Init()
282 CY_ASSERT_L2(CY_SCB_UART_IS_ADDRESS_MASK_VALID(config->receiverAddressMask)); in Cy_SCB_UART_Init()
284 …CY_ASSERT_L2(CY_SCB_UART_IS_MUTLI_PROC_VALID (config->enableMutliProcessorMode, config->uartMode,… in Cy_SCB_UART_Init()
286 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_UART_RX_INTR_MASK)); in Cy_SCB_UART_Init()
287 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_UART_TX_INTR_MASK)); in Cy_SCB_UART_Init()
314 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel)); in Cy_SCB_UART_Init()
315 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel)); in Cy_SCB_UART_Init()
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Dcy_scb_ezi2c.c83 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(config->slaveAddress1)); in Cy_SCB_EZI2C_Init()
84 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(config->slaveAddress2)); in Cy_SCB_EZI2C_Init()
85 CY_ASSERT_L2(config->slaveAddress1 != config->slaveAddress2); in Cy_SCB_EZI2C_Init()
553 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(addr)); in Cy_SCB_EZI2C_SetAddress1()
554 CY_ASSERT_L2(addr != context->address2); in Cy_SCB_EZI2C_SetAddress1()
630 CY_ASSERT_L2(rwBoundary <= size); in Cy_SCB_EZI2C_SetBuffer1()
675 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(addr)); in Cy_SCB_EZI2C_SetAddress2()
676 CY_ASSERT_L2(addr != context->address1); in Cy_SCB_EZI2C_SetAddress2()
750 CY_ASSERT_L2(rwBoundary <= size); in Cy_SCB_EZI2C_SetBuffer2()
Dcy_trigmux.c79 CY_ASSERT_L2(CY_TRIGMUX_IS_INTRIG_VALID(inTrig)); in Cy_TrigMux_Connect()
80 CY_ASSERT_L2(CY_TRIGMUX_IS_OUTTRIG_VALID(outTrig)); in Cy_TrigMux_Connect()
164 CY_ASSERT_L2(CY_TRIGMUX_IS_ONETRIG_VALID(outTrig)); in Cy_TrigMux_Select()
213 CY_ASSERT_L2(CY_TRIGMUX_IS_ONETRIG_VALID(outTrig)); in Cy_TrigMux_Deselect()
Dcy_scb_spi.c82 CY_ASSERT_L2(CY_SCB_SPI_IS_OVERSAMPLE_VALID (config->oversample, config->spiMode)); in Cy_SCB_SPI_Init()
83 CY_ASSERT_L2(CY_SCB_SPI_IS_SS_POLARITY_VALID(config->ssPolarity)); in Cy_SCB_SPI_Init()
84 CY_ASSERT_L2(CY_SCB_SPI_IS_DATA_WIDTH_VALID (config->rxDataWidth)); in Cy_SCB_SPI_Init()
85 CY_ASSERT_L2(CY_SCB_SPI_IS_DATA_WIDTH_VALID (config->txDataWidth)); in Cy_SCB_SPI_Init()
86 …CY_ASSERT_L2(CY_SCB_SPI_IS_BOTH_DATA_WIDTH_VALID(config->subMode, config->rxDataWidth, config->txD… in Cy_SCB_SPI_Init()
88 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->rxFifoIntEnableMask, CY_SCB_SPI_RX_INTR_MASK)); in Cy_SCB_SPI_Init()
89 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->txFifoIntEnableMask, CY_SCB_SPI_TX_INTR_MASK)); in Cy_SCB_SPI_Init()
90 …CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(config->masterSlaveIntEnableMask, CY_SCB_SPI_MASTER_SLAVE_INTR_M… in Cy_SCB_SPI_Init()
122 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->rxFifoTriggerLevel)); in Cy_SCB_SPI_Init()
123 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, config->txFifoTriggerLevel)); in Cy_SCB_SPI_Init()
Dcy_scb_i2c.c89 CY_ASSERT_L2((config->useRxFifo) ? (!config->acceptAddrInFifo) : true); in Cy_SCB_I2C_Init()
90 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID (config->slaveAddress)); in Cy_SCB_I2C_Init()
91 CY_ASSERT_L2(CY_SCB_I2C_IS_ADDR_MASK_VALID(config->slaveAddressMask)); in Cy_SCB_I2C_Init()
92 CY_ASSERT_L2(CY_SCB_I2C_IS_PHASE_OVERSAMPLE_VALID(config->highPhaseDutyCycle)); in Cy_SCB_I2C_Init()
93 CY_ASSERT_L2(CY_SCB_I2C_IS_PHASE_OVERSAMPLE_VALID(config->lowPhaseDutyCycle)); in Cy_SCB_I2C_Init()
550 CY_ASSERT_L2(scbClockHz > 0UL); in Cy_SCB_I2C_SetDataRate()
551 CY_ASSERT_L2(CY_SCB_I2C_IS_DATA_RATE_VALID(dataRateHz)); in Cy_SCB_I2C_SetDataRate()
727 CY_ASSERT_L2(scbClockHz > 0UL); in Cy_SCB_I2C_GetDataRate()
1257 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID(xferConfig->slaveAddress)); in Cy_SCB_I2C_MasterRead()
1485 CY_ASSERT_L2(CY_SCB_IS_I2C_ADDR_VALID (xferConfig->slaveAddress)); in Cy_SCB_I2C_MasterWrite()
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Dcy_i2s.c62 CY_ASSERT_L2(CY_I2S_IS_CLK_DIV_VALID(clockDiv)); in Cy_I2S_Init()
92 CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); in Cy_I2S_Init()
105 CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->txFifoTriggerLevel, channels)); in Cy_I2S_Init()
133 CY_ASSERT_L2(CY_I2S_IS_CHANNELS_VALID(channels)); in Cy_I2S_Init()
146 CY_ASSERT_L2(CY_I2S_IS_TRIG_LEVEL_VALID(config->rxFifoTriggerLevel, channels)); in Cy_I2S_Init()
Dcy_ctb.c326 CY_ASSERT_L2(CY_CTB_OA0SWITCH(config->oa0SwitchCtrl)); in Cy_CTB_Init()
327 CY_ASSERT_L2(CY_CTB_OA1SWITCH(config->oa1SwitchCtrl)); in Cy_CTB_Init()
328 CY_ASSERT_L2(CY_CTB_CTDSWITCH(config->ctdSwitchCtrl)); in Cy_CTB_Init()
587 CY_ASSERT_L2(CY_CTB_OA0SWITCH(config0->oa0SwitchCtrl)); in Cy_CTB_FastInit()
588 CY_ASSERT_L2(CY_CTB_CTDSWITCH(config0->ctdSwitchCtrl)); in Cy_CTB_FastInit()
593 CY_ASSERT_L2(CY_CTB_OA1SWITCH(config1->oa1SwitchCtrl)); in Cy_CTB_FastInit()
594 CY_ASSERT_L2(CY_CTB_CTDSWITCH(config1->ctdSwitchCtrl)); in Cy_CTB_FastInit()
1071 CY_ASSERT_L2(CY_CTB_TRIM(trim)); in Cy_CTB_OpampSetOffset()
1180 CY_ASSERT_L2(CY_CTB_TRIM(trim)); in Cy_CTB_OpampSetSlope()
1263 CY_ASSERT_L2(CY_CTB_SWITCHMASK(switchSelect, switchMask)); in Cy_CTB_SetAnalogSwitch()
Dcy_syspm_v4.c175 CY_ASSERT_L2(CY_IPC_SEMA_SUCCESS == Cy_IPC_Sema_Init(IPC0_SEMA_CH_NUM, 0UL, NULL)); in Cy_SysPm_Init()
1147 CY_ASSERT_L2(false); in Cy_SysPm_GetHibernateWakeupCause()
1162 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage)); in Cy_SysPm_CoreBuckSetVoltage()
1177 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode)); in Cy_SysPm_CoreBuckSetMode()
1190 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_VOLTAGE_VALID(voltage)); in Cy_SysPm_CoreBuckDpslpSetVoltage()
1205 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_MODE_VALID(mode)); in Cy_SysPm_CoreBuckDpslpSetMode()
1229 CY_ASSERT_L2(CY_SYSPM_IS_CORE_BUCK_PROFILE_VALID(profile)); in Cy_SysPm_CoreBuckSetProfile()
1280 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_VOLTAGE_VALID(retLdoParam->activeVoltSel)); in Cy_SysPm_RetLdoConfigure()
1281 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_VOLTAGE_VALID(retLdoParam->deepsleepVoltSel)); in Cy_SysPm_RetLdoConfigure()
1282 CY_ASSERT_L2(CY_SYSPM_IS_RETLDO_GAIN_VALID(retLdoParam->activeGain)); in Cy_SysPm_RetLdoConfigure()
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/hal_infineon-latest/mtb-pdl-cat1/drivers/include/
Dcy_scb_common.h895 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level)); in Cy_SCB_SetRxFifoLevel()
999 CY_ASSERT_L2(CY_SCB_IS_TRIGGER_LEVEL_VALID(base, level)); in Cy_SCB_SetTxFifoLevel()
1149 CY_ASSERT_L2(CY_SCB_IS_MEMWIDTH_VALID(MemWidthMode)); in Cy_SCB_SetMemWidth()
1219 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK)); in Cy_SCB_SetRxInterruptMask()
1294 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK)); in Cy_SCB_ClearRxInterrupt()
1317 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_RX_INTR_MASK)); in Cy_SCB_SetRxInterrupt()
1363 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK)); in Cy_SCB_SetTxInterruptMask()
1440 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK)); in Cy_SCB_ClearTxInterrupt()
1463 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_TX_INTR_MASK)); in Cy_SCB_SetTxInterrupt()
1509 CY_ASSERT_L2(CY_SCB_IS_INTR_VALID(interruptMask, CY_SCB_MASTER_INTR_MASK)); in Cy_SCB_SetMasterInterruptMask()
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Dcy_canfd.h1185 CY_ASSERT_L2(CY_CANFD_IS_CHS_MASK_VALID(channelMask)); in Cy_CANFD_Enable()
1220 CY_ASSERT_L2(CY_CANFD_IS_CHS_MASK_VALID(channelMask)); in Cy_CANFD_Disable()
1266 CY_ASSERT_L2(CY_CANFD_IS_CHS_MASK_VALID(channelMask)); in Cy_CANFD_EnableMRAM()
1341 CY_ASSERT_L2(CY_CANFD_IS_NOM_PRESCALER_VALID(bitrate->prescaler)); in Cy_CANFD_SetBitrate()
1342 CY_ASSERT_L2(CY_CANFD_IS_NOM_TIME_SEG_1_VALID(bitrate->timeSegment1)); in Cy_CANFD_SetBitrate()
1343 CY_ASSERT_L2(CY_CANFD_IS_NOM_TIME_SEG_2_VALID(bitrate->timeSegment2)); in Cy_CANFD_SetBitrate()
1344 CY_ASSERT_L2(CY_CANFD_IS_NOM_SYNC_JUMP_WIDTH_VALID(bitrate->syncJumpWidth)); in Cy_CANFD_SetBitrate()
1387 CY_ASSERT_L2(CY_CANFD_IS_DAT_PRESCALER_VALID(fastBitrate->prescaler)); in Cy_CANFD_SetFastBitrate()
1388 CY_ASSERT_L2(CY_CANFD_IS_DAT_TIME_SEG_1_VALID(fastBitrate->timeSegment1)); in Cy_CANFD_SetFastBitrate()
1389 CY_ASSERT_L2(CY_CANFD_IS_DAT_TIME_SEG_2_VALID(fastBitrate->timeSegment2)); in Cy_CANFD_SetFastBitrate()
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Dcy_sar.h1788 CY_ASSERT_L2(CY_SAR_CHANMASK(enableMask)); in Cy_SAR_SetChanMask()
1876 CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask)); in Cy_SAR_ClearInterrupt()
1908 CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask)); in Cy_SAR_SetInterrupt()
1943 CY_ASSERT_L2(CY_SAR_INTRMASK(intrMask)); in Cy_SAR_SetInterruptMask()
2041 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask)); in Cy_SAR_ClearRangeInterrupt()
2067 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask)); in Cy_SAR_SetRangeInterrupt()
2094 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask)); in Cy_SAR_SetRangeInterruptMask()
2188 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask)); in Cy_SAR_ClearSatInterrupt()
2214 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask)); in Cy_SAR_SetSatInterrupt()
2241 CY_ASSERT_L2(CY_SAR_CHANMASK(chanMask)); in Cy_SAR_SetSatInterruptMask()
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Dcy_dmac.h1141 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(srcXincrement)); in Cy_DMAC_Descriptor_SetXloopSrcIncrement()
1192 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(dstXincrement)); in Cy_DMAC_Descriptor_SetXloopDstIncrement()
1243 CY_ASSERT_L2(CY_DMAC_IS_LOOP_COUNT_VALID(yCount)); in Cy_DMAC_Descriptor_SetYloopDataCount()
1294 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(srcYincrement)); in Cy_DMAC_Descriptor_SetYloopSrcIncrement()
1345 CY_ASSERT_L2(CY_DMAC_IS_LOOP_INCR_VALID(dstYincrement)); in Cy_DMAC_Descriptor_SetYloopDstIncrement()
1506 CY_ASSERT_L2(CY_DMAC_IS_PRIORITY_VALID(priority)); in Cy_DMAC_Channel_SetPriority()
1723 CY_ASSERT_L2(CY_DMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_DMAC_Channel_ClearInterrupt()
1753 CY_ASSERT_L2(CY_DMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_DMAC_Channel_SetInterrupt()
1808 CY_ASSERT_L2(CY_DMAC_IS_INTR_MASK_VALID(interrupt)); in Cy_DMAC_Channel_SetInterruptMask()
Dcy_pdm_pcm_v2.h670 CY_ASSERT_L2(CY_PDM_PCM_IS_HALVE_RATE_SET_VALID(rate)); in Cy_PDM_PCM_SetRateSampling()
716 CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(scale)); in Cy_PDM_PCM_Channel_Set_Fir0()
739 CY_ASSERT_L2(CY_PDM_PCM_IS_SCALE_VALID(scale)); in Cy_PDM_PCM_Channel_Set_Fir1()
785 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_Channel_SetInterruptMask()
865 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_Channel_ClearInterrupt()
886 CY_ASSERT_L2(CY_PDM_PCM_IS_INTR_MASK_VALID(interrupt)); in Cy_PDM_PCM_Channel_SetInterrupt()
Dcy_rtc.h1012 CY_ASSERT_L2(CY_RTC_IS_DAY_VALID(day)); in Cy_RTC_ConvertDayOfWeek()
1013 CY_ASSERT_L2(CY_RTC_IS_MONTH_VALID(month)); in Cy_RTC_ConvertDayOfWeek()
1014 CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year)); in Cy_RTC_ConvertDayOfWeek()
1063 CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year)); in Cy_RTC_IsLeapYear()
1093 CY_ASSERT_L2(CY_RTC_IS_MONTH_VALID(month)); in Cy_RTC_DaysInMonth()
1094 CY_ASSERT_L2(CY_RTC_IS_YEAR_LONG_VALID(year)); in Cy_RTC_DaysInMonth()
Dcy_mcwdt.h734 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); in Cy_MCWDT_Enable()
791 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); in Cy_MCWDT_Disable()
1044 CY_ASSERT_L2(CY_MCWDT_IS_ENABLE_VALID(enable)); in Cy_MCWDT_SetClearOnMatch()
1193 …CY_ASSERT_L2(CY_MCWDT_IS_MATCH_VALID((CY_MCWDT_COUNTER0 == counter) ? … in Cy_MCWDT_SetMatch()
1262 CY_ASSERT_L2(CY_MCWDT_IS_BIT_VALID(bit)); in Cy_MCWDT_SetToggleBit()
1404 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); in Cy_MCWDT_ResetCounters()
1461 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); in Cy_MCWDT_ClearInterrupt()
1485 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); in Cy_MCWDT_SetInterrupt()
1529 CY_ASSERT_L2(CY_MCWDT_IS_CNTS_MASK_VALID(counters)); in Cy_MCWDT_SetInterruptMask()
1672 CY_ASSERT_L2(CY_MCWDT_IS_LOWER_LIMIT_MODE_VALID(mode)); in Cy_MCWDT_SetLowerLimitMode()
Dcy_tdm.h1086 CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); in Cy_AudioTDM_ClearTxInterrupt()
1107 CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); in Cy_AudioTDM_SetTxInterrupt()
1142 CY_ASSERT_L2(CY_I2S_TDM_INTR_TX_MASK_VALID(interrupt)); in Cy_AudioTDM_SetTxInterruptMask()
1203 CY_ASSERT_L2(CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt)); in Cy_AudioTDM_ClearRxInterrupt()
1225 CY_ASSERT_L2(CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt)); in Cy_AudioTDM_SetRxInterrupt()
1259 CY_ASSERT_L2(CY_I2S_TDM_INTR_RX_MASK_VALID(interrupt)); in Cy_AudioTDM_SetRxInterruptMask()

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