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Searched refs:CYHAL_SDHC_BUF_WR_READY (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-hal-cat1/include/
Dcyhal_sdhc.h141CYHAL_SDHC_BUF_WR_READY = 0x00010, //!< This bit is set if the Buffer Write Enable change… enumerator
/hal_infineon-latest/mtb-hal-cat1/source/
Dcyhal_sdhc.c297 (uint32_t)CYHAL_SDHC_BUF_WR_READY, // CY_SD_HOST_BUF_WR_READY