1 /***************************************************************************//** 2 * \file cyip_csd.h 3 * 4 * \brief 5 * CSD IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2023), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_CSD_H_ 28 #define _CYIP_CSD_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * CSD 34 *******************************************************************************/ 35 36 #define CSD_SECTION_SIZE 0x00001000UL 37 38 /** 39 * \brief Capsense Controller (CSD) 40 */ 41 typedef struct { 42 __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */ 43 __IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */ 44 __IM uint32_t RESERVED[30]; 45 __IM uint32_t STATUS; /*!< 0x00000080 Status Register */ 46 __IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */ 47 __IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */ 48 __IM uint32_t STAT_HCNT; /*!< 0x0000008C Current count of the HSCMP counter */ 49 __IM uint32_t RESERVED1[16]; 50 __IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */ 51 __IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */ 52 __IM uint32_t RESERVED2[2]; 53 __IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */ 54 __IM uint32_t RESERVED3[3]; 55 __IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */ 56 __IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */ 57 __IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */ 58 __IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */ 59 __IM uint32_t RESERVED4[32]; 60 __IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */ 61 __IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */ 62 __IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */ 63 __IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */ 64 __IM uint32_t RESERVED5[24]; 65 __IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */ 66 __IM uint32_t RESERVED6[3]; 67 __IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */ 68 __IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */ 69 __IM uint32_t RESERVED7[30]; 70 __IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */ 71 __IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */ 72 __IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */ 73 __IM uint32_t RESERVED8; 74 __IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */ 75 __IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */ 76 __IM uint32_t RESERVED9[2]; 77 __IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */ 78 __IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */ 79 __IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */ 80 __IM uint32_t RESERVED10; 81 __IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */ 82 __IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */ 83 __IM uint32_t RESERVED11[2]; 84 __IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */ 85 __IM uint32_t RESERVED12[3]; 86 __IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */ 87 __IM uint32_t RESERVED13[11]; 88 __IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */ 89 __IM uint32_t RESERVED14[3]; 90 __IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */ 91 __IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */ 92 __IM uint32_t RESERVED15[2]; 93 __IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */ 94 __IM uint32_t RESERVED16[7]; 95 __IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */ 96 __IM uint32_t RESERVED17[47]; 97 __IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */ 98 __IM uint32_t RESERVED18[63]; 99 __IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */ 100 } CSD_V1_Type; /*!< Size = 1284 (0x504) */ 101 102 103 /* CSD.CONFIG */ 104 #define CSD_CONFIG_IREF_SEL_Pos 0UL 105 #define CSD_CONFIG_IREF_SEL_Msk 0x1UL 106 #define CSD_CONFIG_FILTER_DELAY_Pos 4UL 107 #define CSD_CONFIG_FILTER_DELAY_Msk 0x1F0UL 108 #define CSD_CONFIG_SHIELD_DELAY_Pos 10UL 109 #define CSD_CONFIG_SHIELD_DELAY_Msk 0xC00UL 110 #define CSD_CONFIG_SENSE_EN_Pos 12UL 111 #define CSD_CONFIG_SENSE_EN_Msk 0x1000UL 112 #define CSD_CONFIG_FULL_WAVE_Pos 17UL 113 #define CSD_CONFIG_FULL_WAVE_Msk 0x20000UL 114 #define CSD_CONFIG_MUTUAL_CAP_Pos 18UL 115 #define CSD_CONFIG_MUTUAL_CAP_Msk 0x40000UL 116 #define CSD_CONFIG_CSX_DUAL_CNT_Pos 19UL 117 #define CSD_CONFIG_CSX_DUAL_CNT_Msk 0x80000UL 118 #define CSD_CONFIG_DSI_COUNT_SEL_Pos 24UL 119 #define CSD_CONFIG_DSI_COUNT_SEL_Msk 0x1000000UL 120 #define CSD_CONFIG_DSI_SAMPLE_EN_Pos 25UL 121 #define CSD_CONFIG_DSI_SAMPLE_EN_Msk 0x2000000UL 122 #define CSD_CONFIG_SAMPLE_SYNC_Pos 26UL 123 #define CSD_CONFIG_SAMPLE_SYNC_Msk 0x4000000UL 124 #define CSD_CONFIG_DSI_SENSE_EN_Pos 27UL 125 #define CSD_CONFIG_DSI_SENSE_EN_Msk 0x8000000UL 126 #define CSD_CONFIG_LP_MODE_Pos 30UL 127 #define CSD_CONFIG_LP_MODE_Msk 0x40000000UL 128 #define CSD_CONFIG_ENABLE_Pos 31UL 129 #define CSD_CONFIG_ENABLE_Msk 0x80000000UL 130 /* CSD.SPARE */ 131 #define CSD_SPARE_SPARE_Pos 0UL 132 #define CSD_SPARE_SPARE_Msk 0xFUL 133 /* CSD.STATUS */ 134 #define CSD_STATUS_CSD_SENSE_Pos 1UL 135 #define CSD_STATUS_CSD_SENSE_Msk 0x2UL 136 #define CSD_STATUS_HSCMP_OUT_Pos 2UL 137 #define CSD_STATUS_HSCMP_OUT_Msk 0x4UL 138 #define CSD_STATUS_CSDCMP_OUT_Pos 3UL 139 #define CSD_STATUS_CSDCMP_OUT_Msk 0x8UL 140 /* CSD.STAT_SEQ */ 141 #define CSD_STAT_SEQ_SEQ_STATE_Pos 0UL 142 #define CSD_STAT_SEQ_SEQ_STATE_Msk 0x7UL 143 #define CSD_STAT_SEQ_ADC_STATE_Pos 16UL 144 #define CSD_STAT_SEQ_ADC_STATE_Msk 0x70000UL 145 /* CSD.STAT_CNTS */ 146 #define CSD_STAT_CNTS_NUM_CONV_Pos 0UL 147 #define CSD_STAT_CNTS_NUM_CONV_Msk 0xFFFFUL 148 /* CSD.STAT_HCNT */ 149 #define CSD_STAT_HCNT_CNT_Pos 0UL 150 #define CSD_STAT_HCNT_CNT_Msk 0xFFFFUL 151 /* CSD.RESULT_VAL1 */ 152 #define CSD_RESULT_VAL1_VALUE_Pos 0UL 153 #define CSD_RESULT_VAL1_VALUE_Msk 0xFFFFUL 154 #define CSD_RESULT_VAL1_BAD_CONVS_Pos 16UL 155 #define CSD_RESULT_VAL1_BAD_CONVS_Msk 0xFF0000UL 156 /* CSD.RESULT_VAL2 */ 157 #define CSD_RESULT_VAL2_VALUE_Pos 0UL 158 #define CSD_RESULT_VAL2_VALUE_Msk 0xFFFFUL 159 /* CSD.ADC_RES */ 160 #define CSD_ADC_RES_VIN_CNT_Pos 0UL 161 #define CSD_ADC_RES_VIN_CNT_Msk 0xFFFFUL 162 #define CSD_ADC_RES_HSCMP_POL_Pos 16UL 163 #define CSD_ADC_RES_HSCMP_POL_Msk 0x10000UL 164 #define CSD_ADC_RES_ADC_OVERFLOW_Pos 30UL 165 #define CSD_ADC_RES_ADC_OVERFLOW_Msk 0x40000000UL 166 #define CSD_ADC_RES_ADC_ABORT_Pos 31UL 167 #define CSD_ADC_RES_ADC_ABORT_Msk 0x80000000UL 168 /* CSD.INTR */ 169 #define CSD_INTR_SAMPLE_Pos 1UL 170 #define CSD_INTR_SAMPLE_Msk 0x2UL 171 #define CSD_INTR_INIT_Pos 2UL 172 #define CSD_INTR_INIT_Msk 0x4UL 173 #define CSD_INTR_ADC_RES_Pos 8UL 174 #define CSD_INTR_ADC_RES_Msk 0x100UL 175 /* CSD.INTR_SET */ 176 #define CSD_INTR_SET_SAMPLE_Pos 1UL 177 #define CSD_INTR_SET_SAMPLE_Msk 0x2UL 178 #define CSD_INTR_SET_INIT_Pos 2UL 179 #define CSD_INTR_SET_INIT_Msk 0x4UL 180 #define CSD_INTR_SET_ADC_RES_Pos 8UL 181 #define CSD_INTR_SET_ADC_RES_Msk 0x100UL 182 /* CSD.INTR_MASK */ 183 #define CSD_INTR_MASK_SAMPLE_Pos 1UL 184 #define CSD_INTR_MASK_SAMPLE_Msk 0x2UL 185 #define CSD_INTR_MASK_INIT_Pos 2UL 186 #define CSD_INTR_MASK_INIT_Msk 0x4UL 187 #define CSD_INTR_MASK_ADC_RES_Pos 8UL 188 #define CSD_INTR_MASK_ADC_RES_Msk 0x100UL 189 /* CSD.INTR_MASKED */ 190 #define CSD_INTR_MASKED_SAMPLE_Pos 1UL 191 #define CSD_INTR_MASKED_SAMPLE_Msk 0x2UL 192 #define CSD_INTR_MASKED_INIT_Pos 2UL 193 #define CSD_INTR_MASKED_INIT_Msk 0x4UL 194 #define CSD_INTR_MASKED_ADC_RES_Pos 8UL 195 #define CSD_INTR_MASKED_ADC_RES_Msk 0x100UL 196 /* CSD.HSCMP */ 197 #define CSD_HSCMP_HSCMP_EN_Pos 0UL 198 #define CSD_HSCMP_HSCMP_EN_Msk 0x1UL 199 #define CSD_HSCMP_HSCMP_INVERT_Pos 4UL 200 #define CSD_HSCMP_HSCMP_INVERT_Msk 0x10UL 201 #define CSD_HSCMP_AZ_EN_Pos 31UL 202 #define CSD_HSCMP_AZ_EN_Msk 0x80000000UL 203 /* CSD.AMBUF */ 204 #define CSD_AMBUF_PWR_MODE_Pos 0UL 205 #define CSD_AMBUF_PWR_MODE_Msk 0x3UL 206 /* CSD.REFGEN */ 207 #define CSD_REFGEN_REFGEN_EN_Pos 0UL 208 #define CSD_REFGEN_REFGEN_EN_Msk 0x1UL 209 #define CSD_REFGEN_BYPASS_Pos 4UL 210 #define CSD_REFGEN_BYPASS_Msk 0x10UL 211 #define CSD_REFGEN_VDDA_EN_Pos 5UL 212 #define CSD_REFGEN_VDDA_EN_Msk 0x20UL 213 #define CSD_REFGEN_RES_EN_Pos 6UL 214 #define CSD_REFGEN_RES_EN_Msk 0x40UL 215 #define CSD_REFGEN_GAIN_Pos 8UL 216 #define CSD_REFGEN_GAIN_Msk 0x1F00UL 217 #define CSD_REFGEN_VREFLO_SEL_Pos 16UL 218 #define CSD_REFGEN_VREFLO_SEL_Msk 0x1F0000UL 219 #define CSD_REFGEN_VREFLO_INT_Pos 23UL 220 #define CSD_REFGEN_VREFLO_INT_Msk 0x800000UL 221 /* CSD.CSDCMP */ 222 #define CSD_CSDCMP_CSDCMP_EN_Pos 0UL 223 #define CSD_CSDCMP_CSDCMP_EN_Msk 0x1UL 224 #define CSD_CSDCMP_POLARITY_SEL_Pos 4UL 225 #define CSD_CSDCMP_POLARITY_SEL_Msk 0x30UL 226 #define CSD_CSDCMP_CMP_PHASE_Pos 8UL 227 #define CSD_CSDCMP_CMP_PHASE_Msk 0x300UL 228 #define CSD_CSDCMP_CMP_MODE_Pos 28UL 229 #define CSD_CSDCMP_CMP_MODE_Msk 0x10000000UL 230 #define CSD_CSDCMP_FEEDBACK_MODE_Pos 29UL 231 #define CSD_CSDCMP_FEEDBACK_MODE_Msk 0x20000000UL 232 #define CSD_CSDCMP_AZ_EN_Pos 31UL 233 #define CSD_CSDCMP_AZ_EN_Msk 0x80000000UL 234 /* CSD.SW_RES */ 235 #define CSD_SW_RES_RES_HCAV_Pos 0UL 236 #define CSD_SW_RES_RES_HCAV_Msk 0x3UL 237 #define CSD_SW_RES_RES_HCAG_Pos 2UL 238 #define CSD_SW_RES_RES_HCAG_Msk 0xCUL 239 #define CSD_SW_RES_RES_HCBV_Pos 4UL 240 #define CSD_SW_RES_RES_HCBV_Msk 0x30UL 241 #define CSD_SW_RES_RES_HCBG_Pos 6UL 242 #define CSD_SW_RES_RES_HCBG_Msk 0xC0UL 243 #define CSD_SW_RES_RES_F1PM_Pos 16UL 244 #define CSD_SW_RES_RES_F1PM_Msk 0x30000UL 245 #define CSD_SW_RES_RES_F2PT_Pos 18UL 246 #define CSD_SW_RES_RES_F2PT_Msk 0xC0000UL 247 /* CSD.SENSE_PERIOD */ 248 #define CSD_SENSE_PERIOD_SENSE_DIV_Pos 0UL 249 #define CSD_SENSE_PERIOD_SENSE_DIV_Msk 0xFFFUL 250 #define CSD_SENSE_PERIOD_LFSR_SIZE_Pos 16UL 251 #define CSD_SENSE_PERIOD_LFSR_SIZE_Msk 0x70000UL 252 #define CSD_SENSE_PERIOD_LFSR_SCALE_Pos 20UL 253 #define CSD_SENSE_PERIOD_LFSR_SCALE_Msk 0xF00000UL 254 #define CSD_SENSE_PERIOD_LFSR_CLEAR_Pos 24UL 255 #define CSD_SENSE_PERIOD_LFSR_CLEAR_Msk 0x1000000UL 256 #define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Pos 25UL 257 #define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Msk 0x2000000UL 258 #define CSD_SENSE_PERIOD_LFSR_BITS_Pos 26UL 259 #define CSD_SENSE_PERIOD_LFSR_BITS_Msk 0xC000000UL 260 /* CSD.SENSE_DUTY */ 261 #define CSD_SENSE_DUTY_SENSE_WIDTH_Pos 0UL 262 #define CSD_SENSE_DUTY_SENSE_WIDTH_Msk 0xFFFUL 263 #define CSD_SENSE_DUTY_SENSE_POL_Pos 16UL 264 #define CSD_SENSE_DUTY_SENSE_POL_Msk 0x10000UL 265 #define CSD_SENSE_DUTY_OVERLAP_PHI1_Pos 18UL 266 #define CSD_SENSE_DUTY_OVERLAP_PHI1_Msk 0x40000UL 267 #define CSD_SENSE_DUTY_OVERLAP_PHI2_Pos 19UL 268 #define CSD_SENSE_DUTY_OVERLAP_PHI2_Msk 0x80000UL 269 /* CSD.SW_HS_P_SEL */ 270 #define CSD_SW_HS_P_SEL_SW_HMPM_Pos 0UL 271 #define CSD_SW_HS_P_SEL_SW_HMPM_Msk 0x1UL 272 #define CSD_SW_HS_P_SEL_SW_HMPT_Pos 4UL 273 #define CSD_SW_HS_P_SEL_SW_HMPT_Msk 0x10UL 274 #define CSD_SW_HS_P_SEL_SW_HMPS_Pos 8UL 275 #define CSD_SW_HS_P_SEL_SW_HMPS_Msk 0x100UL 276 #define CSD_SW_HS_P_SEL_SW_HMMA_Pos 12UL 277 #define CSD_SW_HS_P_SEL_SW_HMMA_Msk 0x1000UL 278 #define CSD_SW_HS_P_SEL_SW_HMMB_Pos 16UL 279 #define CSD_SW_HS_P_SEL_SW_HMMB_Msk 0x10000UL 280 #define CSD_SW_HS_P_SEL_SW_HMCA_Pos 20UL 281 #define CSD_SW_HS_P_SEL_SW_HMCA_Msk 0x100000UL 282 #define CSD_SW_HS_P_SEL_SW_HMCB_Pos 24UL 283 #define CSD_SW_HS_P_SEL_SW_HMCB_Msk 0x1000000UL 284 #define CSD_SW_HS_P_SEL_SW_HMRH_Pos 28UL 285 #define CSD_SW_HS_P_SEL_SW_HMRH_Msk 0x10000000UL 286 /* CSD.SW_HS_N_SEL */ 287 #define CSD_SW_HS_N_SEL_SW_HCCC_Pos 16UL 288 #define CSD_SW_HS_N_SEL_SW_HCCC_Msk 0x10000UL 289 #define CSD_SW_HS_N_SEL_SW_HCCD_Pos 20UL 290 #define CSD_SW_HS_N_SEL_SW_HCCD_Msk 0x100000UL 291 #define CSD_SW_HS_N_SEL_SW_HCRH_Pos 24UL 292 #define CSD_SW_HS_N_SEL_SW_HCRH_Msk 0x7000000UL 293 #define CSD_SW_HS_N_SEL_SW_HCRL_Pos 28UL 294 #define CSD_SW_HS_N_SEL_SW_HCRL_Msk 0x70000000UL 295 /* CSD.SW_SHIELD_SEL */ 296 #define CSD_SW_SHIELD_SEL_SW_HCAV_Pos 0UL 297 #define CSD_SW_SHIELD_SEL_SW_HCAV_Msk 0x7UL 298 #define CSD_SW_SHIELD_SEL_SW_HCAG_Pos 4UL 299 #define CSD_SW_SHIELD_SEL_SW_HCAG_Msk 0x70UL 300 #define CSD_SW_SHIELD_SEL_SW_HCBV_Pos 8UL 301 #define CSD_SW_SHIELD_SEL_SW_HCBV_Msk 0x700UL 302 #define CSD_SW_SHIELD_SEL_SW_HCBG_Pos 12UL 303 #define CSD_SW_SHIELD_SEL_SW_HCBG_Msk 0x7000UL 304 #define CSD_SW_SHIELD_SEL_SW_HCCV_Pos 16UL 305 #define CSD_SW_SHIELD_SEL_SW_HCCV_Msk 0x10000UL 306 #define CSD_SW_SHIELD_SEL_SW_HCCG_Pos 20UL 307 #define CSD_SW_SHIELD_SEL_SW_HCCG_Msk 0x100000UL 308 /* CSD.SW_AMUXBUF_SEL */ 309 #define CSD_SW_AMUXBUF_SEL_SW_IRBY_Pos 4UL 310 #define CSD_SW_AMUXBUF_SEL_SW_IRBY_Msk 0x10UL 311 #define CSD_SW_AMUXBUF_SEL_SW_IRLB_Pos 8UL 312 #define CSD_SW_AMUXBUF_SEL_SW_IRLB_Msk 0x100UL 313 #define CSD_SW_AMUXBUF_SEL_SW_ICA_Pos 12UL 314 #define CSD_SW_AMUXBUF_SEL_SW_ICA_Msk 0x1000UL 315 #define CSD_SW_AMUXBUF_SEL_SW_ICB_Pos 16UL 316 #define CSD_SW_AMUXBUF_SEL_SW_ICB_Msk 0x70000UL 317 #define CSD_SW_AMUXBUF_SEL_SW_IRLI_Pos 20UL 318 #define CSD_SW_AMUXBUF_SEL_SW_IRLI_Msk 0x100000UL 319 #define CSD_SW_AMUXBUF_SEL_SW_IRH_Pos 24UL 320 #define CSD_SW_AMUXBUF_SEL_SW_IRH_Msk 0x1000000UL 321 #define CSD_SW_AMUXBUF_SEL_SW_IRL_Pos 28UL 322 #define CSD_SW_AMUXBUF_SEL_SW_IRL_Msk 0x10000000UL 323 /* CSD.SW_BYP_SEL */ 324 #define CSD_SW_BYP_SEL_SW_BYA_Pos 12UL 325 #define CSD_SW_BYP_SEL_SW_BYA_Msk 0x1000UL 326 #define CSD_SW_BYP_SEL_SW_BYB_Pos 16UL 327 #define CSD_SW_BYP_SEL_SW_BYB_Msk 0x10000UL 328 #define CSD_SW_BYP_SEL_SW_CBCC_Pos 20UL 329 #define CSD_SW_BYP_SEL_SW_CBCC_Msk 0x100000UL 330 /* CSD.SW_CMP_P_SEL */ 331 #define CSD_SW_CMP_P_SEL_SW_SFPM_Pos 0UL 332 #define CSD_SW_CMP_P_SEL_SW_SFPM_Msk 0x7UL 333 #define CSD_SW_CMP_P_SEL_SW_SFPT_Pos 4UL 334 #define CSD_SW_CMP_P_SEL_SW_SFPT_Msk 0x70UL 335 #define CSD_SW_CMP_P_SEL_SW_SFPS_Pos 8UL 336 #define CSD_SW_CMP_P_SEL_SW_SFPS_Msk 0x700UL 337 #define CSD_SW_CMP_P_SEL_SW_SFMA_Pos 12UL 338 #define CSD_SW_CMP_P_SEL_SW_SFMA_Msk 0x1000UL 339 #define CSD_SW_CMP_P_SEL_SW_SFMB_Pos 16UL 340 #define CSD_SW_CMP_P_SEL_SW_SFMB_Msk 0x10000UL 341 #define CSD_SW_CMP_P_SEL_SW_SFCA_Pos 20UL 342 #define CSD_SW_CMP_P_SEL_SW_SFCA_Msk 0x100000UL 343 #define CSD_SW_CMP_P_SEL_SW_SFCB_Pos 24UL 344 #define CSD_SW_CMP_P_SEL_SW_SFCB_Msk 0x1000000UL 345 /* CSD.SW_CMP_N_SEL */ 346 #define CSD_SW_CMP_N_SEL_SW_SCRH_Pos 24UL 347 #define CSD_SW_CMP_N_SEL_SW_SCRH_Msk 0x7000000UL 348 #define CSD_SW_CMP_N_SEL_SW_SCRL_Pos 28UL 349 #define CSD_SW_CMP_N_SEL_SW_SCRL_Msk 0x70000000UL 350 /* CSD.SW_REFGEN_SEL */ 351 #define CSD_SW_REFGEN_SEL_SW_IAIB_Pos 0UL 352 #define CSD_SW_REFGEN_SEL_SW_IAIB_Msk 0x1UL 353 #define CSD_SW_REFGEN_SEL_SW_IBCB_Pos 4UL 354 #define CSD_SW_REFGEN_SEL_SW_IBCB_Msk 0x10UL 355 #define CSD_SW_REFGEN_SEL_SW_SGMB_Pos 16UL 356 #define CSD_SW_REFGEN_SEL_SW_SGMB_Msk 0x10000UL 357 #define CSD_SW_REFGEN_SEL_SW_SGRP_Pos 20UL 358 #define CSD_SW_REFGEN_SEL_SW_SGRP_Msk 0x100000UL 359 #define CSD_SW_REFGEN_SEL_SW_SGRE_Pos 24UL 360 #define CSD_SW_REFGEN_SEL_SW_SGRE_Msk 0x1000000UL 361 #define CSD_SW_REFGEN_SEL_SW_SGR_Pos 28UL 362 #define CSD_SW_REFGEN_SEL_SW_SGR_Msk 0x10000000UL 363 /* CSD.SW_FW_MOD_SEL */ 364 #define CSD_SW_FW_MOD_SEL_SW_F1PM_Pos 0UL 365 #define CSD_SW_FW_MOD_SEL_SW_F1PM_Msk 0x1UL 366 #define CSD_SW_FW_MOD_SEL_SW_F1MA_Pos 8UL 367 #define CSD_SW_FW_MOD_SEL_SW_F1MA_Msk 0x700UL 368 #define CSD_SW_FW_MOD_SEL_SW_F1CA_Pos 16UL 369 #define CSD_SW_FW_MOD_SEL_SW_F1CA_Msk 0x70000UL 370 #define CSD_SW_FW_MOD_SEL_SW_C1CC_Pos 20UL 371 #define CSD_SW_FW_MOD_SEL_SW_C1CC_Msk 0x100000UL 372 #define CSD_SW_FW_MOD_SEL_SW_C1CD_Pos 24UL 373 #define CSD_SW_FW_MOD_SEL_SW_C1CD_Msk 0x1000000UL 374 #define CSD_SW_FW_MOD_SEL_SW_C1F1_Pos 28UL 375 #define CSD_SW_FW_MOD_SEL_SW_C1F1_Msk 0x10000000UL 376 /* CSD.SW_FW_TANK_SEL */ 377 #define CSD_SW_FW_TANK_SEL_SW_F2PT_Pos 4UL 378 #define CSD_SW_FW_TANK_SEL_SW_F2PT_Msk 0x10UL 379 #define CSD_SW_FW_TANK_SEL_SW_F2MA_Pos 8UL 380 #define CSD_SW_FW_TANK_SEL_SW_F2MA_Msk 0x700UL 381 #define CSD_SW_FW_TANK_SEL_SW_F2CA_Pos 12UL 382 #define CSD_SW_FW_TANK_SEL_SW_F2CA_Msk 0x7000UL 383 #define CSD_SW_FW_TANK_SEL_SW_F2CB_Pos 16UL 384 #define CSD_SW_FW_TANK_SEL_SW_F2CB_Msk 0x70000UL 385 #define CSD_SW_FW_TANK_SEL_SW_C2CC_Pos 20UL 386 #define CSD_SW_FW_TANK_SEL_SW_C2CC_Msk 0x100000UL 387 #define CSD_SW_FW_TANK_SEL_SW_C2CD_Pos 24UL 388 #define CSD_SW_FW_TANK_SEL_SW_C2CD_Msk 0x1000000UL 389 #define CSD_SW_FW_TANK_SEL_SW_C2F2_Pos 28UL 390 #define CSD_SW_FW_TANK_SEL_SW_C2F2_Msk 0x10000000UL 391 /* CSD.SW_DSI_SEL */ 392 #define CSD_SW_DSI_SEL_DSI_CSH_TANK_Pos 0UL 393 #define CSD_SW_DSI_SEL_DSI_CSH_TANK_Msk 0xFUL 394 #define CSD_SW_DSI_SEL_DSI_CMOD_Pos 4UL 395 #define CSD_SW_DSI_SEL_DSI_CMOD_Msk 0xF0UL 396 /* CSD.IO_SEL */ 397 #define CSD_IO_SEL_CSD_TX_OUT_Pos 0UL 398 #define CSD_IO_SEL_CSD_TX_OUT_Msk 0xFUL 399 #define CSD_IO_SEL_CSD_TX_OUT_EN_Pos 4UL 400 #define CSD_IO_SEL_CSD_TX_OUT_EN_Msk 0xF0UL 401 #define CSD_IO_SEL_CSD_TX_AMUXB_EN_Pos 12UL 402 #define CSD_IO_SEL_CSD_TX_AMUXB_EN_Msk 0xF000UL 403 #define CSD_IO_SEL_CSD_TX_N_OUT_Pos 16UL 404 #define CSD_IO_SEL_CSD_TX_N_OUT_Msk 0xF0000UL 405 #define CSD_IO_SEL_CSD_TX_N_OUT_EN_Pos 20UL 406 #define CSD_IO_SEL_CSD_TX_N_OUT_EN_Msk 0xF00000UL 407 #define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Pos 24UL 408 #define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Msk 0xF000000UL 409 /* CSD.SEQ_TIME */ 410 #define CSD_SEQ_TIME_AZ_TIME_Pos 0UL 411 #define CSD_SEQ_TIME_AZ_TIME_Msk 0xFFUL 412 /* CSD.SEQ_INIT_CNT */ 413 #define CSD_SEQ_INIT_CNT_CONV_CNT_Pos 0UL 414 #define CSD_SEQ_INIT_CNT_CONV_CNT_Msk 0xFFFFUL 415 /* CSD.SEQ_NORM_CNT */ 416 #define CSD_SEQ_NORM_CNT_CONV_CNT_Pos 0UL 417 #define CSD_SEQ_NORM_CNT_CONV_CNT_Msk 0xFFFFUL 418 /* CSD.ADC_CTL */ 419 #define CSD_ADC_CTL_ADC_TIME_Pos 0UL 420 #define CSD_ADC_CTL_ADC_TIME_Msk 0xFFUL 421 #define CSD_ADC_CTL_ADC_MODE_Pos 16UL 422 #define CSD_ADC_CTL_ADC_MODE_Msk 0x30000UL 423 /* CSD.SEQ_START */ 424 #define CSD_SEQ_START_START_Pos 0UL 425 #define CSD_SEQ_START_START_Msk 0x1UL 426 #define CSD_SEQ_START_SEQ_MODE_Pos 1UL 427 #define CSD_SEQ_START_SEQ_MODE_Msk 0x2UL 428 #define CSD_SEQ_START_ABORT_Pos 3UL 429 #define CSD_SEQ_START_ABORT_Msk 0x8UL 430 #define CSD_SEQ_START_DSI_START_EN_Pos 4UL 431 #define CSD_SEQ_START_DSI_START_EN_Msk 0x10UL 432 #define CSD_SEQ_START_AZ0_SKIP_Pos 8UL 433 #define CSD_SEQ_START_AZ0_SKIP_Msk 0x100UL 434 #define CSD_SEQ_START_AZ1_SKIP_Pos 9UL 435 #define CSD_SEQ_START_AZ1_SKIP_Msk 0x200UL 436 /* CSD.IDACA */ 437 #define CSD_IDACA_VAL_Pos 0UL 438 #define CSD_IDACA_VAL_Msk 0x7FUL 439 #define CSD_IDACA_POL_DYN_Pos 7UL 440 #define CSD_IDACA_POL_DYN_Msk 0x80UL 441 #define CSD_IDACA_POLARITY_Pos 8UL 442 #define CSD_IDACA_POLARITY_Msk 0x300UL 443 #define CSD_IDACA_BAL_MODE_Pos 10UL 444 #define CSD_IDACA_BAL_MODE_Msk 0xC00UL 445 #define CSD_IDACA_LEG1_MODE_Pos 16UL 446 #define CSD_IDACA_LEG1_MODE_Msk 0x30000UL 447 #define CSD_IDACA_LEG2_MODE_Pos 18UL 448 #define CSD_IDACA_LEG2_MODE_Msk 0xC0000UL 449 #define CSD_IDACA_DSI_CTRL_EN_Pos 21UL 450 #define CSD_IDACA_DSI_CTRL_EN_Msk 0x200000UL 451 #define CSD_IDACA_RANGE_Pos 22UL 452 #define CSD_IDACA_RANGE_Msk 0xC00000UL 453 #define CSD_IDACA_LEG1_EN_Pos 24UL 454 #define CSD_IDACA_LEG1_EN_Msk 0x1000000UL 455 #define CSD_IDACA_LEG2_EN_Pos 25UL 456 #define CSD_IDACA_LEG2_EN_Msk 0x2000000UL 457 /* CSD.IDACB */ 458 #define CSD_IDACB_VAL_Pos 0UL 459 #define CSD_IDACB_VAL_Msk 0x7FUL 460 #define CSD_IDACB_POL_DYN_Pos 7UL 461 #define CSD_IDACB_POL_DYN_Msk 0x80UL 462 #define CSD_IDACB_POLARITY_Pos 8UL 463 #define CSD_IDACB_POLARITY_Msk 0x300UL 464 #define CSD_IDACB_BAL_MODE_Pos 10UL 465 #define CSD_IDACB_BAL_MODE_Msk 0xC00UL 466 #define CSD_IDACB_LEG1_MODE_Pos 16UL 467 #define CSD_IDACB_LEG1_MODE_Msk 0x30000UL 468 #define CSD_IDACB_LEG2_MODE_Pos 18UL 469 #define CSD_IDACB_LEG2_MODE_Msk 0xC0000UL 470 #define CSD_IDACB_DSI_CTRL_EN_Pos 21UL 471 #define CSD_IDACB_DSI_CTRL_EN_Msk 0x200000UL 472 #define CSD_IDACB_RANGE_Pos 22UL 473 #define CSD_IDACB_RANGE_Msk 0xC00000UL 474 #define CSD_IDACB_LEG1_EN_Pos 24UL 475 #define CSD_IDACB_LEG1_EN_Msk 0x1000000UL 476 #define CSD_IDACB_LEG2_EN_Pos 25UL 477 #define CSD_IDACB_LEG2_EN_Msk 0x2000000UL 478 #define CSD_IDACB_LEG3_EN_Pos 26UL 479 #define CSD_IDACB_LEG3_EN_Msk 0x4000000UL 480 481 482 #endif /* _CYIP_CSD_H_ */ 483 484 485 /* [] END OF FILE */ 486
