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Searched refs:CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss_v2.h307 #define CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos 0UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1340 #define CPUSS_RAM1_CTL0_SLOW_WS_Pos CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos …