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Searched refs:CPUSS_RAM2_PWR_CTL (Results 1 – 4 of 4) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_syspm.c2114CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY)… in Cy_SysPm_SetSRAMMacroPwrMode()
2148 retVal = _FLD2VAL(CPUSS_V2_RAM2_PWR_CTL_PWR_MODE, CPUSS_RAM2_PWR_CTL); in Cy_SysPm_GetSRAMMacroPwrMode()
2193CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY)… in Cy_SysPm_SetSRAMPwrMode()
Dcy_syspm_v3.c1524CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) | in Cy_SysPm_SetSRAMMacroPwrMode()
1559 retVal = _FLD2VAL(CPUSS_RAM2_PWR_CTL_PWR_MODE, CPUSS_RAM2_PWR_CTL); in Cy_SysPm_GetSRAMMacroPwrMode()
1596CPUSS_RAM2_PWR_CTL = _VAL2FLD(CPUSS_RAM2_PWR_CTL_VECTKEYSTAT, CY_SYSPM_PWR_MACRO_CTL_WRITE_KEY) | in Cy_SysPm_SetSRAMPwrMode()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h794 #define CPUSS_RAM2_PWR_CTL (*(volatile uint32_t *) (cy_device->cpussBase + cy_devi… macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h526 #define CPUSS_RAM2_PWR_CTL ((((CPUSS_Type *)(CPUSS_BASE))->RAM2_PWR_CTL)) macro