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Searched refs:CPUSS_RAM2_CTL0_SLOW_WS_Pos (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h243 #define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h426 #define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1359 #define CPUSS_RAM2_CTL0_SLOW_WS_Pos CPUSS_V2_RAM2_CTL0_SLOW_WS_Pos … macro