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Searched refs:CPUSS_RAM2_CTL0_ECC_INJ_EN_Pos (Results 1 – 2 of 2) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h434 #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Pos 18UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1367 #define CPUSS_RAM2_CTL0_ECC_INJ_EN_Pos CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Pos … macro