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Searched refs:CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/ip/
Dcyip_cpuss.h238 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/ip/
Dcyip_cpuss.h421 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dtviibe_remaps.h1354 #define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Pos … macro