Searched refs:CPUSS_RAM1_CTL0 (Results 1 – 6 of 6) sorted by relevance
469 CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_SLOW_WS, waitStates); in Cy_SysLib_SetWaitStates()470 CPUSS_RAM1_CTL0 = _CLR_SET_FLD32U(CPUSS_RAM1_CTL0, CPUSS_RAM1_CTL0_FAST_WS, 0UL); in Cy_SysLib_SetWaitStates()
26 #define CPUSS_RAM1_CTL0 0x40201380 macro113 ldr r1, =CPUSS_RAM1_CTL0
34 CPUSS_RAM1_CTL0 EQU 0x40201380 define116 LDR r1, =CPUSS_RAM1_CTL0
55 CPUSS_RAM1_CTL0 EQU 0x40201380 define179 LDR r1, =CPUSS_RAM1_CTL0
790 #define CPUSS_RAM1_CTL0 (*(volatile uint32_t *) (cy_device->cpussBase + cy_devi… macro
521 #define CPUSS_RAM1_CTL0 ((((CPUSS_Type *)(CPUSS_BASE))->RAM1_STATUS)) macro
