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Searched refs:CPUSS_CM4_SYSTEM_INT_CTL (Results 1 – 3 of 3) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/drivers/source/
Dcy_sysint.c238CPUSS_CM4_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn) in Cy_SysInt_SetInterruptSource()
309 …T_ENABLE == _FLD2VAL(CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM4_SYSTEM_INT_CTL[devIntrSr… in Cy_SysInt_GetNvicConnection()
311 … tempReg = _FLD2VAL(CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM4_SYSTEM_INT_CTL[devIntrSrc]); in Cy_SysInt_GetNvicConnection()
561 CPUSS_CM4_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk; in Cy_SysInt_EnableSystemInt()
/hal_infineon-latest/mtb-hal-cat1/include_pvt/
Dcyhal_irq_impl.h230 …return (0u != (CPUSS_CM4_SYSTEM_INT_CTL[system_irq] & CPUSS_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk)); in _cyhal_irq_is_enabled()
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy_device.h805 #define CPUSS_CM4_SYSTEM_INT_CTL (((CPUSS_V2_Type *)(cy_device->cpussBase))->CM4_SYSTEM_… macro