Searched refs:CPUSS_CM0_SYSTEM_INT_CTL (Results 1 – 4 of 4) sorted by relevance
235 … CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX, IRQn) in Cy_SysInt_SetInterruptSource()247 … CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] = _VAL2FLD(CPUSS_CM0_SYSTEM_INT_CTL_CM0_CPU_INT_IDX, IRQn) in Cy_SysInt_SetInterruptSource()273 … CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc] &= (uint32_t)~ CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk; in Cy_SysInt_DisconnectInterruptSource()304 …T_ENABLE == _FLD2VAL(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSr… in Cy_SysInt_GetNvicConnection()306 … tempReg = _FLD2VAL(CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc]); in Cy_SysInt_GetNvicConnection()318 …SINT_ENABLE == _FLD2VAL(CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSr… in Cy_SysInt_GetNvicConnection()320 …tempReg = _FLD2VAL(CPUSS_CM0_SYSTEM_INT_CTL_CM0_CPU_INT_IDX, CPUSS_CM0_SYSTEM_INT_CTL[devIntrSrc]); in Cy_SysInt_GetNvicConnection()547 CPUSS_CM0_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk; in Cy_SysInt_EnableSystemInt()
86 CPUSS_CM0_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk; in Cy_SysInt_EnableSystemInt()88 CPUSS_CM0_SYSTEM_INT_CTL[sysIntSrc] |= CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk; in Cy_SysInt_EnableSystemInt()223 …return (0u != (CPUSS_CM0_SYSTEM_INT_CTL[system_irq] & CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Ms… in _cyhal_irq_is_enabled()225 …return (0u != (CPUSS_CM0_SYSTEM_INT_CTL[system_irq] & CPUSS_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk)); in _cyhal_irq_is_enabled()
803 #define CPUSS_CM0_SYSTEM_INT_CTL (((CPUSS_V2_Type *)(cy_device->cpussBase))->CM0_SYSTEM_… macro
531 #define CPUSS_CM0_SYSTEM_INT_CTL (((CPUSS_Type *)(CPUSS_BASE))->CM0_SYSTEM_INT_CTL) macro
