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Searched refs:CPUSS_BASE (Results 1 – 25 of 347) sorted by relevance

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/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dcy_device.h458 #define CPUSS_SYSTICK_CTL (((CPUSS_Type*) CPUSS_BASE)->SYSTICK_CTL)
469 #define CPUSS_FAST_0_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL)
470 #define CPUSS_FAST_1_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->FAST_1_CLOCK_CTL)
471 #define CPUSS_SLOW_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->SLOW_CLOCK_CTL)
472 #define CPUSS_MEM_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->MEM_CLOCK_CTL)
473 #define CPUSS_PERI_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->PERI_CLOCK_CTL)
488 #define CPUSS_IDENTITY ((((CPUSS_Type *)(CPUSS_BASE))->IDENTITY))
489 #define CPUSS_CM7_0_STATUS ((((CPUSS_Type *)(CPUSS_BASE))->CM7_0_STATUS))
490 #define CPUSS_FAST_0_CLOCK_CTL (((CPUSS_Type*) CPUSS_BASE)->FAST_0_CLOCK_CTL)
491 #define CPUSS_CM7_0_CTL (((CPUSS_Type*) CPUSS_BASE)->CM7_0_CTL)
[all …]
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dcy8c6136fdi_f42.h557 #define CPUSS_BASE 0x40210000UL macro
558 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6137bzi_f14.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6336lqi_blf42.h557 #define CPUSS_BASE 0x40210000UL macro
558 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6337bzi_blf13.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6016bzi_f04.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6036bzi_f04.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6117fdi_f02.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6136bzi_f14.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6136fti_f42.h557 #define CPUSS_BASE 0x40210000UL macro
558 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6137fdi_f02.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6316bzi_blf03.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6316bzi_blf04.h550 #define CPUSS_BASE 0x40210000UL macro
551 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6336bzi_blf03.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6336bzi_blf04.h550 #define CPUSS_BASE 0x40210000UL macro
551 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6336lqi_blf02.h547 #define CPUSS_BASE 0x40210000UL macro
548 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6146bti_f54.h563 #define CPUSS_BASE 0x40210000UL macro
564 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6147bti_f54.h563 #define CPUSS_BASE 0x40210000UL macro
564 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6347fmi_bud13.h775 #define CPUSS_BASE 0x40210000UL macro
776 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c68237bz_ble.h776 #define CPUSS_BASE 0x40210000UL macro
777 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6246bzi_d04.h772 #define CPUSS_BASE 0x40210000UL macro
773 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c68237fm_ble.h776 #define CPUSS_BASE 0x40210000UL macro
777 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6247bzi_d44.h782 #define CPUSS_BASE 0x40210000UL macro
783 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6347bzi_bld43.h782 #define CPUSS_BASE 0x40210000UL macro
783 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …
Dcy8c6347bzi_bld44.h785 #define CPUSS_BASE 0x40210000UL macro
786 #define CPUSS ((CPUSS_Type*) CPUSS_BASE) …

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