Searched refs:CONFIG (Results 1 – 15 of 15) sorted by relevance
47 …__IOM uint32_t CONFIG; /*!< 0x00000004 Timer trigger configuration register… member57 …__IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration r… member67 __IOM uint32_t CONFIG; /*!< 0x00000004 FIFO configuration register */ member
123 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member137 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member171 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
42 __IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */ member
126 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member160 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
42 __IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */ member
124 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member134 …__IOM uint32_t CONFIG; /*!< 0x00000000 400MHz Digital PLL Configuration Reg… member150 …__IOM uint32_t CONFIG; /*!< 0x00000010 MCWDT Subcounter Configuration Regis… member184 __IOM uint32_t CONFIG; /*!< 0x00000010 WDT Configuration Register */ member
47 __IOM uint32_t CONFIG; /*!< 0x00000114 Config */ member
124 __IOM uint32_t CONFIG; /*!< 0x00000000 400MHz PLL Configuration Register */ member134 __IOM uint32_t CONFIG; /*!< 0x00000000 DPLL_LP Configuration Register */ member
238 base->CONFIG = config->config; in Cy_CSD_Configure()
604 #define CY_CSD_REG_OFFSET_CONFIG (offsetof(CSD_Type, CONFIG))
449 …SRSS_CLK_PLL_400M_CONFIG(pllNum) (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG)460 #define SRSS_WDT_CONFIG (((WDT_Type*) &SRSS->WDT_STRUCT)->CONFIG)865 #define LPCOMP_CONFIG(base) (((LPCOMP_Type *)(base))->CONFIG)881 #define MCWDT_CTR_CONFIG(base, counter) (((MCWDT_Type *)(base))->CTR[counter].CONFIG)1730 #define PASS_LPOSC_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->LPOSC.CONFIG)1732 #define PASS_TIMER_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->TIMER.CONFIG)1747 #define PASS_FIFO_CONFIG(sarBase) (PASS_FIFO_BASE(sarBase)->CONFIG)
270 …SRSS_CLK_PLL_400M_CONFIG(pllNum) (((SRSS_Type *) SRSS)->CLK_PLL400M[pllNum].CONFIG)281 #define SRSS_WDT_CONFIG (((WDT_Type*) &SRSS->WDT_STRUCT)->CONFIG)549 #define LPCOMP_CONFIG(base) (((LPCOMP_V1_Type *)(base))->CONFIG)563 #define MCWDT_CTR_CONFIG(base, counter) (((MCWDT_Type *)(base))->CTR[counter].CONFIG)2200 #define PASS_LPOSC_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->LPOSC.CONFIG)2202 #define PASS_TIMER_CONFIG(passBase) (((PASS_V2_Type*) (passBase))->TIMER.CONFIG)2217 #define PASS_FIFO_CONFIG(sarBase) (PASS_FIFO_BASE(sarBase)->CONFIG)
761 #define EFUSE_CONFIG(base) (((EFUSE_Type *) (base))->CONFIG)916 #define SRSS_CLK_DPLL_LP_CONFIG(pllNum) (((SRSS_Type *) SRSS)->CLK_DPLL_LP[pllNum].CONFIG)1058 …_LP_PLL_CONFIG(pllNum) (((CLK_LP_PLL_Type*) &SRSS->CLK_LP_PLL[pllNum])->PLL28LP_STRUCT.CONFIG)1608 #define LPCOMP_CONFIG(base) (((LPCOMP_Type *)(base))->CONFIG)
