1 /***************************************************************************//** 2 * \file cyip_axi_dmac.h 3 * 4 * \brief 5 * AXI_DMAC IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_AXI_DMAC_H_ 28 #define _CYIP_AXI_DMAC_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * AXI_DMAC 34 *******************************************************************************/ 35 36 #define AXI_DMAC_CH_SECTION_SIZE 0x00000100UL 37 #define AXI_DMAC_SECTION_SIZE 0x00010000UL 38 39 /** 40 * \brief AXI DMA controller channel (AXI_DMAC_CH) 41 */ 42 typedef struct { 43 __IOM uint32_t CTL; /*!< 0x00000000 Channel control */ 44 __IM uint32_t STATUS; /*!< 0x00000004 Channel status */ 45 __IM uint32_t RESERVED[2]; 46 __IM uint32_t IDX; /*!< 0x00000010 Channel current X and Y indices */ 47 __IM uint32_t SRC; /*!< 0x00000014 Channel current source address */ 48 __IM uint32_t DST; /*!< 0x00000018 Channel current destination address */ 49 __IM uint32_t M_IDX; /*!< 0x0000001C Channel current M index */ 50 __IOM uint32_t CURR; /*!< 0x00000020 Channel current descriptor pointer */ 51 __IM uint32_t RESERVED1; 52 __IOM uint32_t TR_CMD; /*!< 0x00000028 Channel software trigger */ 53 __IM uint32_t RESERVED2[5]; 54 __IM uint32_t DESCR_STATUS; /*!< 0x00000040 Channel descriptor status */ 55 __IM uint32_t RESERVED3[3]; 56 __IM uint32_t DESCR_CTL; /*!< 0x00000050 Channel descriptor control */ 57 __IM uint32_t DESCR_SRC; /*!< 0x00000054 Channel descriptor source */ 58 __IM uint32_t DESCR_DST; /*!< 0x00000058 Channel descriptor destination */ 59 __IM uint32_t DESCR_M_SIZE; /*!< 0x0000005C Channel descriptor M size */ 60 __IM uint32_t DESCR_X_SIZE; /*!< 0x00000060 Channel descriptor X size */ 61 __IM uint32_t DESCR_X_INCR; /*!< 0x00000064 Channel descriptor X increment */ 62 __IM uint32_t DESCR_Y_SIZE; /*!< 0x00000068 Channel descriptor Y size */ 63 __IM uint32_t DESCR_Y_INCR; /*!< 0x0000006C Channel descriptor Y increment */ 64 __IM uint32_t DESCR_NEXT; /*!< 0x00000070 Channel descriptor next pointer */ 65 __IM uint32_t RESERVED4[3]; 66 __IOM uint32_t INTR; /*!< 0x00000080 Interrupt */ 67 __IOM uint32_t INTR_SET; /*!< 0x00000084 Interrupt set */ 68 __IOM uint32_t INTR_MASK; /*!< 0x00000088 Interrupt mask */ 69 __IM uint32_t INTR_MASKED; /*!< 0x0000008C Interrupt masked */ 70 __IM uint32_t RESERVED5[28]; 71 } AXI_DMAC_CH_Type; /*!< Size = 256 (0x100) */ 72 73 /** 74 * \brief AXI DMAC (AXI_DMAC) 75 */ 76 typedef struct { 77 __IOM uint32_t CTL; /*!< 0x00000000 Control */ 78 __IM uint32_t STATUS; /*!< 0x00000004 Enabled channels */ 79 __IM uint32_t ACTIVE_SEC; /*!< 0x00000008 Active secure channels */ 80 __IM uint32_t ACTIVE_NONSEC; /*!< 0x0000000C Active non-secure channels */ 81 __IM uint32_t RESERVED[1020]; 82 AXI_DMAC_CH_Type CH[8]; /*!< 0x00001000 AXI DMA controller channel */ 83 } AXI_DMAC_Type; /*!< Size = 6144 (0x1800) */ 84 85 86 /* AXI_DMAC_CH.CTL */ 87 #define AXI_DMAC_CH_CTL_P_Pos 0UL 88 #define AXI_DMAC_CH_CTL_P_Msk 0x1UL 89 #define AXI_DMAC_CH_CTL_NS_Pos 1UL 90 #define AXI_DMAC_CH_CTL_NS_Msk 0x2UL 91 #define AXI_DMAC_CH_CTL_B_Pos 2UL 92 #define AXI_DMAC_CH_CTL_B_Msk 0x4UL 93 #define AXI_DMAC_CH_CTL_PC_Pos 4UL 94 #define AXI_DMAC_CH_CTL_PC_Msk 0xF0UL 95 #define AXI_DMAC_CH_CTL_PRIO_Pos 8UL 96 #define AXI_DMAC_CH_CTL_PRIO_Msk 0x300UL 97 #define AXI_DMAC_CH_CTL_ENABLED_Pos 31UL 98 #define AXI_DMAC_CH_CTL_ENABLED_Msk 0x80000000UL 99 /* AXI_DMAC_CH.STATUS */ 100 #define AXI_DMAC_CH_STATUS_ENABLED_Pos 31UL 101 #define AXI_DMAC_CH_STATUS_ENABLED_Msk 0x80000000UL 102 /* AXI_DMAC_CH.IDX */ 103 #define AXI_DMAC_CH_IDX_X_Pos 0UL 104 #define AXI_DMAC_CH_IDX_X_Msk 0xFFFFUL 105 #define AXI_DMAC_CH_IDX_Y_Pos 16UL 106 #define AXI_DMAC_CH_IDX_Y_Msk 0xFFFF0000UL 107 /* AXI_DMAC_CH.SRC */ 108 #define AXI_DMAC_CH_SRC_ADDR_Pos 0UL 109 #define AXI_DMAC_CH_SRC_ADDR_Msk 0xFFFFFFFFUL 110 /* AXI_DMAC_CH.DST */ 111 #define AXI_DMAC_CH_DST_ADDR_Pos 0UL 112 #define AXI_DMAC_CH_DST_ADDR_Msk 0xFFFFFFFFUL 113 /* AXI_DMAC_CH.M_IDX */ 114 #define AXI_DMAC_CH_M_IDX_M_Pos 0UL 115 #define AXI_DMAC_CH_M_IDX_M_Msk 0xFFFFFFUL 116 /* AXI_DMAC_CH.CURR */ 117 #define AXI_DMAC_CH_CURR_PTR_Pos 3UL 118 #define AXI_DMAC_CH_CURR_PTR_Msk 0xFFFFFFF8UL 119 /* AXI_DMAC_CH.TR_CMD */ 120 #define AXI_DMAC_CH_TR_CMD_ACTIVATE_Pos 0UL 121 #define AXI_DMAC_CH_TR_CMD_ACTIVATE_Msk 0x1UL 122 /* AXI_DMAC_CH.DESCR_STATUS */ 123 #define AXI_DMAC_CH_DESCR_STATUS_VALID_Pos 31UL 124 #define AXI_DMAC_CH_DESCR_STATUS_VALID_Msk 0x80000000UL 125 /* AXI_DMAC_CH.DESCR_CTL */ 126 #define AXI_DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL 127 #define AXI_DMAC_CH_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL 128 #define AXI_DMAC_CH_DESCR_CTL_INTR_TYPE_Pos 2UL 129 #define AXI_DMAC_CH_DESCR_CTL_INTR_TYPE_Msk 0xCUL 130 #define AXI_DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Pos 4UL 131 #define AXI_DMAC_CH_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL 132 #define AXI_DMAC_CH_DESCR_CTL_TR_IN_TYPE_Pos 6UL 133 #define AXI_DMAC_CH_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL 134 #define AXI_DMAC_CH_DESCR_CTL_DATA_PREFETCH_Pos 8UL 135 #define AXI_DMAC_CH_DESCR_CTL_DATA_PREFETCH_Msk 0x100UL 136 #define AXI_DMAC_CH_DESCR_CTL_CH_DISABLE_Pos 24UL 137 #define AXI_DMAC_CH_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL 138 #define AXI_DMAC_CH_DESCR_CTL_DESCR_TYPE_Pos 28UL 139 #define AXI_DMAC_CH_DESCR_CTL_DESCR_TYPE_Msk 0x30000000UL 140 /* AXI_DMAC_CH.DESCR_SRC */ 141 #define AXI_DMAC_CH_DESCR_SRC_ADDR_Pos 0UL 142 #define AXI_DMAC_CH_DESCR_SRC_ADDR_Msk 0xFFFFFFFFUL 143 /* AXI_DMAC_CH.DESCR_DST */ 144 #define AXI_DMAC_CH_DESCR_DST_ADDR_Pos 0UL 145 #define AXI_DMAC_CH_DESCR_DST_ADDR_Msk 0xFFFFFFFFUL 146 /* AXI_DMAC_CH.DESCR_M_SIZE */ 147 #define AXI_DMAC_CH_DESCR_M_SIZE_M_COUNT_Pos 0UL 148 #define AXI_DMAC_CH_DESCR_M_SIZE_M_COUNT_Msk 0xFFFFFFUL 149 /* AXI_DMAC_CH.DESCR_X_SIZE */ 150 #define AXI_DMAC_CH_DESCR_X_SIZE_X_COUNT_Pos 0UL 151 #define AXI_DMAC_CH_DESCR_X_SIZE_X_COUNT_Msk 0xFFFFUL 152 /* AXI_DMAC_CH.DESCR_X_INCR */ 153 #define AXI_DMAC_CH_DESCR_X_INCR_SRC_X_Pos 0UL 154 #define AXI_DMAC_CH_DESCR_X_INCR_SRC_X_Msk 0xFFFFUL 155 #define AXI_DMAC_CH_DESCR_X_INCR_DST_X_Pos 16UL 156 #define AXI_DMAC_CH_DESCR_X_INCR_DST_X_Msk 0xFFFF0000UL 157 /* AXI_DMAC_CH.DESCR_Y_SIZE */ 158 #define AXI_DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Pos 0UL 159 #define AXI_DMAC_CH_DESCR_Y_SIZE_Y_COUNT_Msk 0xFFFFUL 160 /* AXI_DMAC_CH.DESCR_Y_INCR */ 161 #define AXI_DMAC_CH_DESCR_Y_INCR_SRC_Y_Pos 0UL 162 #define AXI_DMAC_CH_DESCR_Y_INCR_SRC_Y_Msk 0xFFFFUL 163 #define AXI_DMAC_CH_DESCR_Y_INCR_DST_Y_Pos 16UL 164 #define AXI_DMAC_CH_DESCR_Y_INCR_DST_Y_Msk 0xFFFF0000UL 165 /* AXI_DMAC_CH.DESCR_NEXT */ 166 #define AXI_DMAC_CH_DESCR_NEXT_PTR_Pos 3UL 167 #define AXI_DMAC_CH_DESCR_NEXT_PTR_Msk 0xFFFFFFF8UL 168 /* AXI_DMAC_CH.INTR */ 169 #define AXI_DMAC_CH_INTR_COMPLETION_Pos 0UL 170 #define AXI_DMAC_CH_INTR_COMPLETION_Msk 0x1UL 171 #define AXI_DMAC_CH_INTR_SRC_BUS_ERROR_Pos 1UL 172 #define AXI_DMAC_CH_INTR_SRC_BUS_ERROR_Msk 0x2UL 173 #define AXI_DMAC_CH_INTR_DST_BUS_ERROR_Pos 2UL 174 #define AXI_DMAC_CH_INTR_DST_BUS_ERROR_Msk 0x4UL 175 #define AXI_DMAC_CH_INTR_INVALID_DESCR_TYPE_Pos 3UL 176 #define AXI_DMAC_CH_INTR_INVALID_DESCR_TYPE_Msk 0x8UL 177 #define AXI_DMAC_CH_INTR_CURR_PTR_NULL_Pos 5UL 178 #define AXI_DMAC_CH_INTR_CURR_PTR_NULL_Msk 0x20UL 179 #define AXI_DMAC_CH_INTR_ACTIVE_CH_DISABLED_Pos 6UL 180 #define AXI_DMAC_CH_INTR_ACTIVE_CH_DISABLED_Msk 0x40UL 181 #define AXI_DMAC_CH_INTR_DESCR_BUS_ERROR_Pos 7UL 182 #define AXI_DMAC_CH_INTR_DESCR_BUS_ERROR_Msk 0x80UL 183 /* AXI_DMAC_CH.INTR_SET */ 184 #define AXI_DMAC_CH_INTR_SET_COMPLETION_Pos 0UL 185 #define AXI_DMAC_CH_INTR_SET_COMPLETION_Msk 0x1UL 186 #define AXI_DMAC_CH_INTR_SET_SRC_BUS_ERROR_Pos 1UL 187 #define AXI_DMAC_CH_INTR_SET_SRC_BUS_ERROR_Msk 0x2UL 188 #define AXI_DMAC_CH_INTR_SET_DST_BUS_ERROR_Pos 2UL 189 #define AXI_DMAC_CH_INTR_SET_DST_BUS_ERROR_Msk 0x4UL 190 #define AXI_DMAC_CH_INTR_SET_INVALID_DESCR_TYPE_Pos 3UL 191 #define AXI_DMAC_CH_INTR_SET_INVALID_DESCR_TYPE_Msk 0x8UL 192 #define AXI_DMAC_CH_INTR_SET_CURR_PTR_NULL_Pos 5UL 193 #define AXI_DMAC_CH_INTR_SET_CURR_PTR_NULL_Msk 0x20UL 194 #define AXI_DMAC_CH_INTR_SET_ACTIVE_CH_DISABLED_Pos 6UL 195 #define AXI_DMAC_CH_INTR_SET_ACTIVE_CH_DISABLED_Msk 0x40UL 196 #define AXI_DMAC_CH_INTR_SET_DESCR_BUS_ERROR_Pos 7UL 197 #define AXI_DMAC_CH_INTR_SET_DESCR_BUS_ERROR_Msk 0x80UL 198 /* AXI_DMAC_CH.INTR_MASK */ 199 #define AXI_DMAC_CH_INTR_MASK_COMPLETION_Pos 0UL 200 #define AXI_DMAC_CH_INTR_MASK_COMPLETION_Msk 0x1UL 201 #define AXI_DMAC_CH_INTR_MASK_SRC_BUS_ERROR_Pos 1UL 202 #define AXI_DMAC_CH_INTR_MASK_SRC_BUS_ERROR_Msk 0x2UL 203 #define AXI_DMAC_CH_INTR_MASK_DST_BUS_ERROR_Pos 2UL 204 #define AXI_DMAC_CH_INTR_MASK_DST_BUS_ERROR_Msk 0x4UL 205 #define AXI_DMAC_CH_INTR_MASK_INVALID_DESCR_TYPE_Pos 3UL 206 #define AXI_DMAC_CH_INTR_MASK_INVALID_DESCR_TYPE_Msk 0x8UL 207 #define AXI_DMAC_CH_INTR_MASK_CURR_PTR_NULL_Pos 5UL 208 #define AXI_DMAC_CH_INTR_MASK_CURR_PTR_NULL_Msk 0x20UL 209 #define AXI_DMAC_CH_INTR_MASK_ACTIVE_CH_DISABLED_Pos 6UL 210 #define AXI_DMAC_CH_INTR_MASK_ACTIVE_CH_DISABLED_Msk 0x40UL 211 #define AXI_DMAC_CH_INTR_MASK_DESCR_BUS_ERROR_Pos 7UL 212 #define AXI_DMAC_CH_INTR_MASK_DESCR_BUS_ERROR_Msk 0x80UL 213 /* AXI_DMAC_CH.INTR_MASKED */ 214 #define AXI_DMAC_CH_INTR_MASKED_COMPLETION_Pos 0UL 215 #define AXI_DMAC_CH_INTR_MASKED_COMPLETION_Msk 0x1UL 216 #define AXI_DMAC_CH_INTR_MASKED_SRC_BUS_ERROR_Pos 1UL 217 #define AXI_DMAC_CH_INTR_MASKED_SRC_BUS_ERROR_Msk 0x2UL 218 #define AXI_DMAC_CH_INTR_MASKED_DST_BUS_ERROR_Pos 2UL 219 #define AXI_DMAC_CH_INTR_MASKED_DST_BUS_ERROR_Msk 0x4UL 220 #define AXI_DMAC_CH_INTR_MASKED_INVALID_DESCR_TYPE_Pos 3UL 221 #define AXI_DMAC_CH_INTR_MASKED_INVALID_DESCR_TYPE_Msk 0x8UL 222 #define AXI_DMAC_CH_INTR_MASKED_CURR_PTR_NULL_Pos 5UL 223 #define AXI_DMAC_CH_INTR_MASKED_CURR_PTR_NULL_Msk 0x20UL 224 #define AXI_DMAC_CH_INTR_MASKED_ACTIVE_CH_DISABLED_Pos 6UL 225 #define AXI_DMAC_CH_INTR_MASKED_ACTIVE_CH_DISABLED_Msk 0x40UL 226 #define AXI_DMAC_CH_INTR_MASKED_DESCR_BUS_ERROR_Pos 7UL 227 #define AXI_DMAC_CH_INTR_MASKED_DESCR_BUS_ERROR_Msk 0x80UL 228 229 230 /* AXI_DMAC.CTL */ 231 #define AXI_DMAC_CTL_ENABLED_Pos 31UL 232 #define AXI_DMAC_CTL_ENABLED_Msk 0x80000000UL 233 /* AXI_DMAC.STATUS */ 234 #define AXI_DMAC_STATUS_CH_EN_Pos 0UL 235 #define AXI_DMAC_STATUS_CH_EN_Msk 0xFFUL 236 /* AXI_DMAC.ACTIVE_SEC */ 237 #define AXI_DMAC_ACTIVE_SEC_ACTIVE_Pos 0UL 238 #define AXI_DMAC_ACTIVE_SEC_ACTIVE_Msk 0xFFUL 239 /* AXI_DMAC.ACTIVE_NONSEC */ 240 #define AXI_DMAC_ACTIVE_NONSEC_ACTIVE_Pos 0UL 241 #define AXI_DMAC_ACTIVE_NONSEC_ACTIVE_Msk 0xFFUL 242 243 244 #endif /* _CYIP_AXI_DMAC_H_ */ 245 246 247 /* [] END OF FILE */ 248
